NVMe : Redefining the Hardware/Software Architecture

Transcription

1 NVMe : Redefining the Hardware/Software Architecture Jérôme Gaysse, IP-Maker Santa Clara, CA 1

2 NVMe Protocol How to implement the NVMe protocol? SW, HW/SW or HW? 2- NVMe command ready CPU 1-Host driver Setup root complex 3- NVMe command submission fetch Phy + Ctrl NVMe IP 4- Data transfer 5- NVMe command executed Santa Clara, CA 2

3 Software implementation Architecture SSD Controller Embedded processor Interface Flash Controller NandFlash Controller Santa Clara, CA 3

4 Software implementation Latency CPU at 2GHz 10,000 clock cycles per IO => 5µs Power =>60pJ/bit NVMe latency Media latency Santa Clara, CA 4

5 HW/SW NVMe IP architecture Automatic command processing => Low latency Multi-channel => IOPS acceleration Configuration & System Automatic Command Processing AXI Configuration Registers Queue Context Manager Queue Arbiter AXI Embedded Processor Interface Async Event Error Logs Command Manager AXI Multi-Channel Read s Write s AXI Data Interface Flash Memory Summit 2014 Santa Clara, CA 5

6 Hardware/Software implementation Architecture SSD Controller Flexibility support NVMe firmware Embedded processor Optional IPM-NVMe Interface Automatic Command Processing Nandflash Controller ECC BCH NandFlash IOPS acceleration Low latency Controller Santa Clara, CA 6

7 Hardware/Software implementation Latency Digital Clock = 250MHz 40 cycles CPU at 2GHz 2000 clock cycles per IO => 1.1µs Power =>15pJ/bit NVMe latency Media latency Santa Clara, CA 7

8 Hardware implementation Architecture Device hard IP controller soft IP IPM-NVMe Interface Bridge Automatic Command Processing Bridge 3 Controller 3 7-series Xilinx FPGA 7-series Xilinx evaluation kit Santa Clara, CA 8

9 Hardware implementation Latency FPGA Clock = 250MHz 80 cycles => 320ns Power 6pJ/bit NVMe latency Media latency Santa Clara, CA 9

10 Implementation Summary SW HW/SW HW Latency 5µs 1.3µs 320ns Energy 60pJ/bit 15pJ/bit 6pJ/bit NVMe latency Media latency Santa Clara, CA 10

11 How to benefit from this improved latency and power consumption? Adding features for the same power budget Smart FTL Protocole management for HBA Improve the overall system power efficiency Flash Memory Summit 2014 Santa Clara, CA 11

12 Hardware/Software implementation Application example : SSD Host NVMe Linux driver SSD Controller Smart FTL Embedded processor IPM-NVMe CPU Interface Automatic Command Processing Nandflash Controller ECC BCH NandFlash Controller Santa Clara, CA 12

13 Hardware/Software implementation Application example : HBA Host SSD Controller NVMe Linux driver Embedded processor CPU Interface IPM-NVMe Automatic Command Processing SATA Eth Controller Santa Clara, CA 13

14 Hardware implementation Application example : NV-RAM Drive Drive Latency: 5-7µs Santa Clara, CA 14

15 Hardware implementation Application example : SSD with NG-NVM Host SSD Controller NVMe Linux driver IPM-NVMe CPU Interface Automatic Command Processing NVM Controller SSD Latency: <10µs Santa Clara, CA 15 NVM

16 Conclusion Benefits of a software/hardware NVMe architecture Excellent power/feature tradeoff Allow new NVMe applications Benefits of a hardware NVMe architecture: Less power and lower latency Ready for NG-NVM Santa Clara, CA 16

17 Thanks! Visit IP-Maker booth #717 NVMe live demo! Flash Memory Summit 2014 Santa Clara, CA 17