The Tic-Tac-Toe Game with the NST (Not-So-Tiny) CPU Introduction

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Erika Singleton
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1 The Tic-Tac-Toe Game with the NST (Not-So-Tiny) CPU Introduction The entire project file can be downloaded from the ELE405 FTP site as TTT2.ZIP (needless to say that this is version 2 of the TTT line). Although a simple project, many different parts need to interact with each other flawlessly. Conversely, you will need to understand ALL parts before you can even start to comprehend how everything works together here. Fortunately, you may choose to merely pick a part of this project and concentrate on it. For example, you may study only the CPU part or just the memory interface part or the I/O port design, or even the LED and Key scanning design (if you have keyboard in your project!). The ISA of this CPU has been discussed in length in the class. The only exception is that the HLT (halt CPU) instruction has been replaced by RST (reset CPU) instruction. You will also note that the control unit design is really not much different from the Tiny CPU s control unit. NOTE: The similarity between the two control units was due to the fact that they were designed by the same designer! You should NOT interpret this as it is the only approach to control unit design. The memory and I/O interfaces to the CPU were quite standard and is almost identical to the TINY CPU example. In this case, the main memory consists of 3 ROMs and 1 RAM. The program are stored in the ROMs and most of the RAM. The RAM is needed since I need to store some vital variable in the main memory (see the last three lines of the program listing). A segment of the memory was designated as the LED RAM (sort of like Video RAM). You may find this in the I/O block. This LED RAM was implemented as a dual-port RAM (with two data read-out ports and one data write-in port) and holds only two bits: one for the red LED s and the other for the green LED s. While the CPU have access to the write and one of the read ports, the second read port is controlled by a simple sequential circuit. This sequential circuit continuously scans the 9 locations in the LED RAM. The timing signals X-scan (XS2, XS1, and XS0) and Y- scan (YS2, YS1, YS0) are generated from two set of ring counters. The scan pattern is then converted to the LED RAM address. At the output end, the X-scan signals are used again to synchronize the LED signals to the correct column (see also the circuit on the next page). The key scan uses the same X and Y scan signals from above. Each column key scan input (SI2, SI1, and SI0) has its own de-bounce circuit. You may check the macro and find the design of the de-bounce circuit is simply to delay the acceptance of a key input until the key press has been stabilized for at least three fast cycles (the fast cycle is several times faster then the scan cycle). After a key input is accepted, it is stored in a temporary register. This register can be read by the CPU as if an I/O input port and is connected directly to the 7-segment LED display. At first, I planned to design it so the register is reset after the register s content has been read by the CPU. At the end, instead, I wrote the program so the same key input will be ignored. Another special can be found in the macro KEY_SCAN. When a key press is identified, three F/F s were used to lock-on to the current Y-scan signals. This is necessary to ensure that the correct key code is clocked in to the register. You might have noticed that the main circuit of this project has been spread out in two sheets. The Xilinx s software employs a feature called connected by name : any two wires (or nets) with the same name are connected. Therefore, circuits on both sheets are connected simply by given the nets or buses the proper names.

2 Finally, this project has been built hierarchically with many layers of macros. If you decide to design your project this way, you must make sure that each macro is 100% OK. The problem may arise when you debug the entire project. As you might have discover in Lab 5 exercises, signals in the lower level macros may not be easy (or reliably) monitored in simulations. I would suggest use only the macros you are 100% sure and put the rest of the circuit in the same hierarchical level spreading over several schematic sheets using the connected by name feature. I/O Addresses: LED RAM: $F1 to $F9; bit0=red, bit1=green; $F0 was implemented but unused. R/G: $FF output at bit0 Key Code: $FF input 4-bit (1-9) Circuits in the BOX: RX0 GX0 RX1 GX1 RX2 GX2 Vcc=+3.3V YS YS YS0 Vcc=+3.3V SI0 SI1 SI2 Reset R/G Reset (3) VCC (54) YS2 (4) RX2 (10) YS1 (5) RX1 (13) YS0 (6) RX0 (14) SI2 (7) GX0 (15) SI1 (8) GX1 (16) SI0 (9) GX0 (17) GND (52) R/G (84)

3 Tic-Tac-Toe Program Listing Adr. Machine Code Prog Comments 00 90, 00 RST: MOV R0, #00 ;initialization 02 94, 01 MOV R1, #01 ;clear all LED s 04 98, 09 MOV R2, # C, F0 CLEAR: MOV R3, #F0 ;LED base address 08 1E ADD R3, R2 ;inc address 09 E3 STR R0, $(R3) 0A 29 SUB R2, R1 ;dec count 0B 60, 06 JNZ CLEAR 0D 9C, 01 MOV R3, #01 ;Red s turn first 0F DC, FF AGAIN: STR R3, $FF ;set new R/G 11 A4, FF LOOP: MOV R1, $FF ;read in KEY 13 98, 00 MOV R2, # ADD R1, R2 ;test if zero 16 60, 1A JNZ NEXT 18 80, 11 JMP LOOP 1A 98, F0 NEXT: MOV R2, #F0 ;convert KEY no. 1C 19 ADD R2, R1 ;to LED address 1D B6 MOV R1, $(R2) 1E C2 MOV R0, R2 ;LED address in R0 1F 98, 00 MOV R2, # ADD R1, R , 11 JNZ LOOP ;already taken 24 EC VALID: STR R3, $(R0) ;place new entry ;Checking For a Potential win 25 94, F1 ONE: MOV R1, #F1 ;look for B1 MOV R0, $(R1) SUB R0, R , 5D JNZ FIVE 2B D4, ED STR R1, $W1 ;first wining no. =1 2D 94, F4 MOV R1, #F4 2F B1 MOV R0, $(R1) SUB R0, R , 3D JNZ ONEA 33 D4, EE STR R1, $W2 ;second no. = , F7 MOV R1, #F7 ;third no. =7 37 B1 MOV R0, $(R1) SUB R0, R , 5D JNZ FIVE 3B 80, C9 JMP WIN ;declare winner 3D 94, F5 ONEA: MOV R1, #F5 ;first no.=1 3F B1 MOV R0, $(R1) ;looking for SUB R0, R , 4D JNZ ONEB 43 D4, EE STR R1, $W2 ;second no. = , F9 MOV R1, #F9 ;third no. =9 47 B1 MOV R0, $(R1) SUB R0, R , 5D JNZ FIVE 4B 80, CA JMP WIN

4 4D 94, F3 ONEB: MOV R1, #F3 ;first no.=1 4F B1 MOV R0, $(R1) ;look for SUB R0, R , 5D JNZ FIVE 53 D4, EE STR R1, $W2 ;second no. = , F2 MOV R1, #F2 ;third no. =2 57 B1 MOV R0, $(R1) SUB R0, R , 5D JNZ FIVE 5B 80, CA JMP WIN 5D 94, F5 FIVE: MOV R1, #F5 ;look for F B1 MOV R0, $(R1) SUB R0, R , 95 JNZ SEV 63 D4, ED STR R1, $W1 ;first no. = , F4 MOV R1, #F4 67 B1 MOV R0, $(R1) SUB R0, R , 75 JNZ FIVEA 6B D4, EE STR R1, $W2 ;second no. =4 6D 94, F6 MOV R1, #F6 ;third no. =6 6F B1 MOV R0, $(R1) SUB R0, R , 95 JNZ SEV 73 80, CA JMP WIN 75 94, F8 FIVEA: MOV R1, #F8 ;first no. =5 77 B1 MOV R0, $(R1) ;look for SUB R0, R , 85 JNZ FIVEB 7B D4, EE STR R1, $W2 ;second no. =8 7D 94, F2 MOV R1, #F2 ;third no. =2 7F B1 MOV R0, $(R1) SUB R0, R , 95 JNZ SEV 83 80, C9 JMP WIN 85 94, F3 FIVEB: MOV R1, #F3 ;first no.=5 87 B1 MOV R0, $(R1) ;look for SUB R0, R , 95 JNZ SEV 8B D4, EE STR R1, $W2 ;second no =3 8D 94, F7 MOV R1, #F7 ;third no. =7 8F B1 MOV R0, $(R1) SUB R0, R , 95 JNZ SEV 93 80, CA JMP WIN 95 94, F9 SEV: MOV R1, #F9 ;look for B1 MOV R0, $(R1) SUB R0, R , BD JNZ NOWIN 9B D4, ED STR R1, $W1 ;first no. =9 9D 94, F8 MOV R1, #F8 9F B1 MOV R0, $(R1) A0 23 SUB R0, R3

5 A1 60, AD JNZ SEVA A3 D4, EE STR R1, $W2 ;second no. =8 A5 94, F7 MOV R1, #F7 A7 B1 MOV R0, $(R1) A8 23 SUB R0, R3 A9 60, BD JNZ NOWIN AB 80, CA JMP WIN ;third no. =7 AD 94, F3 SEVA: MOV R1, #F3 ;first no. =9 AF B1 MOV R0, $(R1) ;look for B0 23 SUB R0, R3 B1 60, BD JNZ NOWIN B3 D4, EE STR R1, $W2 ;second no. =3 B5 94, F6 MOV R1, #F6 B7 B1 MOV R0, $(R1) B8 23 SUB R0, R3 B9 60, BD JNZ NOWIN BB 80, CA JMP WIN ;third no. =6 BD 98, FE NOWIN MOV R2, #FE BF 3E AND R3, R2 C0 60, C6 JNZ TOR C2 9C, 02 MOV R3, #02 C4 80, 0F JMP AGAIN C6 9C, 01 TOR: MOV R3, #01 C8 80, 0F JMP AGAIN ;Winning flash Routine CA D4, EF WIN: STR R1, $W3 CC 98, 00 DD: MOV R2, #00 ;blank CE A4, ED MOV R1, $W1 D0 E9 STR R2, $(R1) D1 A4, EE MOV R1, $W2 D3 E9 STR R2, $(R1) D4 A4, EF MOV R1, $W3 D6 E9 STR R2, $(R1) D7 94, 01 MOV R1, #01 D9 29 D1: SUB R2, R1 DA 60, D9 JNZ D1 DC A4, ED MOV R1, $W1 ;light up DE ED STR R3, $(R1) DF A4, EE MOV R1, $W2 E1 ED STR R3, $(R1) E2 A4, EF MOV R1, $W3 E4 ED STR R3, $(R1) E5 94, 01 MOV R1, #01 E7 29 D2: SUB R2, R1 E8 60, E7 JNZ D2 EA 80, CC JMP DD ;repeat ED W1: ;first win no. EE W2: ;second win no. EF W3: ;third win no.

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