Connecting Spansion SPI Serial Flash to Configure Altera FPGAs

Transcription

1 Connecting SPI Serial Flash to Configure Altera s Application By Frank Cirimele 1. Introduction Altera s are programmable logic devices used for basic logic functions, chip-to-chip connectivity, signal processing, and embedded processing. These devices are programmed and configured using an array of SRAM cells that need to be re-programmed on every power-up. Several different methods of configuring s are normally used. They include programming by a microprocessor, JTAG port, or directly by a serial PROM or Flash. 's SPI (Serial Peripheral Interface) Flash can be easily connected to Altera s in order to configure the at power-up. The SPI configuration mode is supported for Altera Cyclone, Cyclone II, Cyclone III, Stratix II, Stratix II GX, Stratix III, and Arria GX families. 2. SPI Basics Serial Peripheral Interface is a simple 4-wire synchronous interface protocol which enables a master device and one or more slave devices to intercommunicate. The SPI bus consists of 4 signal wires: Master Out Slave In (MO) signal generated by the master (data to slave) Master In Slave Out (MI) signal generated by the slave (data to master) Serial Clock () signal generated by the master to synchronize data transfers Slave Select (SS) signal generated by master to select individual slave devices also known as Chip Select (CS) or Chip Enable (CE) In this application note, the is the master device, and the SPI serial flash to configure the is the slave device as seen in Figure 2.1. Figure 2.1 Direct Configuring Interface with Master device MI MO /SS Slave 3. Connections to s Figure 3.1 displays a simplified block diagram of the connection between and Altera. It shows the SPI interface between Altera and, as well as the headers for direct (in-system) and JTAG programming the for configuration data updates from a PC or embedded host. Altera calls their SPI interface the Active Serial (AS) configuration interface. Publication Number Configuring_Altera_s_via_SPI_Flash_AN Revision 01 Issue Date February 20, 2008

2 Figure 3.1 Block diagram of Configuration Interface with Re-programming Capability Header for JTAG Programming PC Altera AS Interface Header for Direct (ISP) Programming PC The following is a detailed explanation of connections between Altera and. The connections to the Cyclone, Stratix, and Arria family devices with direct (ISP) programming only are shown in Figures 3.2 through 3.5, while the connections for both direct and JTAG programming capability are shown in Figures 3.6 through 3.9. Signal connections to the 10-pin male headers for ISP and JTAG programming are provided in Table 3.1. Altera USB Blaster, MasterBlaster, ByteBlaster II or MasterBlasterMV download cables are available to program the embedded with configuration data updates, connected to either the ISP (AS mode) or JTAG headers. Signal descriptions are listed in Table 3.2. The supplies the output from its internal oscillator to drive the clock input of. Logic levels and voltage connections for the Select (MSEL) pins for each Altera family are listed in Table 3.3. The Select pins have internal pull-down resistors that are always active. Table 3.4 through Table 3.10 show the smallest devices required for typical configuration bit requirements of different members of the Cyclone, Stratix, and Arria families. 2 Configuring_Altera_s_via_SPI_Flash_AN_01 February 20, 2008

3 Figure 3.2 Cyclone/Cyclone II Configuration from SPI Serial Flash Connection Header for 3.3V VCC Cyclone Cyclone II +3.3V CS# Figure 3.3 Cyclone III Configuration from SPI Serial Flash Connection Header for VCCIO MSEL3 MSEL2 VCCINT Cyclone III VCCIO +3.3V CS# Forward-biased diodes are connected from each SPI signal line to VCCIO, and 10 pf capacitors are connected from each SPI signal line to GND. Place these components as close as possible to the. February 20, 2008 Configuring_Altera_s_via_SPI_Flash_AN_01 3

4 Figure 3.4 Stratix II/Stratix II GX/Arria GX Configuration from SPI Serial Flash Connection Header for 3.3V VCC MSEL3 MSEL2 Stratix II Stratix II GX Arria GX +3.3V CS# Figure 3.5 Stratix III Configuration from SPI Serial Flash Connection Header for 3.0V VCC MSEL2 Stratix III +3.0V CS# 4 Configuring_Altera_s_via_SPI_Flash_AN_01 February 20, 2008

5 Figure 3.6 Cyclone/Cyclone II Configuration with Both ISP and JTAG Programming Capability Header for JTAG Programming (1) (1) 1KΩ TMS TDI TDO TCK Cyclone Cyclone II Header for CS# s: (1) Resistor value is for Cyclone devices and 1 KΩ for Cyclone II devices. Figure 3.7 Cyclone III Configuration with Both ISP and JTAG Programming Capability Header for JTAG Programming A 1KΩ TMS TDI TDO TCK MSEL3 MSEL2 VCCIO VCCINT VCCA Cyclone III IO Header for +3.3V CS# Forward-biased diodes are connected from each SPI signal line to VCCIO, and 10 pf capacitors are connected from each SPI signal line to GND. Place these components as close as possible to the. Figure 8: Cyclone III Configuration with Both ISP and JTAG Programming Capability February 20, 2008 Configuring_Altera_s_via_SPI_Flash_AN_01 5

6 Figure 3.8 Stratix II/Stratix II GX/Arria GX Configuration with Both ISP and JTAG Programming Capability Header for JTAG Programming 1KΩ TMS TDI TDO TCK MSEL3 MSEL2 TRST VCC Stratix II Stratix II GX Arria GX Header for CS# +3.3V Figure 3.9 Stratix III Configuration with Both ISP and JTAG Programming Capability Header for JTAG Programming 1KΩ TMS TDI TDO TCK MSEL2 TRST Stratix III VCC Header for +3.0V CS# Figure 10: Stratix III Configuration with Both ISP and JTAG Programming Capability Figure 3.10 Pin Orientation for 10-Pin Male Header Configuring_Altera_s_via_SPI_Flash_AN_01 February 20, 2008

7 Table 3.1 Pin Assignments for Direct and JTAG Programming Headers Pin Direct Programming JTAG Programming 1 / TCK 2 GND GND 3 TDO 4 VCC (1) VCC (2) 5 TMS 6 VIO (3) 7 / 8 ncs0/cs# 9 / TDI 10 GND GND s: 1. Connect the download cable power pin to the same voltage used for the pull-up resistors connected to the direct programming header. 2. Connect the download cable power pin to the same voltage used for the pull-up resistors connected to the JTAG programming header. 3. VIO is a reference voltage for the output driver of the MasterBlaster download cable. For the ByteBlasterMV cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to when the JTAG interface is used for active serial programming, otherwise this pin is a no connect. Table 3.2 Pin Descriptions for Configuration from Pin Name Type Description MSEL[1:0] MSEL[2:0] MSEL[3:0] Input Input Input Cyclone / Cyclone II Stratix III Cyclone III / Stratix II / Arria GX Input All families Open-drain, bidirect. I/O All families Pins. Selects configuration scheme. These input pins must be hardwired to VCC or GND. These pins have internal pull-down resistors that are always active. Configuration Control. Pulling pin low during user-mode will cause the to lose its configuration data, enter a reset state, and tristate all its I/O pins. Transitioning this pin high will start a reconfiguration. nstatus I/O. The device drives low immediately after power-up and releases it after the Power-On Reset time. Status output. If an error occurs during configuration, is pulled low by the target device. Status input. If an external source drives the pin low during configuration or initialization, the target device enters an error state. Driving low after configuration and initialization does not affect the configured device. February 20, 2008 Configuring_Altera_s_via_SPI_Flash_AN_01 7

8 Table 3.2 Pin Descriptions for Configuration from Pin Name Type Description Open-drain, bidirect. I/O All families Input All families Output All families Input All families Output All families Output All families Output All families TDI Input All families TDO Output All families TMS Input All families Status I/O. Status output. The target device drives the pin low before and during configuration. Once the device receives all its configuration data without error and the initialization cycle begins, the output is released by the device. Status input. This pin must have an external pull-up resistor in order for the device to initialize. After the device receives all its configuration data, the pin transitions high and the device initializes and enters user mode. Device configuration is unaffected by being driven low after configuration and initialization has completed. Active-Low Chip Enable. A low signal to enables the device for configuration. must be held low during configuration, initialization and user mode. Tie this pin low with a pull-down resistor. Cascade Chip Enable. Used to cascade to pin of next device in multi-device configuration. In single-device configuration, this pin is left floating. Data Input. Serial configuration data from the SPI Flash device is presented to the target device on the pin in AS mode. After configuration, is available as a user I/O pin. This pin has an internal pull-up resistor that is always active. Data Output. Control signal from the target device in AS mode to the device used to read out configuration data. In AS mode, has an internal pull-up resistor that is always active. Data Clock. In AS mode, provides the synchronous timing to for sending configuration data to target device. It has an internal pull-up resistor that is always active. Chip Select Output. Enables the Chip Select input to send configuration data. It has an internal pull-up resistor that is always active. JTAG Test Data Input. Input instructions as well as test and programming data serially. Data is shifted in on the rising edge of TCK. If the JTAG interface is not required, then connect this pin to Vcc to disable the JTAG circuitry. JTAG Test Data Output. Output instructions as well as test and programming data serially. Data is shifted out on the falling edge of TCK. If the JTAG interface is not required, then leave this pin unconnected to disable the JTAG circuitry. JTAG Test Select. Provides the control signal to determine transitions of the TAP controller state machine. TMS transitions occur on the rising edge of TCK. If the JTAG interface is not required, then connect this pin to Vcc to disable the JTAG circuitry. 8 Configuring_Altera_s_via_SPI_Flash_AN_01 February 20, 2008

9 Table 3.2 Pin Descriptions for Configuration from Pin Name Type Description TCK Input All families TRST Input Stratix families JTAG Test Clock. Provides the clock to the boundary scan circuitry. Operations occur on both edges of the clock. If the JTAG interface is not required, then connect this pin to GND to disable the JTAG circuitry. JTAG Test Reset. Provide an active-low input to asynchronously reset the boundary-scan circuitry. This pin is optional according to IEEE Std If the JTAG interface is not required, then connect this pin to GND to disable the JTAG circuitry. Table 3.3 Logic Level and Voltage Connections for Select Pins Family Stratix III Stratix II Stratix II GX / Arria GX Cyclone III Cyclone II Cyclone Configuration Scheme Fast AS (40 MHz) AS (20 MHz) Fast AS (40 MHz) AS (20 MHz) Fast AS (40 MHz) AS (20 MHz) Fast AS (40 MHz) AS (20 MHz) Select Pin Applied Logic Level Voltage Connections MSEL MSEL3 1 MSEL MSEL3 1 MSEL MSEL3 0 MSEL MSEL3 1 MSEL Logic 1: VCCPGM Logic 0: GND Logic 1: VCCPD Logic 0: GND Logic 1: VCCA Logic 0: GND Logic 1: VCCIO Logic 0: GND Logic 0: GND Table 3.4 for Stratix III Family Devices # of Configuration Bits 1 Minimum Device 2 EP3SL50 22,000, Mb/16 Mb EP3SL70 22,000, Mb/16 Mb February 20, 2008 Configuring_Altera_s_via_SPI_Flash_AN_01 9

10 Table 3.4 for Stratix III Family Devices # of Configuration Bits 1 Minimum Device 2 EP3SL110 47,000, Mb/32 Mb EP3SL150 47,000, Mb/32 Mb EP3SL200 66,000, Mb/64 Mb EP3SL260 93,000, Mb/64 Mb EP3SL ,000, Mb/128 Mb EP3SE50 26,000, Mb/32 Mb EP3SE80 48,000, Mb/32 Mb EP3SE110 48,000, Mb/32 Mb s: 1. Preliminary data values from Altera. 2. Device sizes are for uncompressed/compressed data files, which assumes a minimum 35% reduction in data size due to compression. Table 3.5 for Stratix II GX Family Devices # of Configuration Bits 1 Minimum Device 2 EP2GX30C/D 9,640, Mb/8 Mb EP2GX60C/D/E 16,951, Mb/16 Mb EP2GX90E/F 25,699, Mb/16 Mb EP2GX130G 37,325, Mb/32 Mb s: 1. Final data values from Altera. 2. Device sizes are for uncompressed/compressed data files, which assumes a minimum 35% reduction in data size due to compression. Table 3.6 for Stratix II Family Devices # of Configuration Bits 1 Minimum Device 2 EP2S15 4,721,544 8 Mb/4 Mb EP2S30 9,640, Mb/8 Mb EP2S60 16,951, Mb/16 Mb EP2S90 25,699, Mb/16 Mb EP2S130 37,325, Mb/32 Mb EP2S180 49,814, Mb/32 Mb s: 1. Final data values from Altera. 2. Device sizes are for uncompressed/compressed data files, which assumes a minimum 35% reduction in data size due to compression. s: 1. Preliminary data values from Altera. Table 3.7 for Cyclone III Family Devices # of Configuration Bits 1 Minimum Device 2 EP3C5 3,500,000 4 Mb/4 Mb EP3C10 3,500,000 4 Mb/4 Mb EP3C16 4,500,000 8 Mb/4 Mb EP3C25 6,500,000 8 Mb/8 Mb EP3C40 10,500, Mb/8 Mb EP3C55 16,000, Mb/16 Mb EP3C80 21,000, Mb/16 Mb EP3C120 30,500, Mb/32 Mb 10 Configuring_Altera_s_via_SPI_Flash_AN_01 February 20, 2008

11 2. Device sizes are for uncompressed/compressed data files, which assumes a minimum 35% reduction in data size due to compression. Table 3.8 for Cyclone II Family Devices # of Configuration Bits 1 Minimum Device 2 EP2C5 1,265,792 4 Mb/4 Mb EP2C8 1,983,536 4 Mb/4 Mb EP2C20 3,892,496 4 Mb/4 Mb EP2C35 6,848,608 8 Mb/8 Mb EP2C50 9,951, Mb/8 Mb EP2C70 14,319, Mb/16 Mb s: 1. Final data values from Altera. 2. Device sizes are for uncompressed/compressed data files, which assumes a minimum 35% reduction in data size due to compression. Table 3.9 for Cyclone Family Devices # of Configuration Bits 1 Minimum Device 2 EP1C3 627,376 4 Mb/4 Mb EP1C4 924,512 4 Mb/4 Mb EP1C6 1,167,216 4 Mb/4 Mb EP1C12 2,323,240 4 Mb/4 Mb EP1C20 3,559,608 4 Mb/4 Mb s: 1. Final data values from Altera. 2. Device sizes are for uncompressed/compressed data files, which assumes a minimum 35% reduction in data size due to compression. Table 3.10 for Arria GX Family Devices Device # of Configuration Bits 1 Minimum Device 2 EP1AGX20C/D 7,203,621 8 Mb/8 Mb EP1AGX35C/D 10,859, Mb/8 Mb EP1AGX50C/D 14,514, Mb/16 Mb EP1AGX60C/D/E 16,951, Mb/16 Mb EP1AGX90E 25,699,104 32Mb/16 Mb s: 1. Preliminary data values from Altera. 2. Device sizes are for uncompressed/compressed data files, which assumes a minimum 35% reduction in data size due to compression. 4. Other Considerations There are two other considerations related to connecting to an Altera that will be addressed now. First, the details of the Altera configuration cycle are presented. Second, the control signal required to enable direct programming in system will be discussed. 4.1 Configuration Cycle The three stages of the configuration cycle are power-on reset, configuration, and initialization. The 's power-on reset (POR) circuit keeps the device in a reset state until all applied voltages reach stable levels on power-up. As soon as the enters POR, it drives the signal low to indicate it is busy, drives the signal low to indicate that its configuration has not been completed, and tri-states all user I/O pins. After POR, the releases and enters configuration mode when this signal is pulled high by the external pull-up resistor connected to. February 20, 2008 Configuring_Altera_s_via_SPI_Flash_AN_01 11

12 The serial clock () generated by the device controls the configuration data transfer from SPI Flash to the. After all configuration data is transferred to the, it releases the pin, which is pulled high by an external pull-up resistor. initialization begins after goes to a logic high-level. After internal initialization, the enters user mode. 4.2 Direct Programming During production, the is loaded with configuration data via a third-party programmer. After installation in the final product, the off-board programmed configures the Altera at every power-up. However, if a change in configuration data is planned, the requires reprogramming on-board. Figures 3.2 through 3.9 show headers for direct (ISP). ISP programmer selection dictates header configuration. In order to allow an external source to directly program the through this header, the input signal must be held Low to force the I/O pins into a high-z state during programming, thereby eliminating any interference from the I/O pins to the reprogramming. 5. Power Management 6. References Power management, including power ramp-up rate, ramp-up voltage differentials and power sequencing are beyond the scope of this application note. Refer to power management literature from Altera for this information. Altera Cyclone Device Handbook: Chapter 13 Configuring Cyclone s (ver 1.7, Jan 2007) Altera Cyclone II Device Handbook: Chapter 13 Configuring Cyclone II Devices (ver 1.2, Feb 2007) Altera Cyclone III Device Handbook: Chapter 10 Configuring Cyclone III Devices (ver 1.1, Jul 2007) Altera Stratix II GX Device Handbook, Volume 2: Chapter 13 Configuring Stratix II and Stratix II GX Devices (ver 4.5, Oct 2007) Altera Stratix III Device Handbook, Volume 1: Chapter 11 Configuring Stratix III Devices (ver 1.3, Nov 2007). For example, Chapter 10 of Volume 1 of the Stratix III Device Handbook, titled "Hot Socketing and Power-On Reset" would contain the power management information required by the designer. Altera Arria GX Device Handbook, Volume 2: Chapter 11 - Configuring Arria GX Devices (ver 1.1, Aug 2007) 12 Configuring_Altera_s_via_SPI_Flash_AN_01 February 20, 2008

13 7. Revision History Section Revision 01 (February 20, 2008) Initial release Description February 20, 2008 Configuring_Altera_s_via_SPI_Flash_AN_01 13

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