COMPLIANCE STATEMENT

Transcription

1 COMPLIANCE STATEMENT Specification Specification name: PCIE-BASE-REV4.-CC-REFCLK Specification title: Common-clock Refclk Evaluation for PCIe v4. BASE (v1.) Specification owner: JitterLabs Device Under Test Sample product number: DEMO-1MHz-PCIe4 Sample description: PCIe4 1 MHz HCSL Refclk Sample manufacturer: Demo Devices Sample submitted by: Demo Devices Test Report Test Report number: JL17118 Test date: Oct 18, 217 Test frequency: 1 Hz Test supply voltage: 3.3 V Test temperature: 25 C This document presents independent test and analysis provided by JitterLabs for the above sample in accordance with the above specification. The Test Report referenced herein is available online in the JitterLabs app (at which includes this document plus additional data. The specification includes one or more tests, each of which is evaluated for the sample and assigned a test result from the table below. Test Result Pass Marginal Pass Fail Incomplete Interpretation The sample passes with more margin than the Warning Margin defined for the test. The sample passes with less margin than the Warning Margin defined for the test. The sample fails the test. Not all tests could be performed due to insufficient or missing data. These results are then used to assign an overall result for each generation of PCI Express technology, shown below. GEN-1: GEN-2: GEN-3: GEN-4: 1% passing 1% passing 1% passing 1% passing Gary Giust, PhD CEO, JitterLabs JitterLabs 1551 McCarthy Blvd, STE 111 Milpitas, CA (48) Overall result Approved by Contact JitterLabs LLC (the Company) is an independent laboratory providing unbiased third-party test services according to agreed requirements. This document is issued by the Company subject to its Terms of Service, available at Please refer to the limitation of liability and indemnity matters defined within. Be advised that the information contained herein summarizes the Company's findings during its testing only and, unless otherwise stated, refers only the sample(s) tested. This document may not be altered in content or appearance, nor reproduced, except in full, without prior written approval of the Company. This work is copyright by the Company with all rights reserved. October 23, JL17118-PCIE-REV4p.pdf

2 1. Specification PCIE-BASE-REV4.-CC-REFCLK, v1 Specification title: Standard body: Common-clock Refclk Evaluation for PCIe v4. BASE (v1.) PCI-SIG association Standard name: PCIe v4. GEN 1/2/3/4 [1] Specification owner: JitterLabs Warning margin: 5% for all tests, except Fssc (.5%) and Tssc_freq_dev (.5%). 2. Test Details Test Report Test report: JL17118 Test date: Oct 18, 217 Product number: DEMO-1MHz-PCIe4 Sample title: PCIe4 1 MHz HCSL Refclk Manufacturer: Demo Devices Manufacturer URL: Report owner: Demo Devices Report owner URL: Test Environment Frequency: 1 Hz Temperature: 25 C Supply voltage: 3.3 V Tune voltage: Signaling: HCSL Package: QFN Spread spectrum: No Sample interval: 25 ps 3. Test Setup The test setup is illustrated above with a connection diagram (top) and electrical model (bottom). A compliance load board with 15 db loss at 4 GHz is terminated with 2 pf capacitors [2], across which signals are measured differentially. Output DC impedance tests use an additional setup that replaces each 2 pf terminator with 5 Ohms. October 23, 217 page 2 of 17 JL17118-PCIE-REV4p.pdf

3 4. AC, DC Parameters The measurement value listed below for each test [3,4] is the worst-case value measured for that test. The population used for each measurement is 1, except for Tstable (2 ), Tperiod_avg ( ), and Zc_dc (1). All measurements except Zc_dc were derived from one continuous oscilloscope acquistion. # Parameter Measurement Specification Min Max Unit Margin Result T1 ER_rising V/ns 38 % Pass T2 ER_falling V/ns 4 % Pass T3 Vih mv 539 % Pass T4 Vil mv 53 % Pass T5 Vcross mv 39 % Pass T6 Vcross_delta mv Pass T7 Vrb (PPW) mv 361 % Pass T8 Vrb (NPW) mv 361 % Pass T9 Tstable ps 874 % Pass T1 Tperiod_avg ppm 5 % Pass T11 Tperiod_abs ns 4 % Pass T12 Tcc_jitter ps pk Pass T13 Vmax V 19 % Pass T14 Vmin V 75 % Pass T15 Duty_cycle % 49 % Pass T16 ER_matching % 35 % Pass T17 Zc_dc (REFCLK+) Ohm 46 % Pass T18 Zc_dc (REFCLK ) Ohm 48 % Pass T19 Fssc n/a khz n/a Pass T2 Tssc_freq_dev n/a -.5. % n/a Pass T21 Tssc_max_freq_slew n/a ppm/us n/a Pass ER_rising: Rising edge rate Tcc_jitter: Cycle to cycle jitter ER_falling: Falling edge rate Vmax: Absolute maximum input voltage Vih: Differential input high voltage Vmin: Absolute minimum input voltage Vil: Differential input low voltage Duty_cycle: Duty cycle Vcross: Absolute crossing-point voltage ER_matching: Rising to falling edge-rate matching Vcross_delta: Variation of Vcross for rising edges Zc_dc: Clock source output DC impedance Vrb: Ring-back voltage margin Fssc: SSC Frequency, using 2 MHz low-pass filter PPW, NPW Positive/negative pulse width Tssc_freq_dev: Deviation of SSC, using 2 MHz low-pass filter Tstable: Time before Vrb is allowed Tssc_max_freq_slew: SSC df/dt, using 2 MHz low-pass filter Tperiod_avg: Average clock period accuracy n/a: Test is not applicable Tperiod_abs: Absolute period October 23, 217 page 3 of 17 JL17118-PCIE-REV4p.pdf

4 Differential Voltage (V) Differential Waveform mean:.2 V range: 1.97 V max:.991 V min: V Time (ns) Single-ended Voltage (V) Single-ended Waveforms REFCLK+ REFCLK max:.927 V min: -.75 V Time (ns) ER_rising Distribution mean: V/ns range:.153 V/ns ER_falling Distribution mean: 2.56 V/ns range:.156 V/ns 2E-8 1.5E-8 1E-8 5E-9 max: 2.76 V/ns min: V/ns std:.18 V/ns 2E-8 1.5E-8 1E-8 5E-9 max: V/ns min: V/ns std:.18 V/ns E Rising Edge Rate (V/ns) E Falling Edge Rate (V/ns) Vih Distribution mean:.975 V range:.33 V Vil Distribution mean: V range:.33 V max:.991 V min:.958 V std:.4 V max: V min: V std:.4 V Differential Input High Voltage (V) Differential Input Low Voltage (V) Vcross Distribution mean:.423 V range:.18 V max:.432 V min:.414 V std:.2 V 2E11 1.5E11 1E11 5E1 Tcc_jitter Distribution range: ps pp max: ps pk min:. ps pk Crossing Voltage for REFCLK+ rising edges (V) E Cycle-to-cycle Jitter (ps pp) October 23, 217 page 4 of 17 JL17118-PCIE-REV4p.pdf

5 Vrb (PPW) Distribution mean:.477 V range:.35 V Vrb (NPW) Distribution mean: V range:.32 V max:.495 V min:.461 V std:.4 V max: V min: V std:.4 V Ring-back Voltage (V) Ring-back Voltage (V) 1.5E11 1E11 5E1 Tstable Distribution PPW NPW mean: ns range:.26 ns max: ns min: ns Duty_cycle Distribution mean: 5.25 % range:.1 max: % min: % std:.21 % E Tstable (ns) Duty Cycle (%) ER_matching Distribution mean: % range: % max: % min:.17 % std: % Single-ended Voltage (V) ER Example REFCLK+ REFCLK Vcross mean:.423 V in a +/- 75 mv window Rising-to-falling Edge-rate Matching (%) Time (ns) Filtered Frequency (MHz) Fssc Frequency Profile Not Applicable Time (us) SSC df/dt (ppm/us) Tssc_max_freq_slew Time Trend Not Applicable Time (us) October 23, 217 page 5 of 17 JL17118-PCIE-REV4p.pdf

6 5. Low-frequency Jitter Mask Low-frequency clock jitter must not exceed the piece-wise linear mask [5] shown below, which is defined by the following 4 points: (3 khz, 25 ns), (33 khz, 25 ns), (1 khz, 1 ns), (5 khz, 25 ps). Mask Jitter (ps pp) + worst margin # Parameter Measurement Specification Min Max Unit Margin Result T22 Jitter_mask ps pp 1 % Pass 6. Common-clock Architecture The common clock architecture [6] distributes a single reference to both Tx and Rx. A maximum Tx-to-Rx transport delay difference (T) of 12 ns is required [4], which represents the delay difference between Tx data and recovered Rx clock (as observed by the Rx latch). Jitter at Rx latch (compute both and use the larger of the two): X(s) [H 1 (s)e -st H 2 (s)] H 3 (s) X(s) [H 2 (s)e -st H 1 (s)] H 3 (s) October 23, 217 page 6 of 17 JL17118-PCIE-REV4p.pdf

7 7. Jitter GEN-1 (2.5 GT/s) Common-clock Refclk jitter compliance is analyzed for generation 1 data rates. Jitter is computed after applying each possible combination of filter model below, which estimate realistic PLL implementations for Tx, Rx, and CDR blocks. PLL #1.1 db peaking 3. db peaking PLL #2.1 db peaking 3. db peaking Model A Model B Model A Model B = 1.5 MHz ω =.336 ζ = 14 1 ω = 5.9 ζ =.54 1 = 1.5 MHz ω =.336 n2 ζ = 14 2 ω = 5.9 n2 ζ =.54 2 Model C Model D Model C Model D (max) = 22 MHz ω = 4.93 ζ = 14 1 ω = ζ =.54 1 (max) = 22 MHz ω = 4.93 n2 ζ = 14 2 ω = n2 ζ =.54 2 CDR BW CDR = 1.5 MHz 16 combinations (since PLL #1 and #2 are the same) The table below summarizes the specification limit [7] in the upper-left corner, and lists the computed jitter and margin for each required filter combination [8]. The worst-case filter corner is identified by below, and presented in more detail on the next page. Each analysis uses a population of 1 continuous clock cycles captured using a real-time oscilloscope with broadband noise minimized. Spec = 18 ps Units are pk-pk PLL #1 or #2 Rx A (T23 T26) Rx B (T27 T3) Rx C (T31 T34) Rx D (T35 T38) PLL #1 or #2 Tx A Tx B Tx C Tx D ps 99 % 1.44 ps 99 % ps 9 % ps ps 98 %.878 ps 99 % ps 89 % ps ps 91 % ps 91 % 14.1 ps ps 89 % ps 89 % ps ps ps October 23, 217 page 7 of 17 JL17118-PCIE-REV4p.pdf

8 The following shows the worst-case filter combination (identified by in the previous page) and resulting Refclk jitter. Gain (db) Block Transfer Functions H1 H2 H3 Gain (db) System Transfer Function Jitter Spectrum Unfiltered Filtered Jitter (s pp) October 23, 217 page 8 of 17 JL17118-PCIE-REV4p.pdf

9 8. Jitter GEN-2 (5. GT/s) Common-clock Refclk jitter compliance is analyzed for generation 2 data rates. Jitter is computed after applying each possible combination of filter model below, which estimate realistic PLL implementations for Tx, Rx, and CDR blocks. PLL #1.1 db peaking 1. db peaking PLL #2.1 db peaking 3. db peaking Model A Model B Model A Model B = 5. MHz ω = 1.12 ζ = 14 1 ω = 11.1 ζ = = 8. MHz ω = 1.79 n2 ζ = 14 2 ω = n2 ζ =.54 2 Model C Model D Model C Model D (max) = 16. MHz ω = 3.58 ζ = 14 1 ω = ζ = (max) = 16. MHz ω = 3.58 n2 ζ = 14 2 ω = n2 ζ =.54 2 CDR BW CDR = 5 MHz 64 combinations The table below summarizes the specification limit [7] in the upper-left corner, and lists the computed jitter and margin for each required filter combination [8]. The worst-case filter corner is identified by below, and presented in more detail on the next page. Each analysis uses a population of 1 continuous clock cycles captured using a real-time oscilloscope with broadband noise minimized. Spec = 3.1 ps Units are RMS PLL #1 PLL #2 Rx A (T39 T46) Rx B (T47 T54) Rx C (T55 T62) Rx D (T63 T7) Rx A (T71 T78) Rx B (T79 T86) Rx C (T87 T94) Rx D (T95 T12) PLL #1 PLL #2 Tx A Tx B Tx C Tx D Tx A Tx B Tx C Tx D.435 ps.377 ps.974 ps.93 ps 71 %.61 ps 8 %.423 ps.974 ps.876 ps 72 %.432 ps.365 ps.975 ps.913 ps 71 %.616 ps 8 %.431 ps.975 ps.99 ps 71 %.745 ps.734 ps ps 63 % 1.16 ps 67 %.82 ps 74 %.74 ps 77 % ps 63 %.861 ps 72 %.736 ps.718 ps 77 % ps 63 % 1.36 ps 67 %.824 ps.671 ps 78 % ps 63 %.878 ps 72 %.52 ps 83 %.481 ps 84 % 1.23 ps 67 %.928 ps 7 %.661 ps 79 %.477 ps 1.23 ps 67 %.844 ps.535 ps 83 %.471 ps 1.62 ps 66 %.991 ps 68 %.75 ps 77 %.453 ps 1.62 ps 66 %.974 ps.745 ps.734 ps ps 63 % 1.16 ps 67 %.82 ps 74 %.74 ps 77 % ps 63 %.861 ps 72 %.816 ps 74 %.796 ps 74 % 1.24 ps 6 % ps 64 %.99 ps 71 %.73 ps 1.24 ps 6 %.948 ps October 23, 217 page 9 of 17 JL17118-PCIE-REV4p.pdf

10 The following shows the worst-case filter combination (identified by in the previous page) and resulting Refclk jitter. Gain (db) Block Transfer Functions H1 H2 H3 Gain (db) System Transfer Function Jitter Spectrum Unfiltered Filtered Jitter (s pp) October 23, 217 page 1 of 17 JL17118-PCIE-REV4p.pdf

11 9. Jitter GEN-3 (8. GT/s) Common-clock Refclk jitter compliance is analyzed for generation 3 data rates. Jitter is computed after applying each possible combination of filter model below, which estimate realistic PLL implementations for Tx, Rx, and CDR blocks. PLL #1.1 db peaking 2. db peaking PLL #2.1 db peaking 1. db peaking Model A Model B Model A Model B = 2. MHz ω =.448 ζ = 14 1 ω = 6.2 ζ =.73 1 = 2. MHz ω =.448 n2 ζ = 14 2 ω = 4.62 n2 ζ = Model C Model D Model C Model D (max) = 4. MHz ω =.896 ζ = 14 1 ω = 12.4 ζ =.73 1 (max) = 5. MHz ω = 1.12 n2 ζ = 14 2 ω = n2 ζ = CDR BW CDR = 1 MHz 64 combinations The table below summarizes the specification limit [7] in the upper-left corner, and lists the computed jitter and margin for each required filter combination [8]. The worst-case filter corner is identified by below. Each analysis uses a population of 1 continuous clock cycles captured using a real-time oscilloscope with broadband noise minimized. Test-environment noise is separately measured and removed, as discussed in Section 11. Spec = 1 fs Units are RMS PLL #1 PLL #2 Rx A (T13 T11) Rx B (T111 T118) Rx C (T119 T126) Rx D (T127 T134) Rx A (T135 T142) Rx B (T143 T15) Rx C (T151 T158) Rx D (T159 T166) PLL #1 PLL #2 Tx A Tx B Tx C Tx D Tx A Tx B Tx C Tx D 78 fs 92 % 66 fs 129 fs 97 fs 9 % 78 fs 92 % 71 fs 155 fs 135 fs 71 fs 55 fs 95 % 126 fs 94 fs 91 % 71 fs 63 fs 94 % 153 fs 134 fs 118 fs 113 fs 89 % 153 fs 126 fs 118 fs 115 fs 89 % 176 fs 82 % 156 fs 84 % 99 fs 9 % 89 fs 91 % 143 fs 11 fs 89 % 99 fs 9 % 93 fs 91 % 168 fs 83 % 147 fs 78 fs 92 % 66 fs 129 fs 97 fs 9 % 78 fs 92 % 71 fs 155 fs 135 fs 74 fs 6 fs 94 % 127 fs 95 fs 91 % 74 fs 66 fs 154 fs 134 fs 139 fs 136 fs 168 fs 83 % 144 fs 139 fs 137 fs 19 fs 81 % 171 fs 83 % 127 fs 122 fs 161 fs 84 % 133 fs 127 fs 124 fs 183 fs 82 % 163 fs 84 % October 23, 217 page 11 of 17 JL17118-PCIE-REV4p.pdf

12 The following shows the worst-case filter combination (identified by in the previous page) and resulting Refclk jitter. Gain (db) Block Transfer Functions H1 H2 H3 Gain (db) System Transfer Function Jitter Spectrum Unfiltered Filtered Environment Noise Jitter (s pp) October 23, 217 page 12 of 17 JL17118-PCIE-REV4p.pdf

13 1. Jitter GEN-4 (16. GT/s) Common-clock Refclk jitter compliance is analyzed for generation 4 data rates. Jitter is computed after applying each possible combination of filter model below, which estimate realistic PLL implementations for Tx, Rx, and CDR blocks. PLL #1.1 db peaking 2. db peaking PLL #2.1 db peaking 1. db peaking Model A Model B Model A Model B = 2. MHz ω =.448 ζ = 14 1 ω = 6.2 ζ =.73 1 = 2. MHz ω =.448 n2 ζ = 14 2 ω = 4.62 n2 ζ = Model C Model D Model C Model D (max) = 4. MHz ω =.896 ζ = 14 1 ω = 12.4 ζ =.73 1 (max) = 5. MHz ω = 1.12 n2 ζ = 14 2 ω = n2 ζ = CDR BW CDR = 1 MHz 64 combinations The table below summarizes the specification limit [7] in the upper-left corner, and lists the computed jitter and margin for each required filter combination [8]. The worst-case filter corner is identified by below. Each analysis uses a population of 1 continuous clock cycles captured using a real-time oscilloscope with broadband noise minimized. Test-environment noise is separately measured and removed, as discussed in Section 11. Any SSC spurs are also removed up to 2 MHz. Spec = 5 fs Units are RMS PLL #1 PLL #2 Rx A (T167 T174) Rx B (T175 T182) Rx C (T183 T19) Rx D (T191 T198) Rx A (T199 T26) Rx B (T27 T214) Rx C (T215 T222) Rx D (T223 T23) PLL #1 PLL #2 Tx A Tx B Tx C Tx D Tx A Tx B Tx C Tx D 78 fs 84 % 66 fs 129 fs 74 % 97 fs 81 % 78 fs 84 % 71 fs 155 fs 135 fs 71 fs 55 fs 89 % 126 fs 75 % 94 fs 81 % 71 fs 63 fs 153 fs 134 fs 118 fs 113 fs 77 % 153 fs 126 fs 75 % 118 fs 115 fs 77 % 176 fs 65 % 156 fs 99 fs 8 % 89 fs 82 % 143 fs 71 % 11 fs 78 % 99 fs 8 % 93 fs 81 % 168 fs 66 % 147 fs 71 % 78 fs 84 % 66 fs 129 fs 74 % 97 fs 81 % 78 fs 84 % 71 fs 155 fs 135 fs 74 fs 6 fs 127 fs 75 % 95 fs 81 % 74 fs 66 fs 154 fs 134 fs 139 fs 72 % 136 fs 168 fs 66 % 144 fs 71 % 139 fs 72 % 137 fs 19 fs 62 % 171 fs 66 % 127 fs 75 % 122 fs 161 fs 68 % 133 fs 127 fs 75 % 124 fs 75 % 183 fs 63 % 163 fs 67 % October 23, 217 page 13 of 17 JL17118-PCIE-REV4p.pdf

14 The following shows the worst-case filter combination (identified by in the previous page) and resulting Refclk jitter. Gain (db) Block Transfer Functions H1 H2 H3 Gain (db) System Transfer Function Jitter Spectrum Unfiltered Filtered Environment Noise Jitter (s pp) October 23, 217 page 14 of 17 JL17118-PCIE-REV4p.pdf

15 11. Jitter Methodology The PCI-SIG association requires clock jitter to be evaluated using an oscilloscope [9]. However, an oscilloscope's noise floor can approach or exceed that of a precision clock device. This is particularly relevant for newer standards, where tighter jitter limits require cleaner devices. Our goal is to accurately report a device's intrinsic jitter, without noise from the test environment. We achieve this using the method below, which we apply in Sections 9 and 1. The following method [1,11] obeys all test requirements of PCIe v4.. However, it includes an additional process to measure then subtract noise from the test environment. The process requires no additional hardware, and is SSC agnostic. Since this process is outside PCI-SIG, we summarize its key steps and results below. Differential Voltage (V) Differential Voltage (V) Step 1: Acquire Signal Time (ns) Step 4: Create a Jitter-free Model Time (ns) Differential Voltage (mv) Voltage (mv) Step 2: Acquire Noise Time (ns) Step 5: Add Noise to Model Model + Noise Model Test Environment Jitter Time/25ps (relative units) 1. Acquire a clock waveform and apply a noise-reduction bandwidth filter (to remove oscilloscope broadband noise). 2. Power off the device under test (DUT), and acquire a noise waveform. Apply the same filter as step Create a continuous-time model for a time segment representing the average rising (and separately, falling) edge. 4. Construct an ideal differential waveform from these models, sampled at the same time interval as the clock signal. This waveform accurately models the average shape of each edge, the average period, and contains no jitter (within machine precision, e.g. 16+ digits). Only the V-crossing regions of this model are used. 5. Compute jitter time trends for (1) the signal, and (2) the model plus noise (the above figure analyzes 1 rising edge). 6. Apply the same (required) jitter filter to each of the jitter time trends. 7. For SSC and GEN-4 analysis, remove SSC frequency-domain jitter spurs up to 2 MHz. 8. Compute RMS jitter separately for the filtered signal (J S ), and the filtered model-plus-noise (J N ). Estimate the true DUT jitter using quadrature subtraction as follows: J DUT = sqrt( J 2 S J 2 N ) October 23, 217 page 15 of 17 JL17118-PCIE-REV4p.pdf

16 The DUT intrinsic jitter (J DUT ) is computed using the above methodology and plotted below as open circles with error bars for each filter combination. For reference, the corresponding signal jitter (J S ) is plotted as filled circles. GEN-3 Jitter Analysis (spec = 1 ps RMS) Jitter (ps RMS) Jitter Filter (T# per Section 9) DUT jitter (after noise removal) with 98% error bars Signal jitter (before noise removal).4 GEN-4 Jitter Analysis (spec =.5 ps RMS).35 Jitter (ps RMS) Jitter Filter (T# per Section 1) DUT jitter (after noise removal) with 98% error bars Signal jitter (before noise removal) The overall results shown on page 1 for GEN-1 and GEN-2, and jitter values in Sections 7 and 8, use a traditional jitter analysis (based on J S ). The overall results for GEN-3 and GEN-4 on page 1, and jitter values in Sections 9 and 1, use the traditional jitter analysis plus a step to remove noise from the test environment (based on J DUT ). Although we recommend this approach, GEN-3 and GEN-4 jitter can also be analyzed without noise removal using the above data for J S instead. Note that the 98% error bars shown for J DUT analyze the noise removal process. They are informational only, and not used to determine compliance. October 23, 217 page 16 of 17 JL17118-PCIE-REV4p.pdf

17 12. References [1] PCI Express Base Specification, Rev. 4., Version 1. (Sept. 27, 217) available at [2] Reference [1], section titled "Refclk Test Setup". [3] Reference [1], section titled "Refclk AC Specifications". [4] Reference [1], section titled "Data Rate Independent Refclk Parameters". [5] Reference [1], section titled "Low Frequency Refclk Jitter Limits". [6] Reference [1], section titled "Common Refclk Rx Architecture (CC)". [7] Reference [1], section titled "Jitter Limits for Refclk Architectures". [8] Reference [1], section titled "CDR and PLL BW and Peaking Limits for Common Refclk". [9] Reference [1], section states "Jitter measurements shall be made with a... real time oscilloscope." [1] Removing Oscilloscope Noise from RMS Jitter Measurements, NOTE-5, JitterLabs (July 217). [11] Patent pending, "Characterizing a signal in the presence of noise," JitterLabs. 13. Disclaimer All opinions, judgments, recommendations, etc. presented herein are the opinions of JitterLabs and do not necessarily reflect the opinions of the PCI-SIG association. The information in this document refers to specifications still in the development process. Material is subject to change before the specifications are released. October 23, 217 page 17 of 17 JL17118-PCIE-REV4p.pdf