2-Level Page Tables. Virtual Address Space: 2 32 bytes. Offset or Displacement field in VA: 12 bits

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Eunice Clarke
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1 -Level Page Tables Virtual Address (VA): bits Offset or Displacement field in VA: bits Virtual Address Space: bytes Page Size: bytes = KB Virtual Page Number field in VA: - = bits Number of Virtual Pages: / = VA: VPN VPN bits OFFSET bits Page of bytes Virtual Address Space of pages -

2 -Level Page Tables PA: Physical Address (PA): 8 bits Offset or Displacement field in PA: bits Physical Address Space: 8 bytes Page Size: bytes = KB Page Frame Number field in PA: 8 - = 6 bits Number of Physical Pages: 8 / = 6 PFN OFFSET 6 bits bits Page Frame of size bytes Physical Address Space of 6 pages 6 -

3 BYTE BYTE - - Page Table: descriptors descriptor for each Virtual Page 6 - VPN can be used as an index into Page Table to find the descriptor for that page Single Level Page Table

4 Descriptor holds the Page Frame Number (PFN) of the virtual page if it is in memory A presence bit (P) indicates if it is in memory or on the backing device Descriptor also contains other administrative and protection bits e.g. D (Dirty), U (Used), R (Read), W (Write), E(Execute) etc. In the example: PFN requires 6 bits Assume exactly the 6 administrative bits mentioned above Descriptor is 6+6 = bits or bytes wide. Size of Page Table = Number of descriptors x Size of descriptor = x bytes = MB

5 Two-Level Page Tables Break up Page Table into fixed-size blocks of the same size as a page In example: Each page is KB and Page Table is MB So we will have MB/KB = = such blocks This collection of blocks that make up the Page Table will be called the nd-level Page Table The st-level Page Table will have entries pointing to each block of the nd level Page Table. In example: entries in the st-level Page Table How many descriptors in each block? Each block (or page of the Page Table) will hold: KB/bytes = descriptors

6 entries: one for each block of nd level page table nd-level Page Table Descriptors per block (page) of the Page Table st-level Page Table - such blocks (pages) of the Page Table Page Table: descriptors descriptor for each Virtual Page Blocked into blocks of descriptors each

7 entries: one for each block of nd level page table nd-level Page Table Descriptors per block (page) of the Page Table st-level Page Table - such blocks (pages) of the Page Table Do not need to store the entire nd level Page Table as a contiguous array Do not allocate blocks that have no descriptors Keep blocks on secondary store and bring in when needed (mini virtual memory system for the Page Table management)

8 entries: one for each block of nd level page table nd-level Page Table Descriptors per block (page) of the Page Table st-level Page Table - Do not need to store the entire nd level Page Table as a contiguous array Do not allocate blocks that have no descriptors Keep blocks on secondary store and bring in when needed (mini virtual memory system for the Page Table management) Q: What is the actual size of virtual address space being used by the above process? Each descriptor represents to a = KB portion of the address space blocks = x descriptors imply : x x KB = 8MB address space

9 Virtual Memory: -level Page Table MSBs (bits..) of the virtual address (PTN) are used to index into the Page Table Directory Next bits (..) are used to index the chosen Page Table. PTN () PN() PD() PTR Page Offset (PD) KB Page st-level Page Table (Page Table Directory) Page Tables

10 More Details on Page Table Lookup 6 bits PTR PTN () PN() PD() PTR PTN 6 8 bit physical address of desiredst-level Page Table entry st Level Page Table and all blocks of the nd-level Page Table are stored at Page Aligned Boundaries i.e. LSBs are zero

11 More Details on Page Table Lookup 6 bits Base Address PTN () PN() PD() From selected entry in st-level PT Base Address PN 6 8 bit physical address of desired nd-level Page Table entry

12 More Details on Page Table Lookup 6 bits PFN PTN () PN() PD() From selected entry in nd-level PT PFN PD 6 8 bit physical address of desired memory byte

13 Virtual Memory and Caches Physical cache Accessed using translated physical address Cache access only after TLB translation Common case (cache hit) slowed down Cache locations addressed using physical memory addresses Physical Address (PA) TAG C ACHE INDEX BYTE OFFSET CPU VA PA PHYSICAL TLB CACHE VPN PAGE OFFSET PFN PAGE OFFSET Virtual Address (VA) Physical Address (PA) Can we avoid latency of translation every memory access?

14 Virtual cache Accessed using the virtual address directly Virtual Memory and Caches VPN PAGE OFFSET Virtual Address (VA) TLB PA CPU VA TAG Virtual Address (VA) C ACHE INDEX BYTE OFFSET VIRTUAL CACHE PFN Cache locations addressed using virtual memory addresses PAGE OFFSET Physical Address (PA)

15 Virtual Memory and Caches Accessed using virtual addresses (+) Address translation (TLB lookup) in parallel with cache lookup Access TLB for protection information unless information replicated in cache (-) Context switch must invalidate all cache entries Every process has the same virtual address space n - How do you distinguish a virtual address of some process from the same virtual address of a different process? Use processor identifiers (PIDs) as additional field to tag cache blocks

16 Virtual Memory and Caches VA = PA = VPN 6 VA = PA = TAG PFN Physical Memory 6 7 Page Table Process Direct Mapped size Blocks Assumes cache block size of w bytes VA = PA = VA = PA = w BYTES

17 Virtual Memory and Caches VA = VPN 6 7 Page Table Process VA = TAG PFN Physical Memory Page Table Process VA = VA = Process will access cached data of Process

18 Virtual Memory and Caches VPN PFN Physical Memory 6 7 Page Table Process V I I I I TAG Page Table Process Solution : Invalidate all cache blocks on a context switch Cache blocks that may have survived (i.e were not evicted) by swapped-in process are wastefully invalidated. Cold cache on resumption

19 Virtual Memory and Caches VPN PFN Physical Memory 6 7 Page Table Process PROCESS ID TAG 6 Solution : Add a process id field as a part of the tag to identify the process whose blocks are in cache 6 7 Page Table Process

20 Virtual Memory and Caches : Accessed using virtual addresses : (-) Aliases: Different names for the same physical object Different virtual address but same physical address May result in multiple inconsistent copies of the data in the cache

21 Virtual Memory and Caches VPN TAG PFN Physical Memory 6 7 Page Table Process VA: PA: VA: PA: Note: This can only happen if the number of blocks in any way of the cache is greater than the number of blocks in a virtual page. cached copies of same physical location (in different cache locations) For aliasing to occur: The cache page size must exceed the virtual page size

Computer Structure. X86 Virtual Memory and TLB

Computer Structure. X86 Virtual Memory and TLB Computer Structure X86 Virtual Memory and TLB Franck Sala Slides from Lihu and Adi s Lecture 1 Virtual Memory Provides the illusion of a large memory Different machines have different amount of physical