10. INPUT/OUTPUT STRUCTURES

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1 10. INPUT/OUTPUT STRUCTURES (R. Horvath, Introduction to Microprocessors, Chapter 10) The input/output (I/O) section of a computer handles the transfer of information between the computer and the devices which communicate with the outside world. The input and output directions are from the point of view of the computer. Output flows from the computer to the devices; input flows from the devices to the computer. T he devices, called peripheral devices or peripherals, include such things as keyboards, switches, display lamps, character displays, cathode ray tube displays, pen plotters, teleprinters, analog-to-digital (A/D) converters, digital-to-analog (D/A) converters, solenoids, motor starters, and the like. Peripheral devices are connected to the processor through special electronic circuits known as interfaces. These circuits access a selected peripheral and take care of any special timing requirements or signal level adjustments, which may be necessary. Both data and control information must be transferred between the computer and a peripheral. Data comprises the bits which encode the pattern to be displayed, and so forth. Control signals keep the computer informed as to the status or availability of the peripheral. Thus, control information includes acknowledgement signals which may travel in either direction. 1

2 10.1 ACCESSING I/O The processor may access the interface circuits associated with a particular peripheral using either of two basic methods. The first method, which must be designed into the processor, is known as special I/O (sometimes referred as I/O-mapped I/O). The other method, which requires no special considerations in the processor, is called memory-mapped I/O Special I/O Special I/O refers to a configuration in which the I/O circuitry has its own address space separate from that of memory. The interface circuits are accessed by special I/O instructions. These instructions are intended specifically for I/O operations and they refer to the special I/O address space. Special I/O must be designed into the processor, since it requires, among other things, that the special instructions must be a part of the instruction set for the processor. The number of I/O locations in any computer system is very much smaller than the number of memory locations. As a consequence, only very simple instructions are available to support special I/O. These commonly include only such operations as "input a byte from device number N to an accumulator" or "output a byte from an accumulator to device number N". In these examples N would be the I/O space address of the interface circuit. 2

3 Memory-Mapped I/O The MC68000 do not use special I/O, instead, systems based on either of these processors must use memory-mapped I/O. An alternative way for it to access the I/O interface circuits is by including them in the system in exactly the same way that memory is included. In that case, the I/O circuits share the single address space of the processor with the memory devices. This approach, known as memorymapped I/O. All of the rich and varied memory reference operations and addressing modes are available for use in I/O instructions. This is a major advantage of memory-mapped I/O over that of special I/O with its limited instruction set. A disadvantage of memory-mapped I/O is that the interface circuits occupy a portion of the common address space which would ordinarily be available for memory. Even though there may be only a few I/O devices in a system, memory comes in fairly sizable modules, on the order of 1024 or more bytes per chip. However, control applications which use 16-bit processors usually have more than enough memory space available to provide for memory-mapped I/O. Instructions such as LDA $1234, CLR $5678 or MOVE D0,$ may be ordinary memory reference instructions or they may be I/O instructions. 3

4 10.2 INITIATION AND CONTROL OF I/O Both the processor and the peripheral device (through its interface circuitry) are involved in the transfer of I/O data and control information. Several alternatives have been devised for initiating and controlling the transfer Programmed I/O In programmed I/O the processor, by executing program instructions, both initiates and controls the transfer of information. The program tells the peripheral interface exactly what to do and when to do it. Lighting up a pattern on an LED display may be accomplished by a pair of instructions such as instruction MOVE #PTRN,DSPL, where PTRN is the binary pattern to be sent to the display interface and DSPL is the address of the interface. These instructions could be included in the program wherever the programmer decides that it is appropriate to do so. In some cases, it may be necessary to test the peripheral to determine whether it is ready to communicate. If so, the program will perform the test with a simple procedure called a polling loop. The processor fetches a byte from the interface and tests a bit in it. If the result of this test indicates that the peripheral is not ready for data transfer, then the program loops back to repeat the fetch and test (polling) sequence. The polling continues until the peripheral is ready to transfer data. At that time the program proceeds with the data transfer operation. Example of polling loops for a keyboard is shown bellow. l.*mc68000 POLLING LOOP EXAMPLE 2 TEST BTST 3 BEQ TEST BIT 7 = 1 WHEN KEY IS PUSHED 4 PSHD MOVE KCOD,D0 KCOD CONTAINS THE KEYCODE 5 DO SOMETHING WITH THE KEYCODE Of the three methods described here for initiating and controlling the transfer of information between the computer and its peripherals, programmed I/O is the slowest. 4

5 Interrupt I/O The processor may spend a large part of its time waiting for a key to be pushed. There may be other, more important things which the processor should be doing rather than waiting for peripherals. In such cases, an alternative is to use interrupt I/O. With interrupt I/O the peripheral initiates the transfer of data. It does this by signaling its readiness on a special input to the processor called an interrupt request line. The interrupt process is illustrated in Figure. The interrupt is indicated by the IRQ (Interrupt ReQuest) signal coming in from outside of the processor while it is executing the main program sequence at point A. The processor responds to the interrupt request by completing the execution of the current instruction and saving information concerning the status of the current program on the stack. Included in this information must be at least the content of the program counter so that the processor will know where to return after completion of the I/O operation. The processor then turns off the interrupt system so that it can execute instructions with no additional interrupt occurring. Then it branches to the beginning of a special program segment called an interrupt service routine. This is shown in Figure 10.5 as point X. The interrupt service routine transfers the data or otherwise services the peripheral in accordance with its needs. Note the similarity of the interrupt process to a subroutine. The primary difference is that the interrupt may occur at any unpredictable time whereas the subroutine call is under the complete control of the programmer. Because of the elimination of the polling loops, interrupt I/O is faster 5

6 than programmed I/O. A wide variety of interrupt support structures, both hardware and software, exist in microprocessors. With programmed I/O the transfer of information is both initiated and controlled by the program. With interrupt I/O, the peripheral initiates the transfer and the program (through the interrupt service routine) controls the transfer. Program control of the transfer of information means that the processor must fetch and execute instructions in order to carry out the transfer. The next approach to be described relieves the processor of this duty and achieves the maximum data transfer rate possible Direct Memory Access The absolute maximum I/O transfer rate for a given system occurs when the memory ' ' is accessed at every cycle and a word is transferred at each access. This corresponds to a transfer rate of one word per memory cycle time. This rate cannot be achieved when the transfer is under program control because the instructions to transfer the data must also be fetched during memory cycles. The data transfer rate in the MC68000 using the MOVE instruction is one byte in 4 to 12 memory cycles, depending on the operand size and the addressing mode used. The maximum data transfer rate can be achieved only by removing the processor from the system and transferring data directly between the peripheral (through its interface) and memory. This technique is known as direct memory access or DMA. It requires a complex interface and a certain amount of initialization time. As a consequence, it is used only when large blocks of data must be transferred in the shortest possible time. Examples of peripherals which may use DMA are video displays and disks. With DMA the peripheral device initiates the transfer by signaling the processor that it wishes to take over control of the address and data buses. This signaling takes place over a special line called a bus request or a DMA request line. When the processor reaches a place in its sequence where it can do so, it will cease fetching and executing instructions. 6

The von Neumann Architecture. IT 3123 Hardware and Software Concepts. The Instruction Cycle. Registers. LMC Executes a Store.

The von Neumann Architecture. IT 3123 Hardware and Software Concepts. The Instruction Cycle. Registers. LMC Executes a Store. IT 3123 Hardware and Software Concepts February 11 and Memory II Copyright 2005 by Bob Brown The von Neumann Architecture 00 01 02 03 PC IR Control Unit Command Memory ALU 96 97 98 99 Notice: This session