ECEN720: High-Speed Links Circuits and Systems Spring 2017

Transcription

1 ECEN720: High-Speed Links Circuits and Systems Spring 2017 Lecture 1: Introduction Sam Palermo Analog & Mixed-Signal Center Texas A&M University

2 Class Topics System and design issues relevant to high-speed electrical (and optical) signaling Channel properties Modeling, measurements, communication techniques High-Speed link circuits Drivers, receivers, equalizers, timing systems Link system design Modeling and performance metrics Link system examples 2

3 Administrative Instructor: Sam Palermo 315E WEB, , Office hours: M 3:00pm-4:30pm, Tu 8:00am-9:30am Lectures: TR 11:10am-12:25pm, WEB 049 Lab: M 10:20pm-1:10pm, CVLB 322 Lab begins on January 30 Class web page 3

4 Class Material Textbook: Class Notes and Technical Papers Key References Digital Systems Engineering, W. Dally and J. Poulton, Cambridge University Press, Advanced Signal Integrity for High-Speed Digital Designs, S. H. Hall and H. L. Heck, John Wiley & Sons, High-Speed Digital Design: A Handbook of Black Magic, H. Johnson & M. Graham, Prentice Hall, Design of Integrated Circuits for Optical Communications, B. Razavi, McGraw-Hill, Class notes Will post online before class 4

5 Grading Exams (50%) Two midterm exams (25% each) Homework & Labs (25%) Labs (Prelab + Report) and homeworks weighted equally Collaboration is allowed, but independent simulations and write-ups Need to setup CADENCE simulation environment Due at beginning of lab or 5PM (HW) No late homework will be graded Final Project (25%) Groups of 1-3 students Report and PowerPoint presentation required 5

6 Prerequisites This is a circuits AND systems class Circuits ECEN474 or approval of instructor Basic knowledge of CMOS gates, flops, etc Circuit simulation experience (HSPICE, Spectre) Systems Basic knowledge of s- and z-transforms Basic digital communication knowledge MATLAB experience 6

7 Simulation Tools Matlab ADS (Statistical BER link analysis) Cadence 90nm CMOS device models Can use other technology models if they are a 90nm or more advanced CMOS node Other tools, schematic, layout, etc are optional 7

8 Desktop Computer I/O Architecture Many high-speed I/O interfaces Key bandwidth bottleneck points are memory (FSB) and graphics interfaces (PCIe) Near-term architectures Integrated memory controller with serial I/O (>5Gb/s) to memory Increasing PCIe from 2.5Gb/s (Gen1) to 8Gb/s (Gen3) Other serial I/O systems Multi-processor systems Routers 8

9 Serial Link Applications Processor-to-memory RDRAM (1.6Gbps), XDR DRAM (7.2Gbps), XDR2 DRAM (12.8Gbps) Processor-to-peripheral PCIe (2.5, 5, 8Gbps), Infiniband (10Gbps), USB3 (4.8Gbps) Processor-to-processor Intel QPI (6.4Gbps), AMD Hypertransport (6.4Gbps) Storage SATA (6Gbps), Fibre Channel (20Gbps) Networks LAN: Ethernet (1, 10Gbps) WAN: SONET (2.5, 10, 40Gbps) Backplane Routers: ( Gbps) 9

10 Chip-to-Chip Signaling Trends Lumped capacitance Decade Speeds Transceiver Features 1980 s >10Mb/s Inverter out, inverter in Transmission line 1990 s >100Mb/s Termination Source-synchronous clk. Lossy transmission line 2000 s >1 Gb/s Pt-to-pt serial streams Pre-emphasis equalization Transmit Filter Channel h(t) noise Future >10 Gb/s Adaptive Equalization, Slicer Advanced low power clk. Alternate channel materials Sampler RX Equalizer CDR Slide Courtesy of Frank O Mahony & Brian Casper, Intel 10

11 Increasing I/O Bandwidth Demand Single Multi Many-Core Processors Tera-scale many-core processors will aggressively drive aggregate I/O rates Intel Teraflop Research Chip ITRS Projections* 80 processor cores On-die mesh interconnect network w/ >2Tb/s aggregate bandwidth 100 million transistors 275mm 2 S. Vangal et al, An 80-Tile Sub-100W TeraFLOPS Processor in 65nm CMOS," JSSC, *2006 International Technology Roadmap for Semiconductors 11

12 High-Speed Electrical Link System 12

13 Electrical Backplane Channel Frequency dependent loss Dispersion & reflections Co-channel interference Far-end (FEXT) & near-end (NEXT) crosstalk 13

14 Channel Performance Impact 14

15 Channel Performance Impact 15

16 Backplane Link Example A 10Gb/s 5-tap DFE / 4-Tap FFE Transceiver in 90nm CMOS Technology Mounir Meghelli, Sergey Rylov, John Bulzacchelli, Woogeun Rhee, Alexander Rylyakov, Herschel Ainspan, Ben Parker, Michael Beakes, Aichin Chung, Troy Beukema, Petar Pepeljugoski, Lei Shan, Young Kwark, Sudhir Gowda and Dan Friedman IBM T. J. Watson Research Center, Yorktown Heights, NY 16

17 Transmission Channel Impairments INPUT Eye FFE1 10.0Gb/s [OPEN,1e-8] No Xtalk Packaged SerDes Eye FFE1 10.0Gb/s [OPEN,1e-8] No Xtalk 500mVDATA = RAND Tx 600mVpd AGC Gain -5.48dB XTALK = NONE AGC 5.0GHz 0.00dB PKG=0/0 TERM = 5050/5050 IC = 3/3 400mV 300mV Signal Amplitude Vpd 500mVDATA = RAND Tx 600mVpd AGC Gain -6.02dB XTALK = NONE AGC 5.0GHz 0.00dB PKG=0/0 TERM = 5050/5050 IC = 3/3 400mV 300mV 200mV 100mV -0.0mV -100mV -200mV -300mVHSSCDR = pre2 IBM Confidential Date = Sat 01/21/ :01 PM PLL=0F1V0S0,C16,N32,O1,L80 FREQ=0.00ppm/0.00us -400mVFFE = [1.000, 0.000] -500mV -100ps -50ps 0ps 50ps Time 100ps Backplane trace Line card trace Edge connector Via stub Signal Amplitude Vpd 200mV 100mV -0.0mV -100mV -200mV -300mVHSSCDR = pre2 IBM Confidential Date = Sat 01/21/ :00 PM PLL=0F1V0S0,C16,N32,O1,L80 FREQ=0.00ppm/0.00us -400mVFFE = [1.000, 0.000] -500mV -100ps -50ps 0ps 50ps Time OUTPUT 100ps SDD21 S Hz [OPEN,1e-8] Channel Response 5GHz 2.0GHz 4.0GHz 6.0GHz 8.0GHz Frequency S11, S GHz Pkg Line card trace Edge connector Backplane 16 trace Edge connector Line card trace Pkg Tx IC [Meghelli (IBM) ISSCC 2006] The Channel Rx IC 17

18 10Gb/s SerDes Main Features Tx with 1 baud-spaced 4-tap FFE Rx with 5-tap adaptive DFE and digital clock recovery LC-VCO based PLL for low noise clock generation 90nm CMOS technology [Meghelli (IBM) ISSCC 2006] 18

19 Key Features: - Half-rate CML design - 4-tap FFE - Tap polarity control - ESD protection - 70mW (24mA main tap, no FFE) V DD =1.0V Transmitter Architecture IDACs & Bias Control FFE Taps Full Scale DAC bits Pre-cursor 25% 4 Cursor 100% 6 1 st Post-cursor 50% 5 2 nd Post-cursor 25% 4 V DDA =1.2V ESD 1/4 1 1/2 1/4 1x 4x 2x 1x V DDA =1.2V 50Ω Out-P Out-N (10Gb/s) V DDIO =1.0V (2.5Gb/s) D 0 D 1 D 2 D (5Gb/s) 4:2 MUX L L sgn -1 sgn 0 sgn 1 sgn 2 L L L L L L L [Meghelli (IBM) ISSCC 2006] 2 C2 (5GHz) From on-chip PLL A Low Power 10Gb/s Serial Link Transmitter in 90-nm CMOS A. Rylyakov et al., CSICS

20 Tx Output Eye 10Gb/s e FFE1 10.0Gb/s [OPEN,1e-8] No Xtalk x 600mVpdAGC Gain -6.02dB AGC 5.0GHz 0.00dB = 5050/5050 IC = 3/0 No FFE, 24mA on main tap Measured IBM Confidential EQ OFS = 0.00ppm/0.00us 000] Simulated 0ps 0ps 50ps Time 100ps Eye FFE4 10.0Gb/s [OPEN,1e-8] No Xtalk 00mVpd AGC Gain -6.02dB AGC 5.0GHz 0.00dB 5050 IC = 3/0 FFE 4=[0, 85%, -15%, 0, 0] nfidential Q OFS = 0.00ppm/0.00us D/E OFST 1 37, 0.000] ps 0ps 50ps Time 100ps [Meghelli (IBM) ISSCC 2006] 20

21 Receiver Architecture From on-chip PLL (5GHz) In_P In_N (10Gb/s) Vcm 50Ω T-Coil Compensation Network ESD V DDA =1.2V VGA C2-I Phase rotator I PI C2-Q PI Q Phase detector DFE Block I-Clock control Q-Clock control Edge Data Amp V DD =1.0V 2:8 DMUX Tap weights CDR logic 8:16 DMUX DFE logic CML CMOS logic V DDIO =1V 8 Data Amp Edge Clock D 0 D 1 D 2 D 3 (2.5Gb/s) Key Features: - Half-rate design - 5-tap continuously adaptive DFE - Variable gain amplifier - Digital CDR - ESD protection (HBM & CDM) - 130mW (with DFE and CDR logic) [Meghelli (IBM) ISSCC 2006] 21

22 DFE Approach (+H1) I I I Σ I L L L Deven Data (-H1) (+H1) I H1-5 Tap-feedback and weighting Σ I L L L I I I (-H1) I Tap weights Dodd On-chip DFE Logic DFE Taps Resolution H1 6 bits H2 5 bits H3, H4, H5 4 bits Σ Amplitude I Offset Received eye ISI [Meghelli (IBM) ISSCC 2006] Key Features: - Half-rate DFE with H1 speculation and dynamic H2-H5 feedback allows 2UI for settling - DFE algorithm maximizes vertical eye opening at the data slicing instant - Offset adjustment at all the slicer inputs 22

23 CDR Loop Data Z -1 Z -1 Data Clock D DMUX E Edge Clock D E XORs Early Late Digital Filter I Rotator Control D/A Q Rotator Control D/A PI PI C2-I C2-Q From on-chip PLL Jitter Tolerance Receiver Jitter tolerance curve ( BER<1e-9) Key Features: - Fully digital loop - Can handle up to +/- 4000ppm frequency offset - Independent I,Q control Sine Jitter (UI pp) Tracking bandwidth ~9MHz E E E E E+09 Modulation Frequency [Meghelli (IBM) ISSCC 2006] 23

24 Chip-to-Chip Link Experiments Trace SerDes1 SerDes1 Module SerDes2 SerDes2 Module Board Trace Length 5GHz losses (Tx module + board trace + Rx module) 10 (#1) 12dB 2 / 0 / 0 10 (#2) 10dB 0 / 2 / dB 4 / 2 / dB 0 / 0 / 2 Number of vias 3.8mm via stub / 1.8mm via stub / 1.8mm via through Via stub Trace [Meghelli (IBM) ISSCC 2006] 24

25 Horizontal Eye Opening (1e-9 BER) 50.00% 40.00% 30.00% 20.00% 10.00% Chip-to-Chip Measurement Results Horizontal eye opening of the equalized eye at the receiver slicer input 60.00% DFE + FFE DFE + FFE DFE ONLY FFE ONLY DFE + FFE DFE + FFE Trace Length DFE ONLY 5GHz losses (Tx module + board trace + Rx module) 10 (#1) 12dB 2 / 0 / 0 10 (#2) 10dB 0 / 2 / dB 4 / 2 / dB 0 / 0 / 2 FFE ONLY DFE+FFE DFE FFE Number of vias 3.8mm via stub / 1.8mm via stub / 1.8mm via through 0.00% 10" (#1) 10" (#2) 15" 20" Link [Meghelli (IBM) ISSCC 2006] 25

26 Preliminary Schedule Dates may change with reasonable notice 26

27 Next Time Channels Components Chip packages, PCBs, Wires, Connectors Modeling Wires, Transmission Lines 27