Virtex-5 FPGA RocketIO GTX Transceiver Characterization Report

Transcription

1 Virtex-5 FPGA RocketIO GTX Transceiver Characterization Report PCI Express 2.0 (5.0 Gb/s) Electrical Gb/s) Standard Electrical Standard [optional] [optional]

2 Xilinx is disclosing this user guide, manual, release note, and/or specification (the Documentation ) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. PCI Express 2.0 Electrical Standard Report

3 Revision History The following table shows the revision history for this document. Date Version Revision 06/18/ Initial Xilinx Release. PCI Express 2.0 Electrical Standard Report

4 PCI Express 2.0 Electrical Standard Report

5 Table of Contents Revision History PCI Express 2.0 (5.0 Gb/s) Electrical Standard Characterization Report Introduction Test Conditions Transceiver Selection Summary of Results Electrical Characterization Details Transmitter Output Eye Test Methodology Test Results Transmitter Output Jitter and Peak Differential Output Voltage Test Methodology Test Results Transmitter Differential and Common Mode Return Loss Test Methodology Test Results Receiver Input Jitter Tolerance Test Methodology Test Results Receiver Differential and Common Mode Return Loss Test Methodology Test Results PCI Express 2.0 Electrical Standard Report 5

6 6 PCI Express 2.0 Electrical Standard Report

7 PCI Express 2.0 (5.0 Gb/s) Electrical Standard Characterization Report Introduction This characterization report compares the electrical performance of the Virtex -5 FPGA RocketIO GTX transceiver against revision 2.0 PCI Express specifications published in the PCI Express Base Specification Revision 2.0 and the PCI Express Card Electromechanical Specification Revision 2.0. Testing is based on a line rate of 5.0 Gb/s across voltage, temperature, and worst-case transceiver performance corners. This report includes test results for the PCI Express 2.0 specifications listed here: Transmitter Unit Interval Transmitter Output Jitter Transmitter Peak Differential Output Voltage Transmitter Differential and Common Mode Return Loss Receiver Input Jitter Tolerance Receiver Differential and Common Mode Return Loss Test Conditions Table 1 and Table 2 show the supply voltage and temperature conditions used in the PCI Express specification tests, respectively. Table 1: Supply Voltage Test Conditions Condition MGTAVCC (V) MGTAVCCPLL (V) MGTAVTTRX (V) MGTAVTTTX (V) V MIN V MAX Notes: 1. Other FPGA voltages stay at their nominal values. Table 2: Temperature Test Conditions Condition Temperature ( C) T T 0 0 T PCI Express 2.0 Electrical Standard Report 7

8 Transceiver Selection Transceiver Selection Transceiver channels are chosen to represent a mixture of transmitters and receivers having worst-case and typical performance based on volume generic characterization data. Transceivers with the absolute worst-case transmitter output jitter and receiver jitter tolerance are selected from the corner silicon used during generic volume characterization. The histograms in this characterization report do not show a true statistical representation that is normally present in a random (or even typical) population. The histograms are skewed toward the worst-case performance because of the transceiver selection and are not representative of the typical production silicon. Summary of Results Table 3 shows a comparison of the tested GTX transceiver performance against the revision 2.0 PCI Express specifications. The data reported in Table 3 represents values obtained under worst-case voltage, temperature, and performance corner conditions. Table 3: Revision 2.0 PCI Express Specification Characterization Summary of Results Test Parameter Specification Worst-Case Test Result Units Compliant Transmitter Unit Interval Min ps Yes Max ps Yes Transmitter Output Eye Width Eye Width (1) ps Yes Transmitter Output Deterministic Jitter DJ (1) ps Yes Transmitter Output Total Jitter TJ (1,2) ps Yes Transmitter Peak Differential Output Voltage Min 380 Programmable mv Yes Max 1200 Programmable mv Yes Transmitter Differential Return Loss Frequency Profile See Figure 12, page 18 db Yes Transmitter Common Mode Return Loss Frequency Profile See Figure 13, page 18 db Yes Receiver Input Jitter Tolerance TJ (not including SJ) See Table 10, page 20 (3) See Table 10 UI Yes 22.8 MHz (2) Not Defined UI Yes Receiver Differential Input Return Loss Frequency Profile See Figure 18, page 23 db Yes Receiver Common Mode Input Loss Frequency Profile See Figure 19, page 23 db Yes Notes: 1. With crosstalk. 2. BER = Jitter components and amplitude settings from the table called 5.0 GT/s Limits for Common Refclk Rx Architecture in the PCI Express Base Specification Revision 2.0. Electrical Characterization Details This section describes the test methodology used to characterize the GTX transceiver performance against the revision 2.0 PCI Express specifications. The results for each test are summarized in Table 3. The GTX transceiver is configured using version 1.5 of the 8 PCI Express 2.0 Electrical Standard Report

9 Virtex-5 FPGA RocketIO GTX Transceiver Wizard, including attribute settings. GTX transceiver attribute settings that differ from the GTX Transceiver Wizard default settings are identified in the Test Setup and Conditions table for each test. Table 4 shows the PLL settings used in the characterization. Table 4: Data Rate (Gb/s) 5.0 Gb/s Line Rate PLL Settings PLL Frequency (Gb/s) REFCLK Frequency (MHz) PLL_DIVSEL_REF PLL_DIVSEL_FB and DIV PLL_TXDIVSEL_OUT and PLL_RXDIVSEL_OUT x 5 = 10 1 Transmitter Output Eye Test Methodology While operating at nominal voltage and room temperature, the device under test is configured to transmit the PCI Express specification compliance pattern on each of the TX data pins. The resulting eye is captured using an Agilent Infiniium DSA91304A Digital Signal Analyzer. The add-in card setup, as shown in Figure 1, is used for measuring the output eye. This corresponds to the Add-In Card Transmitter Path Compliance Eye Diagrams at 5.0 GT/s from the PCI Express Card Electromechanical Specification (CEM) Revision 2.0 specification. PCI Express 2.0 Electrical Standard Report 9

10 X-Ref Target - Figure 1SMA M/F INNER Agilent Infiniium DSA91304A Digital Signal Analyzer 13 GHz - Gsa/s Display Miscellaneous Buttons Agilent E3631A 0-6V, 5A / 0-±25V, 1A On/Off Display Function Adjust Voltage/ Current ±25V + 6V + COM Agilent E3631A 0-6V, 5A / 0-±25V, 1A Display Adjust On/Off Gnd Aux Out Aux Trig Channel 1 Channel 2 Channel 3 Channel 4 On/Off Function Voltage/ Current ±25V + 6V + COM PCI Express Gen-2 Compliance Base Board R2.0 SMA to PCIe Adapter Card LANE0 RXN RXP TXN TXP CLKPCLKN TXP TXN LANE0 ICS874003AG-02-EVB VCC 3.3V VCCO 3.3V GND VEE DIP SWITCH nclk CLK nqa0 QA0 ICS BG -05 ML523 Virtex-5 FX70T FPGA Board RXN RXP TXN TXP CLKN CLKP Virtex-5 FX70T FPGA FF1136 MGTAVCC 1.0V AVCCPLL 1.0V AVTTTX 1.2V AVTTRX 1.2V GND Legend DC Blocks SMA Matched Pair Cables From PCIe Load Board TX to Scope SMA Matched Pair Cables From PCIe SMA Board RX to GTX TX SMA Matched Pair Cables From PCIe SMA Board CLK to ICS CLK SMA Matched Pair Cables From ICS CLK to GTX CLK Cable For 1.0 V PS Cable For 1.2 V PS Cable For 3.3 V PS Cable For Ground PS RPT119_01_ Figure 1: Transmitter Output Jitter and Peak Differential Output Voltage Test Setup Block Diagram Table 5 defines the test setup and conditions for the transmitter output eye. Table 5: Transmitter Output Eye Test Setup and Conditions Parameter Value Measurement Instrument TX Coupling Voltage Temperature Agilent Infiniium DSA91304A Digital Signal Analyzer AC coupled using DC blocks Nominal Room Temperature Pattern Compliant with the PCI Express specification, revision PCI Express 2.0 Electrical Standard Report

11 Table 5: Transmitter Output Eye Test Setup and Conditions (Cont d) Parameter Value Load Boards ML523 RocketIO Transceiver Characterization Platform, Revsion D with Virtex-5 FX70T FPGA (FF1136) SMA to PCIe Adapter Card PCIe Compliance Base Board, Version 2.0 ICS874003BG-05 evaluation board TX Amplitude and Pre-Emphasis REFCLK RocketIO GTX Transceiver Attributes: TXDIFFCTRL = 011 TXPREEMPHASIS = MHz sourced from the PCIe Compliance Base Board, Version 2.0 and the ICS874003BG-05 PCI Express Jitter Attenuator IC Test Results Figure 2 shows the transmitter output eye at 5.0 Gb/s. X-Ref Target - Figure 2 RPT119_02_ Figure 2: Transmitter Output Eye (5.0 Gb/s with 250 MHz REFCLK) Transmitter Output Jitter and Peak Differential Output Voltage Test Methodology Transmitter output jitter and the peak differential output voltage are measured using the test setup shown in Figure 1. An Agilent Infiniium DSA91304A Digital Signal Analyzer measures the transmitter output jitter using the methodology defined in the PCI-SIG document PCI Express 2.0 CEM Signal Quality Testing for Add-in Cards using Agilent DSO91304A, and DSA91304A 13 GHz Real-Time Oscilloscopes. The version of the SIGtest software used is PCI Express 2.0 Electrical Standard Report 11

12 An SMA to PCIe Adapter Card (Figure 3) is used in order to connect the ML523 board to the PCIe Compliance Base Board. X-Ref Target - Figure 3 RPT119_03_ Figure 3: ML523 Board with an SMA to PCIe Adapter Card Table 6 defines the test setup and conditions for the transmitter output jitter and peak differential output voltage tests. Table 6: Transmitter Output Jitter and Peak Differential Output Voltage Test Setup and Conditions Parameter Value Measurement Instrument TX Coupling Voltage Agilent Infiniium DSA91304A Digital Signal Analyzer AC coupled using DC blocks V MIN, V MAX Temperature T -40, T 0, T 100 Pattern Compliant with the PCI Express specification, revision 2.0 BER Load Boards ML523 RocketIO Transceiver Characterization Platform, Revsion D with Virtex-5 FX70T FPGA (FF1136) SMA to PCIe Adapter Card PCIe Compliance Base Board, Version 2.0 ICS874003BG-05 evaluation board TX Amplitude/Pre-Emphasis REFCLK RocketIO GTX Transceiver Attributes: TXDIFFCTRL = 011 TXBUFDIFFCTRL = 101 TXPREEMPHASIS = MHz sourced from the PCIe Compliance Base Board, Version 2.0 and the ICS874003BG PCI Express 2.0 Electrical Standard Report

13 Test Results Figure 4, Figure 5, and Figure 6 show histograms for the output jitter test results. Table 7 summarizes the maximum and minimum test result values. X-Ref Target - Figure 4 Number of Data points Eye Width Eye Width (ps) RPT119_04_ Figure 4: Transmitter Eye Width X-Ref Target - Figure 5 Number of Data Points DJ (ps) DJ RPT119_05_ Figure 5: Transmitter Deterministic Jitter PCI Express 2.0 Electrical Standard Report 13

14 X-Ref Target - Figure 6 16 Number of Data Points TJ (BER = ) TJ (BER = ) (ps) RPT119_06_ Figure 6: Transmitter Output Total Jitter (BER = ) Table 7: Transmitter Output Jitter Test Results Parameter Min Max Units Transmitter Output Eye Width ps Transmitter Output Deterministic Jitter ps Transmitter Output Total Jitter (BER = ) ps The revision 2.0 PCI Express Card Electromechanical Specification defines the transmitter peak differential output voltage between 380 mv to 1200 mv. Figure 7 shows the transmitter peak differential output voltage histogram. Table 8 summarizes the maximum and minimum test result values. X-Ref Target - Figure 7 Number of Data Points Peak Differential Output Voltage Peak Differential Output Voltage (mv) RPT119_07_ Figure 7: Transmitter Peak Differential Output Voltage Table 8: Transmitter Peak Voltage Output Parameter Min Max Units Transmitter Peak Differential Output Voltage (TXDIFFCTRL = 011, TXPREEMPHASIS = 0010) mv 14 PCI Express 2.0 Electrical Standard Report

15 Figure 8 shows the non-transition eye signal diagram from the SIGtest software. X-Ref Target - Figure Differential Signal (V) Unit Intervals RPT119_08_ Figure 8: Transmitter Non-Transition Eye Signal Diagram from SIGTest Figure 9 shows the transition eye signal diagram from the SIGtest software. X-Ref Target - Figure Differential Signal (V) Unit Intervals RPT119_09_ Figure 9: Transmitter Transition Eye Signal Diagram from SIGtest PCI Express 2.0 Electrical Standard Report 15

16 Figure 10 shows the SIGtest results displayed on the Agilent Infiniium DSA91304A Digital Signal Analyzer. X-Ref Target - Figure 10 RPT119_10_ Figure 10: Transmitter SIGtest Results Transmitter Differential and Common Mode Return Loss Test Methodology The PCI Express Base Specification Revision 2.0 defines the differential return loss measurement as 10 db or better from 50 MHz to 1.25 GHz, and as 8 db or better from 1.25 GHz to 2.5 GHz. Differential return loss includes contributions from on-chip circuitry, chip packaging, and any off-chip components related to the driver. This output impedance requirement applies to all valid output levels. The reference impedance for differential return loss measurements is 100Ω. The transmit common mode return loss measurement is defined as 6 db or better from 50 MHz to 2.5 GHz. The Vector Network Analyzer (VNA) interfaces to the host PC through a GPIB interface. After the measurement parameters are set, calibration begins. Four cables are included in the calibration process. VNA measurements are independent of voltage and are accurate up to 11 GHz. A digital multimeter (DVM) confirms the differential resistance is 100Ω before the measurement. Table 9 defines the test setup and conditions PCI Express 2.0 Electrical Standard Report

17 Table 9: Transmitter Differential and Common Mode Return Loss Test Setup and Conditions Parameter Value Measurement Instrument TX Coupling/Termination Voltage Temperature Frequency Sweep Test Fixture REFCLK Source Power HP8720ES Vector Network Analyzer Differential, DC coupled into 50Ω to GND Typical voltage Room temperature 50 MHz to 11 GHz (10 MHz steps) ML523 test fixture with 1-inch board trace using a lowprofile ZIF socket Not Used 0 dbm Averaging Calibration 1 Intermediate Frequency (IF) 100 Hz Figure 11 shows the setup for the return loss measurement. X-Ref Target - Figure 11 E1 port ES 20 GHz Vector Network Analyzer port 3 GPIB GPIB USB PC ChipScope Tool Serial port 2 port 4 RX - Pair E A DVM com I V+ GPIB 2 Ft. Green Cable OFF 5V TX - Pair 5VDC Plug + + 1V VCCINT + 2.5V VCCO + 2.5V VCCAUX - GND ON switch 122 RX0 TX0 122 TX1 RX1 126 RX0 TX0 126 RX1 TX1 50MHz TX1 118 RX1 DIFF RX1 114 TX1 RX0 118 TX0 RX0 114 TX0 RX1 112 TX1 OZTEC Socket FF1136 RX1 116 TX1 RX0 116 TX0 RX0 112 TX0 TE: 1-inch 114 ML TX1 RX1 120 RX0 TX0 124 TX1 RX1 124 TX0 RX0 DIFF 126 X0Y0 122 X0Y1 118 X0Y2 114 X0Y3 112 X0Y4 116 X0Y5 120 X0Y6 124 X0Y7 + 1V AVCC + 1V AVCCPLL + 1.2V AVTTTX + 1.2V AVTTRX - GND ACE PROG DONE INIT PC4 RPT119_11_ Test Results Figure 11: Return Loss Test Setup Block Diagram Figure 12 shows the transmitter differential output return loss measurement. PCI Express 2.0 Electrical Standard Report 17

18 X-Ref Target - Figure Loss (db) TXSDD11 PCIe Frequency (GHz) RPT119_12_ Figure 12: Transmitter Differential Return Loss Measurement Figure 13 shows the transmitter common mode output return loss measurement. X-Ref Target - Figure Loss (db) TXSCC11 PCIe Frequency (GHz) RPT119_13_ Figure 13: Transmitter Common Mode Return Loss Measurement Receiver Input Jitter Tolerance Test Methodology The receiver input jitter tolerance as defined by the PCI Express Base Specification Revision 2.0 is measured using the test setup shown in Figure 14. The BERTScope BSA75B-PCIE generates a CJTPAT pattern with different components of Random Jitter (RJ) and Deterministic Jitter (DJ) per the table called 5.0 GT/s Limits for Common Refclk Rx Architecture from the PCI Express Base Specification Revision 2.0. Part of the DJ in the form of ISI is added using 15 inches of FR4 through the Xilinx Quad Serial Loop Board. Sinusoidal Jitter (S J) is swept from 1 MHz to 80 MHz. The CJTPAT pattern is used in this test because it is a more strenuous specification test than the compliance test pattern. The GTX transceiver under test recovers the data and transmits the pattern back to the Error Detector input of the BERTScope, where bit errors are measured. The test setup is synchronous, with no PPM offset between the BERTScope data generator and the reference clock provided to the GTX transceiver under test PCI Express 2.0 Electrical Standard Report

19 X-Ref Target - Figure 14 + Clock Output + Clock Input BERTScope S BSA75B-PCIE 7.5 Gb/s PCIe Display Agilent E3631A 0-6V, 5A / 0-±25V, 1A On/Off Display Function Adjust Voltage/ Current ±25V + 6V + COM + Data Output + Data Input Gnd EXT Clock Pattern Generator HF Jitter Subrate Clock Trigger Marker TTL Level Error Detector Blank TTL Error Level Trigger USB Port Agilent E3631A 0-6V, 5A / 0-±25V, 1A On/Off Display Function Adjust Voltage/ Current ±25V + 6V + COM Xilinx Quad Serial Loop RevB ML523 Virtex-5 FX70T FPGA Board TXP TXN RXP RXN CLKN CLKP Virtex-5 FX70T FPGA FF1136 MGTAVCC 1.0V AVCCPLL 1.0V AVTTTX 1.2V AVTTRX 1.2V GND Legend DC Blocks SMA Matched Pair Cables For GTX Receiver SMA Matched Pair Cables For GTX Transmitter SMA Matched Pair Cables For GTX Clocks Cable For BERTScope Clock Input Cable For 1.0 V Power Cable For 1.2 V Power Cable For Ground RPT119_14_ Figure 14: Receiver Jitter Tolerance Setup Block Diagram PCI Express 2.0 Electrical Standard Report 19

20 Figure 15 shows the jitter injected to the GTX transceiver under test. In addition to all the jitter components added and amplitude settings applied as defined in Table 10, SJ is applied during the test. X-Ref Target - Figure 15 RPT119_15_ Figure 15: Receiver Jitter Tolerance Setup - Eye Diagram of Pattern with RJ and DJ Injected Table 10 defines the test setup and conditions for receiver jitter tolerance. Table 10: Receiver Jitter Tolerance Test Setup and Conditions Parameter Value Measurement Instrument RX Coupling Voltage BERTScope S BSA75B-PCIE, 7.5 Gb/s AC coupled using DC blocks V MIN, V MAX Temperature T -40, T 0, T 100 Pattern Injected Jitter and Amplitude Settings CJTPAT Sum of the following: High Frequency RJ ( MHz RMS jitter) = 3.4 ps RMS Low Frequency RJ (below 1.5 MHz RMS jitter) = 4.2 ps RMS High Frequency DJ = 88 ps Low Frequency DJ (33 khz REFCLK residual) = 75 ps Eye width = 120 ps Minimum/maximum pulse voltage ratio = 5 Receive eye voltage opening = 120 mvpp differential Common mode noise from RX = 300 mvpp SJ = Tested to Failure, Frequency Sweep = 1 MHz to 80 MHz BER (measured at 10-9, extrapolated to ) 20 PCI Express 2.0 Electrical Standard Report

21 Table 10: Receiver Jitter Tolerance Test Setup and Conditions (Cont d) Parameter Value Load Board ML523 RocketIO Transceiver Characterization Platform, Revsion D with Virtex-5 FX70T FPGA (FF1136) Xilinx Quad Serial Loop Board Attributes REFCLK RocketIO GTX Transceiver Attributes: PMA_CDR_SCAN = 27 h PMA_RX_CFG = 25 h0f44088 RXEQMIX = 2 b10 DFE Disabled DFECLKDLYADJ = 0 DFETAP1[4:0] = 0 DFETAP2[4:0] = 0 DFETAP3[4:0] = 0 DFETAP4[4:0] = 0 DFE_CAL_TIME[4:0] = 5'b00110 DFE_CFG[9:0] = 10 b MHz sourced from the BERTScope Test Results Figure 16 shows the receiver jitter tolerance SJ sweep. SJ is applied in addition to all the jitter components and amplitude settings as defined in Table 10. X-Ref Target - Figure Amplitude (UI) ,000 10, ,000 1,000,000 10,000, ,000,000 Frequency (Hz) RPT119_16_ Figure 16: Receiver Jitter Tolerance SJ Sweep Test Results (CJTPAT, BER = ) PCI Express 2.0 Electrical Standard Report 21

22 Figure 17 shows the SJ at 22.8 MHz. SJ is applied in addition to all the jitter components and amplitude settings as defined in Table 10. X-Ref Target - Figure Number of Data points SJ at 22.8 MHz SJ at 22.8 MHz (UI) RPT119_17_ Figure 17: Receiver Sinusoidal Jitter Tolerance at 22.8 MHz Test Results (CJTPAT, BER = ) Table 11 shows the minimum receiver SJ tolerance for 22.8 MHz. SJ is applied in addition to all the jitter components and amplitude settings as defined in Table 10. Table 11: Receiver Jitter Tolerance Test Results Parameter Test Condition BER Min SJ Tolerance Units Receiver Jitter Tolerance SJ at 22.8 MHz UI Receiver Differential and Common Mode Return Loss Test Methodology The receiver input differential and common mode return loss specification and setup are the same as Transmitter Differential and Common Mode Return Loss, page 16. Table 12 defines the test setup and conditions. Table 12: Receiver Differential and Common Mode Input Return Loss Test Setup and Conditions Parameter Value Measurement Instrument RX Configuration/Amplitude Voltage Temperature Frequency Sweep HP8720ES Vector Network Analyzer RX configured for 100Ω differential termination (center tap to GND), AC coupled using both internal and external capacitors Typical voltage Room temperature 50 MHz to 11 GHz (10 MHz steps) 22 PCI Express 2.0 Electrical Standard Report

23 Table 12: Receiver Differential and Common Mode Input Return Loss Test Setup and Conditions (Cont d) Parameter Value Test Fixture REFCLK Source Power ML523 RocketIO Transceiver Characterization Platform, Revsion D with Virtex-5 FX70T FPGA (FF1136) with 1-inch board trace using a low-profile ZIF socket Not Used 0 dbm Averaging Calibration 1 Intermediate Frequency (IF) 100 Hz Test Results Figure 18 shows the receiver differential input return loss measurement. X-Ref Target - Figure Loss (db) RXSDD11 PCIe Frequency (GHz) RPT119_18_ Figure 18: Receiver Differential Input Return Loss Measurement Figure 19 shows the receiver common mode input return loss measurement. X-Ref Target - Figure Loss (db) RXSCC11 PCIe Frequency (GHz) RPT119_19_ Figure 19: Receiver Common Mode Input Return Loss Measurement PCI Express 2.0 Electrical Standard Report 23

24 24 PCI Express 2.0 Electrical Standard Report