UNIVERSITY OF HONG KONG DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING

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1 UNIVERSITY OF HONG KONG DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING Experiment PCO: Principles of Computer Operation Location: Part I Lab., CYC 102. Objective: The objective is to learn the basic principles of computer operation. A simple micro-controller system is used for illustration. The process of fetching and executing instructions is studied by using a logic analyzer to examine bus activities and signals. Apparatus: Computer and software: An IBM PC, an M68HC11 micro-controller board and debugging software. Assembly language code: sci_com2.asm, sci_com2.s19. Downloader programme: m68download_v2.exe. Equipment: Logic analyzer (Agilent mixed signal oscilloscope MSO6034A), and a dc power supply unit. Introduction: A simplified block diagram of a micro-processor system is given in Fig. 1. A brief introduction is given below. Please refer to the lecture notes and textbook for more details. Memory Contains program codes and data. A program consists of a sequence of instructions. Program Counter (PC) It is a register that contains the address of the next instruction byte to be fetched from memory into the CPU. The control unit (timing & control block) sends the necessary enable signals to the PC to place the PC's content onto the address bus. The PC's content is then incremented automatically to point to the next instruction byte in memory. Data Address Register (DAR) It holds the address of the operand to be fetched from memory into the CPU. Again the control unit provides the signals to place DAR's content onto the address bus. Page 1 of 13

2 (Control unit) Fig. 1 Block diagram of a micro-processor system (from Ref. 1) Instruction Register (IR) and Control Unit To fetch an op-code from memory, the control unit generates signals to (i) put the content of the PC (= address of the op-code byte) onto the address bus, and (ii) set R/W'=1 to initiate a read from memory. With the given address, the memory unit gets the op-code byte from the memory cells, and puts the byte onto the data bus. The control unit generates signals to copy the byte into the Instruction Register (IR). Hence the IR contains the op-code. The decoder circuit decodes the op-code, and signals the control unit to generate the required sequence of control signals to complete the execution of the given instruction. Information about the sequence of control signals to be generated (called a microprogram) is stored in the control unit. Page 2 of 13

3 Accumulator (A) & Data Register (DR) The operands to be operated on are read from memory and copied into these two registers. The ALU then performs the required operation and the result is put into accumulator A. Execution of a program As an example, let the instruction to be fetched and executed be LDAA $1080 ; read the operand at memory address $1080 into accumulator A Since the op-code for LDAA is $B6, the complete instruction is coded as $B Let the instruction be stored at memory address $00A0. Hence the memory contains: Address (Hex) Content (Binary) Content (Hex) 00A B6 (op-code) 00A (operand address) 00A (operand address) operand operand Steps to execute this instruction: 1. The PC contains the instruction address $00A0. The control unit loads this address onto the address bus and asserts the R/W' (read) signal. The memory unit puts the addressed byte onto the data bus and the control unit gets it into the Instruction Register. The byte obtained is $B6. The CPU treats it as the op-code. The PC is incremented by The control unit decodes this op-code and finds it to be LDAA. Hence it knows the operand address is stored at the next two memory addresses. So it fetches the byte from memory at address $00A1 into the Data Address Register. The byte obtained is $10 which is treated as the higher byte of the operand address. The PC is incremented by A further memory read at address $00A2 is performed to read the lower byte of the operand address which is $80. The complete operand address is thus $1080 which is stored in the Data Address Register of the CPU. The PC is incremented by The control unit fetches the operand byte from memory at address $1080 into Accumulator A. Execution of the instruction ends. After executing the current instruction, the CPU fetches the next instruction, decodes and executes it. This continues until all instructions in the program have been executed. In summary, the phases of executing an instruction are: 1. Instruction fetch 2. Instruction decode 3. operand fetch 4. execution 5. store back result (if needed). Page 3 of 13

4 Experimental Circuit: A board with an MC68HC11 micro-controller is used in this experiment. The board contains a number of peripheral devices. However, for this experiment, we may just consider the simple memory circuit as given in Fig. 2. Since the lower address byte A7...A0 and data byte D7...D0 are time-multiplexed, an address latch 74HC373, which consists of 8 level-triggered D-type flip-flops, is used to provide a stable address. The AS (address strobe) signal from the micro-controller is used to activate the latch. When AS is high, the CPU outputs an address, and the output pins Q7...Q0 of the 74HC373 contains the address. When AS goes low, the address at Q7...Q0 is locked and remains unchanged until the next AS pulse arrives. A 32-kbyte memory chip is connected. Memory is accessed by using the signals R/W' and E. Timing of the bus signals for the read operation is illustrated in Fig.3. Address latch kByte SRAM Connect jumpers for bootstrap mode Fig. 2 Schematic diagram of a micro-controller system (adapted from Ref. 1) Page 4 of 13

5 Fig. 3 CPU read timing (from Ref. 1) The reading operation as illustrated in Fig. 3 consists of the following steps. 1. At the rising edge of AS (Point 1), the CPU sets R/W' to 1 to indicate read, and puts the address on the pins of Ports B and C. 2. If the memory read is an instruction fetch, the PC is incremented at the rising edge of PH2 (Point 2). 3. At the falling edge of AS (Point 3), the address bits A0-A7 are latched, and the address bus holds the 16-bit address until the next AS pulse arrives. 4. At the rising edge of E-clock (Point 4), the selected memory or I/O device is enabled, and the device begins putting data onto the data bus. After a while, valid data appears on the data bus. 5. At the falling edge of the E-clock (Point 5), the CPU latches the data from the data bus into its internal register such as the instruction register. Page 5 of 13

6 Main theme of this experiment In this experiment, a sample program is to be downloaded into the memory chip of the micro-controller board and executed. A logic analyzer is used to probe the signals on the address, data and control buses. By looking at the signals, the instruction fetch and execution cycles can be readily appreciated. Sample program The sample program is given in Appendix 1. The program starts at address $8080. It consists of only a few instructions which repeatedly reads and writes memory address $B0F0. To load the program to the target address, a 2-stage bootstrap process is adopted in our experiment. Upon reset, the primary bootstrap program in the micro-controller's internal ROM is executed. This program starts communicating with the host PC through the RS232 port and downloads a secondary bootstrap program from the host PC to address $0000 in the internal RAM of the micro-controller. After the download, the PC (program counter) is set to zero and the secondary bootstrap program at address $0000 starts to execute. This program communicates with the host PC and downloads the user program to the memory chip on the micro-controller board. The 2-stage bootstrap process is needed because upon reset, the primary bootstrap program executes in special bootstrap mode in which only the internal RAM (512 bytes) of the micro-controller can be accessed. Since the user program in our case has to reside in external memory, a secondary bootstrap program is needed to switch the microcontroller to normal expanded mode (in which external memory can be accessed) and to load the user program to external memory. The secondary bootstrap program is given in Appendix 2 (available from course web site). Since our user program is very short, for the sake of convenience, it is included inside the secondary bootstrap program so that it is downloaded together with the secondary bootstrap program and does not need to be downloaded separately. Page 6 of 13

7 Procedure: 1. Copy (or download from course web site) the secondary bootstrap program sci_com2.asm as given in Appendix 2 into a text file in your PC. Assemble it using the THRSim11 software. Two files will be generated: sci_com2.s19 (available from course web site) and sci_com2.lst. The former is a listing file showing the assembled hex code while the latter contains the executable code in Motorola's S19 text format. 2. Follow the procedures in Appendix 3 to set up the microcontroller board. 3. Connect the micro-controller board to the COM1 port of the PC using the RS232 cable. Connect a 9-V dc supply to the board's power supply jack. 4. We need to observe 19 digital signals. Since there are only 16 logic probes on the mixed signal oscilloscope, we have to use 3 analogue probes as well. Connect the probes to the signal pins on the board as follows: Analogue channel 1: AS (address strobe) Analogue channel 2: E Analogue channel 3: R/W' (read/write') Digital channels 8-15: A8, A9,..., A15 Digital channels 0-7: AD0, AD1,..., AD7 Gnd: Ground (note that each of the two pods and each analogue probe has a ground pin and ALL five pins have to be connected to ground) 5. Switch on the logic analyzer (mixed signal oscilloscope). Follow the procedures in Appendix 4 to set up the logic analyzer for capturing waveforms. 6. Download the program to the micro-controller board as follows. Switch on the 9-V dc power supply to the micro-controller board. Press the RESET button on the board. The micro-controller undergoes a power-on reset cycle and executes the primary bootstrap program. The micro-controller is now ready to receive bytes from the host PC through the RS232 link. On the host PC, run the program m68download_v2.exe. When prompted, enter the full path and name of the file (sci_com2.s19, available from course web site) to be downloaded to the board. Press the ENTER key. The program code will be downloaded to the micro-controller board. After downloading, the program on the micro-controller board will be executed automatically. 7. Run the logic analyzer by pressing the SINGLE button. The logic analyzer will be triggered when the CPU reads from address $8087. Set the time base such that at least 4 complete bus cycles (E clock cycles) are displayed on the logic analyzer. A suitable setting is 200ns/division and 850 ns delay. If the delay is incorrectly set, part or all of the required waveform will be shifted out of the screen. As a check, the first address appearing on the lower left corner of the screen should be $8087. Study the 19 waveforms. Identify the 4 bus cycles beginning at the triggering point. Compare with the read cycle timing diagram of the M68HC11 (Fig. 3 of this instruction sheet). 8. It is convenient if the 16 address values can be displayed in Hex notation. This can be done as follows. Page 7 of 13

8 Press the "D15 Thru D0" button. On the bottom of the screen, press the BUS softkey. Select BUS1 by turning the knob situated below the clockwise arrow on the panel. Then press the BUS1/BUS2 softkey to switch on BUS1. Use the softkeys on the bottom of the screen to select channels D15-D8 and D7-D0 for inclusion into BUS1. The binary values for the 16 address signals should now be displayed as hex values for BUS1 at the bottom of the screen. You can label BUS1 as AD. 9. Check that the address and data signals are as expected (refer to the listing in Sample_program.lst in Appendix 1 for the codes that should appear on the address and data buses). 10. Measure the time t D between the correct address appearing on the address bus to the time valid data appearing on the data bus. 11. Save the waveforms on the screen to a bitmap file as follows. Plug in a USB thumb drive on the front panel. Press the UTILITY button, then press the PRINT CONFIG softkey. Press the PRINT TO softkey and select the 24-bit BMP bitmap file format. Press the QUICK PRINT button. The waveform on the screen will be saved as a file in the USB drive. Report: [Note: (i) Each student has to do the report independently and submit an individual report. (ii) Submit the report in.pdf format. ] 1. Paste the recorded waveform into the report. By referring to the listing in Sample_program.lst in Appendix 1, explain which instruction of the program in Appendix 1 corresponds to the observed waveform. 2. Explain the waveforms by mapping each cycle to a different phase of execution of the target instruction. From the recorded waveforms, read the values on the address and data buses at various instants and compare them with the values expected from the execution of the target instruction. Is there any discrepancy? 3. Report the value of the time delay t D measured in Step 10 of the procedures. Assume that the circuit is as given in Fig. 2. By referring to the timing diagram in Fig. 3 and the actual waveforms captured in Step 11, explain the causes of this time delay t D. Note that the access time t AA (the time from address valid to data valid) of the SRAM chip is 70 ns. 4. Explain any difficulties encountered in the experiment. References: 1. R.J. Tocci and F.J. Ambrosio, Microprocessors and Microcomputers, 6 th Edition, Prentice Hall, M68HC11 Reference Manual 3. M68HC11 Technical Data. Page 8 of 13

9 Appendix 1: -- Sample Program Sample_program.asm * This program starts at address $8080, and * repeatedly writes and reads memory address $B0F0. ORG $8080 ;start of program ldaa #$55 ;get data to be stored loop staa $B0F0 ;store data to target address ldaa #$00 ;clear A ldaa $B0F0 ;read back data from target address bra loop ;repeat indefinitely Sample_program.lst Address Code ORG $8080 ;start of program ldaa #$55 ;get data to be stored 8082 B7 B0 F0 loop staa $B0F0 ;store data to target address ldaa #$00 ;clear A 8087 B6 B0 F0 ldaa $B0F0 ;read back data from target address 808A 20 F6 bra loop ;repeat indefinitely Symbol Table LOOP 8082 Page 9 of 13

10 Appendix 2: -- Secondary Bootstrap Program (file: sci_com2.asm, available from course web site) * Upon reset, the primary bootstrap program in ROM is executed. Its job is * to download this secondary bootstrap program from the host PC into the * internal RAM of the micro-controller at address $0000. The secondary * bootstrap program is then executed. It in turn copies the user program * as given in Appendix 1 to external memory (at address $8080) and * initiates the execution of the user program. * * For the sake of convenience, the short user program is included in the * body of this secondary bootstrap program so that there is no need * to download the user program from the host PC. ORG $0000 ;start of RAM ext_mem equ $8080 ;address of instruction in external memory block equ $0080 ;address of instruction block to be copied hprio equ $3C ;hprio register lower nibble address start ldx #$1000 ;set X to register base address bset hprio,x $20 ;set micro-controller to expanded mode bclr hprio,x $40 ;set micro-controller to normal mode ldx #block ;pointer to local block code ldy #ext_mem ;pointer to external memory loop1 ldaa 0,x ;get one byte from local block staa 0,y ;store in external memory inx ;increment pointer iny ;increment pointer cpx #last ;reached the end of block? blo loop1 ;not yet, loop back for another transfer jmp ext_mem ;jump to execute code in external memory ORG block ;start of block code to be copied to external memory ldaa #$55 ;get data to be stored loop2 staa $B0F0 ;store data to target address ldaa #$00 ;clear A ldaa $B0F0 ;read back data from target address bra loop2 ;repeat indefinitely last equ * ;last address Page 10 of 13

11 Appendix 3: -- Procedures to set up the Micro-controller Board 1. Check that the "62256" SRAM chip is installed in Socket U6 (instead of U5). 2. Set the jumpers as follows. Note: ON means jumper installed (i.e., short-circuit the two pins) OFF means jumper not installed (i.e., pins not short-circuited) MODA = ON, JP3 = ON, JP5 = OFF, JP7 = ON, JP9 = OFF, MODB = ON JP4 = ON, JP6 = ON, JP8 = OFF, WRITE_EN = OFF, MEM_EN = ON, SYNC = ON, TRACE = ON, PROG = OFF, Page 11 of 13

12 Appendix 4: -- Procedures to set up the Logic Analyzer (Mixed Signal Oscilloscope) for Waveform Capture 1. Connect the two logic pods (each with 8 logic probes) to the back of the logic analyzer. Switch on the logic analyzer. 2. Press the "D15 Thru D0" button. The 16 digital channels will be displayed on the screen. On the bottom of the screen, press the leftmost softkey to change the size of the digital display to half of the screen's height. Press the THRESHOLDS softkey. Select CMOS for channels D15-D8 and D7-D0. This sets the threshold voltages for logic 1 and 0 according to CMOS devices. 3. Turn on analogue channels 1 by pressing the buttons 1. Set the voltage scale to 5V per division for each channel. Check that the input impedance is set at 1 M Ohm (as shown at the bottom of the screen). Press the PROBE softkey (at the bottom of the screen). Check that the probe impedance ratio shown is the same as that marked on the probe. Now the screen should show 19 signal traces. 4. Label the channels as follows. Press the LABEL button. Then press the CHANNEL softkey. Select analogue channel 1 by turning the Selection Knob (near the top left corner of the panel, below the clockwise arrow). Label the channel as 'AS' by pressing the softkeys (press SPELL; turn the Selection Knob to select character A, press ENTER; repeat for character S, then press APPLY NEW LABEL). Similarly label analogue channels 2 and 3 as 'E' and 'R/W~' respectively. Label digital channels D0 to D7 as 'AD0' to 'AD7' respectively. Label digital channels D8 to D15 as 'A8' to 'A15' respectively. 5. Set the logic analyzer to operate in pattern trigger mode. Set the trigger pattern as follows by pressing the PATTERN button: D15, D14, D13,..., D0 = HLLL LLLL HLLL LHHH (L = low, H = high, i.e., set triggering address to $8087) Analogue channel 1 = falling edge (i.e., falling edge of AS) Analogue channel 2 = X (i.e., don't care for E) Analogue channel 3 = H (i.e., R/W' = 1 for read operation) Analogue channel 4 = X (i.e., don't care for the unconnected channel) Page 12 of 13

13 6. We need to set the threshold for deciding whether a logic signal is high or low. For the digital channels, this has already been done in Step 2 above. We need to set the thresholds for the analogue channels as follows. Press the CHANNEL softkey and select Analogue channel 1 by turning the Selection knob (below the clockwise arrow). Set the threshold level to 2.5V by turning the LEVEL knob (near to top right corner of the panel). The threshold voltage is shown on the top right corner of the screen. Similarly set the threshold for Analogue channel 3 to 2.5V. 7. Press the MODE button on the panel, then press the MODE softkey at the bottom of the screen. Select NORMAL MODE. The logic analyzer will be triggered if the 19 input signals are as specified (i.e., a read operation at address $8087). Problems with setup 1. Undo Auto-Scale In case you pressed the AUTOSCALE button and the displayed format is not acceptable, you may undo it by pressing the UNDO AUTOSCALE softkey. It will return to the configuration immediately before the AUTOSCALE button was pressed. 2. Reset to Factory Default Setup To rest to factory default setup, press the SAVE/RECALL button, then press the DEFAULT SETUP softkey. Page 13 of 13

UNIVERSITY OF HONG KONG DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING. Principles of Computer Operation

UNIVERSITY OF HONG KONG DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING Experiment PCO: Principles of Computer Operation Location: Part I Lab., CYC 102. Objective: The objective is to learn the basic