ni.com Best Practices for Architecting Embedded Applications in LabVIEW

Transcription

1 Best Practices for Architecting Embedded Applications in LabVIEW

2 Overview of NI RIO Architecture PC Real Time Controller FPGA 2

3 Where to Start? 3

4 Requirements Before you start to design your system, you must first have an understanding of what you want your system to do. Requirements are often difficult to discern at the beginning of a project, and tend to change over time. These are the key requirements that typically drive a design: Data acquisition rates Channel count Control loop rates and latencies Level and timing of data analysis o Offline, online, inline Data destinations o Log all raw data to disk o Display all data on PC UI 4

5 Build with Modular Processes Break up the application into numerous (typically 5-8) independent, freerunning processes Each process is a loop, in a subvi Each process should be responsible for one aspect of the system Limit the state data that needs to be shared between processes 5

6 Assign Processes to the Right Target PC RT FPGA PC Inline analysis Offline processing and analysis User Interface Long-term data storage Enterprise interface o SQL Database o OPC Online analysis Temporary data storage Closed-loop control (100 us ms time scales) Peripheral interface o Modbus o Serial o CAN/LIN Closed-loop control (10s of ns us time scales) Anything related to safety or time-critical operation Digital hardware interface o I2C o SPI Real-Time FPGA 6

7 Accessing IO: NI Scan Engine Provides single-point access to I/O channels using a scan that stores and updates data in a global memory map Updates all values concurrently at a single rate (Scan Period) CompactRIO Scan Mode Interface LabVIEW Real-Time NI Scan Engine RT VI I/O Variables I/O memory table FPGA RIO Scan Interface I/O Modules I/O Modules 7

8 Accessing IO: Scan Engine vs FPGA Scan Engine: Continuous single point acquisition Scalar data Scan rates below ~1 KHz o CPU usage scales with scan rate higher-performance targets can handle higher scan rates. Pre-written, easy access to data No FPGA programming required FPGA Custom triggering Waveform or scalar data Acquisition rates to ~ 1 MHz Requires writing FPGA code, allows full control 8

9 Accessing IO: Hybrid Mode Can choose what IO mode to use for each module Location in project tree determines mode Scan Interface Mode I/O LabVIEW FPGA Interface Mode I/O 9

10 Available LabVIEW Data Communication APIs Local Process Local Variable Global Variable Single-Process Variable Functional Global Variable Network Variable Queues Dynamic Variables Notifiers Time-Triggered Variable RT FIFOs Web Services User Events Datasocket Data Value Reference Shared Memory Current Value Table (CVT)* Tag Bus(*) NI Pipes Network TCP UDP Network Streams Simple TCP Messaging (STM)* Asynchronous Message Communication (AMC)* FTP HTTP WebDAV 10 FPGA Memory Item Register Target Scoped FIFO VI VI Defined FIFO DRAM FIFO DMA FIFO Read/Write Controls User Defined IO Variables Peer-to-Peer (P2P) PXImc *SE Maintained

11 Three Fundamental Communication Paradigms Lossy Current value Lossless High throughput Buffered data Reliable delivery Low latency 11

12 Three Fundamental Communication Paradigms Global and Local Variables Network Published Shared Variables Tag Bus Current Value Table (CVT) FPGA Registers Scan Engine I/O Variables Network Streams TCP/IP Queues RT FIFOs FPGA FIFOs 12 TCP and UDP Network Streams Queues and Notifiers User Events RT FIFOs FPGA / RT FIFOs FPGA Handshakes FPGA IRQs

13 FPGA Internal Communication Tags: Registers Local\Global Variables Messages: Handshake Target (or VI)-scoped FIFO Streams: Target (or VI)-scoped FIFO Memories PC RT FPGA 13

14 FPGA External Communication Tags: FPGA Front Panel User-Defined Variable (if using Scan Engine) Messages: Interrupt DMA FIFO Streams: DMA FIFO PC RT FPGA 14

15 RT Internal Communication Tags: Current Value Table Single-Process Shared Variables (no RT FIFO) Global Variables Messages: Queue RT FIFO User Events Streams: RT FIFO Queue Single-Process Shared Variable (with RT FIFO) PC RT FPGA 15

16 RT to HMI Communication Tags: Network-Published Shared Variable Web Service Messages: Network Stream STM TCP Web Service Streams: Network Stream UDP TCP PC RT FPGA 16

17 Typical RT Modules Acquisition/Control (main logic) Incoming Message Handler System Health Monitor Central Error Handler Debug Trace Logger Watchdog 17

18 Error Management Each process should attempt to handle (or ignore) its own errors If the scope of an error requires higher-level action, this action should be triggered by the central error handler One and only one process should log errors, all other processes forward errors to be logged Leverage existing reference designs and components Sample Projects Structured Error Handler Tag Bus 18

19 Central Error Handling Framework Command Receiver Specific Loop Handler UI message handling loop Specific Watchdog Loop Handler Specific Monitoring Loop Handler 19

20 System Health Continuously monitor and report critical system health tags CPU usage Memory usage Disk usage Delete older log/acquisition files if disk usage is high Controlled restart if available memory or CPU usage crosses a threshold Consider also using this process to control LEDs to visually inform users of system status 20

21 Trace Logging Single process responsible for logging trace data Expose a simple API for other processes to send trace strings This permits changes to the logging method without impacting other processes Simplifies field debugging Consider Syslog for network transmission of trace data 21

22 Trace Log - Example One file avoids ms timestamp problems Correlation of events to errors 22

23 Watchdogs A watchdog timer is a hardware counter that interfaces with the embedded software application to detect and recover from software failures A user can then: Reboot real-time target automatically Perform user-defined recovery actions Two types of watchdogs with NI Real-Time hardware: LabVIEW Real-Time Watchdog Real-Time <-> FPGA Watchdog (FPGA Fail Safe Design) 23

24 LabVIEW Real-Time Only Watchdog Uses hardware timer built into CompactRIO hardware Reset = True reboots system if the watchdog process is starved 24

25 LabVIEW Real-Time Watchdog Enable occurrence in expiration actions Configure appropriate watchdog timeout and Watchdog Whack loop period 25

26 Real-Time <-> FPGA Watchdog Reset timer Put control loop into a safe state, and reset system 26

27 Watchdog Typically, embedded systems are meant to run reliably for long periods of time. They may be deployed to remote or inaccessible locations. If the system encounters a problem that is not accounted for in software, it is valuable for the system to recover itself from a failure. NI embedded controllers feature a built-in hardware timer that can automatically reboot the controller if the timer expires Enable the watchdog in your embedded application to provide a failure recovery mechanism for unexpected conditions 27

28 Watchdogs Types of watchdogs FPGA Watchdog Can set I/O to safe states Can reboot RT target LabVIEW Real-Time Watchdog Can reboot RT target 28

29 Configuration Any item that is a constant on the diagram or entered via the front panel of an RT VI should be considered for inclusion in a configuration file instead Use a lookup table, such as the Current Value Table, to make configuration parameters available throughout the application Use a human-readable format for your configuration files Consider using a tool, such as the Configuration Editor Framework (CEF), to help create a user application to edit your configuration files. 29

30 LabVIEW for CompactRIO Sample Projects Pre-built architectures for embedded control and monitoring applications Designed to ensure quality and scalability of a system 30

31 FPGA Control with Sequencer Sample Project 31

32 Real-Time Control Sample Project 32

33 FPGA Waveform Acquisition and Logging 33

34 Further Reference CompactRIO Developer s Guide: /compactriodevguide/ NI-created reuse code: /referencedesigns/ LabVIEW add-ons: /labview-tools-network/ 34

35 Embedded Control and Monitoring Using LabVIEW Training course for new CompactRIO and Single-Board RIO users Configure and build an embedded project in one week Requirements definition though deployment LabVIEW Real-Time and LabVIEW FPGA Topics include I/O, system timing, data communication, optimization, debugging, benchmarking, deployment 35

36 Embedded Control Specialty Partners NI Alliance Partners who have demonstrated experience in designing medium to large scale control and monitoring applications Significant, architect-level expertise with LabVIEW and CompactRIO, Single-Board RIO, and/or R Series devices Ready to help you achieve your goals /alliance/embedded-control 36