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5 Size:31.60*20.70*3.90mm 8dBm :-99dBm :107dB Sleep mode:<2.0µa RX mode:29ma TX EM351/EM357: 128K/192K bytes Flash;12K bytes RAM STM32W:128K bytes Flash; 8K bytes RAM 1 x 1 x TW 1 x SP/ 2 C PCB board, good ESD/EMC protection ability. SM FCC certified:fcc D:46RY12M01

6 1 1.5 ADC AP DC DTR DP EEPRM ESD GP HAL HVAC HW TW EEE RQ SM JTAG MAC MCU NWK EM TA PCB PER PHY RAM RF RTS/CTS RX SMA SP SW TX UART Analog-to -Digital Converter Application Programming nterface Direct Current Data Terminal Ready Dual n-line package Electrically Erasable Programmable Read-nly Memory Electrostatic Discharge General Purpose nput/utput Hardware Abstraction Layer Heating, Ventilating and Air Conditioning Hardware nter-ntegrated Circuit nstitute of Electrical and Electronics Engineers nterrupt Request ndustrial, Scientific and Medical radio band Digital interface for debugging of embedded device, also known as EEE standard interface Medium Access Control layer Microcontroller Unit. n this document it also means the processor, which is the core of ZigBee module Network layer riginal Equipment Manufacturer ver-the-air upgrade Printed Circuit Board Package Error Ratio Physical layer Random Access Memory Radio Frequency Request to Send/ Clear to Send Receiver Surface Mount Assembly Serial Peripheral nterface Software Transmitter Universal Asynchronous Receiver/Transmitter

7 2 USART Universal Synchronous/Asynchronous Receiver/Transmitter USB Universal Serial Bus ZDK ZigBee Development Kit ZigBeePR Wireless networking standards targeted at low-power applications The EEE standard applicable to low-rate wireless PAN 1.6 [1] EEE Std EEE Standard for nformation technology - Part 15.4 Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) [2] ZigBee Specification. ZigBee Document r17, ctober 19, 2007

8 Figure 2-1. XTAL (Crystal Frequency 24MHz) Cortex M3 Core Data Program Power Management -QPSK Modem RAM 12kB Flash 192kB SP TW EEE MAC Accelerator ARM CRTEX-M3 CPU with NVC and MPU Timers UART 2.4GHz Radio Encryption Accelerator GP registers Antenna Balun Matching Network

9 Parameters Min Max Power supply range(vcc) 2.1V 3.6V Pin working voltage range (except ADC pin) -0.3V VDD_PADS+0.3 ADC pin working voltage range -0.3V 2.0V Max drive current data for all / Max RX RF levle 40 ma +10dBm Parameter Range Unit, VCC 2.1 to 3.6 V RX current 29 ma TX current(@3dbm) 36 ma TX current(@8dbm) 45 ma Sleeping current <2.0 μa TX power -32 to +8 dbm

10 Parameter Condition Range Unit 2400~ MHz 16 0B~1A Hex 5 MHz -32 to +8 dbm Packct Loss 1% -99 dbm 250 kbps For unbalanced output 50 Ω Parameter Condition Range Unit 192KB bytes 12KB bytes 24 MHz Parameter Condition Range Unit bps 12/4096 Bits/µs >1 MΩ 1.2 V 0 - VREF V 400 KHz (Logical 0) -8/ 4 ma 0 ~ 0.18*VCC V (Logical 1) -8/ 4 ma 0.82*VCC ~ VCC V

11 KHz 3.2. Parameter Value Remark Size 31.60*20.70*3.90mm Weight 3.6g Working temp. -40 C to +85 C perating Relative Humidity Range <95% 3.3. Picture 3-7. Size Picture 3-8. Package

12 Picture

13 8 Figure Pin instruction Module Pin No. 1 2 QFN48 Pin No. Signal Direction Description 3.3V DC3.3V supply PC5 / Digital /; 3 11 TX_ACTV E Logic-level control for external Rx/Tx switch. The STM32W108 baseband controls TX_ACTVE and drives it high (VDD_PADS) when in Tx mode. Select alternate output function with GP_PCCFGH[7:4] PC6 / Digital /; khz crystal oscillator Select analog function SC32B / with GP_PCCFGH[11:8] ntx_act nverted TX_ACTVE signal (see PC5) Select VE alternate output function with GP_PCCFGH[11:8] PC7 / Digital / SC khz crystal oscillator. Select analog / A function with GP_PCCFGH[15:12] SC32_EX Digital 32 khz clock input source T / High Digital /. Disable REG_EN with PA7 current GP_DBGCFG[4] Timer 1 Channel 4 output Enable timer output with TM1_CCER Select alternate output function with TM1_CH4 GP_PACFGH[15:12] Disable REG_EN with GP_DBGCFG[4] Timer 1 Channel 4 input. (Cannot be remapped.)

14 9 Module QFN48 Pin No. Pin No. Signal Direction Description REG_EN External regulator open drain output. (Enabled after reset.) 7 12 nreset Active low chip reset (internal pull-up) PB3 / Digital / Timer 2 channel 3 output Enable remap with TM2_CH3 TM2_R[6] Enable timer output in TM2_CCER Select alternate output function with GP_PBCFGL[15:12] Timer 2 channel 3 input. Enable remap with TM2_R[6]. UART CTS handshake of Serial Controller UART_CTS Enable with SC1_UARTCFG[5] Select UART with SC1_MDE SP master clock of Serial Controller 1 Either disable timer output in TM2_CCER or disable remap SC1SCLK with TM2_R[6] Enable master with SC1_SPCFG[4] Select SP with SC1_MDE Select alternate output function with GP_PBCFGL[15:12] SP slave clock of Serial Controller 1 Enable slave with SC1_SPCFG[4] Select SP with SC1_MDE PB4 / Digital / Timer 2 channel 4 output Enable remap with 9 20 TM2_CH4 UART_RTS TM2_R[7] Enable timer output in TM2_CCER Select alternate output function with GP_PBCFGH[3:0] Timer 2 channel 4 input. Enable remap with TM2_R[7]. UART RTS handshake of Serial Controller 1 Either disable timer output in TM2_CCER or disable remap with TM2_R[7] Enable with SC1_UARTCFG[5] Select UART with SC1_MDE Select alternate output function with GP_PBCFGH[3:0] SC1nSSEL SP slave select of Serial Controller 1 Enable slave with SC1_SPCFG[4] Select SP with SC1_MDE PA0 / Digital / Timer 2 channel 1 output Disable remap with TM2_CH1 TM2_R[4] Enable timer output in TM2_CCER Select alternate output function with GP_PACFGL[3:0] Timer 2 channel 1 input. Disable remap with TM2_R[4].

15 10 Module Pin No. QFN48 Pin No. Signal Direction Description SC2MS SP master data out of Serial Controller 2 Either disable timer output in TM2_CCER or enable remap with TM2_R[4] Enable master with SC2_SPCFG[4] Select SP with SC2_MDE Select alternate output function with GP_PACFGL[3:0] SP slave data in of Serial Controller 2 Enable slave with SC2_SPCFG[4] Select SP with SC2_MDE PA1 / Digital / Timer 2 channel 3 output Disable remap with TM2_CH3 TM2_R[6] Enable timer output in TM2_CCER Select alternate output function with GP_PACFGL[7:4] Timer 2 channel 3 input. Disable remap with TM2_R[6]. TW data of Serial Controller 2 Either disable timer output in TM2_CCER or enable remap with SC2SDA / TM2_R[6] Select TW with SC2_MDE Select alternate open-drain output function with GP_PACFGL[7:4] SP slave data out of Serial Controller 2 Either disable timer output in TM2_CCER or enable remap SC2MS with TM2_R[6] Enable slave with SC2_SPCFG[4] Select SP with SC2_MDE Select alternate output function with GP_PACFGL[7:4] SP master data in of Serial Controller 2 Enable slave with SC2_SPCFG[4] Select SP with SC2_MDE PA2 / Digital / Timer 2 channel 4 output Disable remap with TM2_CH4 TM2_R[7] Enable timer output in TM2_CCER Select alternate output function with GP_PACFGL[11:8] Timer 2 channel 4 input. Disable remap with TM2_R[7] SC2SCL / TW clock of Serial Controller 2 Either disable timer output in TM2_CCER or enable remap with TM2_R[7] Select TW with SC2_MDE Select alternate open-drain output function with GP_PACFGL[11:8] SP master clock of Serial Controller 2 Either SC2SCLK disable timer output in TM2_CCER or enable remap with TM2_R[7] Enable master with SC2_SPCFG[4]

16 11 Module Pin No. QFN48 Pin No. Signal Direction Description Select SP with SC2_MDE Select alternate output function with GP_PACFGL[11:8] SP slave clock of Serial Controller 2 Enable slave with SC2_SPCFG[4] Select SP with SC2_MDE PA3 / Digital / SC2nSSEL SP slave select of Serial Controller 2 Enable slave with SC2_SPCFG[4] Select SP with SC2_MDE Synchronous CPU trace clock Either disable timer TRACECL K output in TM2_CCER or enable remap with TM2_R[5] Enable trace interface in ARM core Select alternate output function with GP_PACFGL[15:12] Timer 2 channel 2 output Disable remap with TM2_CH2 TM2_R[5] Enable timer output in TM2_CCER Select alternate output function with GP_PACFGL[15:12] Timer 2 channel 2 input. Disable remap with TM2_R[5]. PA4 / Digital / ADC4 Analog ADC nput 4. Select analog function with GP_PACFGH[3:0]. Frame signal of Packet Trace nterface (PT) PT_EN Disable trace interface in ARM core. Select alternate output function with GP_PACFGH[3:0]. Synchronous CPU trace data bit 2. Select 4-wire TRACEDA TA2 synchronous trace interface in ARM core. Enable trace interface in ARM core. Select alternate output function with GP_PACFGH[3:0]. PA5 / Digital / ADC5 Analog ADC nput 5. Select analog function with GP_PACFGH[7:4]. Data signal of Packet Trace nterface (PT) PT_DATA nbtm DE Disable trace interface in ARM core. Select alternate output function with GP_PACFGH[7:4]. Embedded serial bootloader activation out of reset. Signal is active during and immediately after a reset on NRST. Synchronous CPU trace data bit 3. Select 4-wire TRACEDA TA3 synchronous trace interface in ARM core. Enable trace interface in ARM core. Select alternate output function with GP_PACFGH[7:4]

17 12 Module Pin No. QFN48 Pin No Signal Direction Description PA6 / High current Digital / Timer 1 channel 3 output Enable timer output in TM1_CH3 TM1_CCER Select alternate output function with GP_PACFGH[11:8] Timer 1 channel 3 input (Cannot be remapped.) PC2 / Digital / Enable with GP_DBGCFG[5] JTD JTAG data out to debugger Selected when in JTAG mode (default mode, see JTMS description, Pin 35) Serial Wire utput asynchronous trace output to debugger Select asynchronous trace interface in ARM SW core Enable trace interface in ARM core Select alternate output function with GP_PCCFGL[11:8] Enable Serial Wire mode (see JTMS description, Pin 35) nternal pull-up is enabled PB1 / Digital / SP slave data out of Serial Controller 1 Either disable timer output in TM2_CCER or disable remap SC1MS with TM2_R[4] Select SP with SC1_MDE Select slave with SC1_SPCR Select alternate output function with GP_PBCFGL[7:4] SP master data out of Serial Controller 1 Either disable timer output in TM2_CCER or disable remap SC1MS with TM2_R[4] Select SP with SC1_MDE Select master with SC1_SPCR Select alternate output function with GP_PBCFGL[7:4] SC1SDA / TW data of Serial Controller 1 Either disable timer output in TM2_CCER, or disable remap with TM2_R[4] Select TW with SC1_MDE Select alternate open-drain output function with GP_PBCFGL[7:4] UART transmit data of Serial Controller 1 Either SC1TXD disable timer output in TM2_CCER or disable remap with TM2_R[4] Select UART with SC1_MDE Select alternate output function with GP_PBCFGL[7:4] Timer 2 channel 1 output Enable remap with TM2_CH1 TM2_R[4] Enable timer output in TM2_CCER Select alternate output function with GP_PACFGL[7:4] Timer 2 channel 1 input. Disable remap with TM2_R[4].

18 13 Module Pin No. QFN48 Pin No Signal Direction Description PB2 / Digital / SC1MS SP master data in of Serial Controller 1 Select SP with SC1_MDE Select master with SC1_SPCR SC1MS SP slave data in of Serial Controller 1 Select SP with SC1_MDE Select slave with SC1_SPCR TW clock of Serial Controller 1 Either disable timer output in TM2_CCER, or disable remap with SC1SCL / TM2_R[5] Select TW with SC1_MDE Select alternate open-drain output function with GP_PBCFGL[11:8] SC1RXD UART receive data of Serial Controller 1 Select UART with SC1_MDE Timer 2 channel 2 output Enable remap with TM2_R[5] Enable timer output in TM2_CCER Select TM2_CH2 alternate output function with GP_PBCFGL[11:8] Timer 2 channel 2 input. Enable remap with TM2_R[5]. Serial Wire clock input/output with debugger SWCLK / Selected when in Serial Wire mode (see JTMS description, Pin 35) JTAG clock input from debugger Selected when in JTCK JTAG mode (default mode, see JTMS description, Pin 35) nternal pull-down is enabled PC3 / Digital / Either Enable with GP_DBGCFG[5], or enable Serial Wire mode (see JTMS description) JTAG data in from debugger Selected when in JTD JTAG mode (default mode, see JTMS description, Pin 35) nternal pull-up is enabled PC4 / Digital / Enable with GP_DBGCFG[5] JTAG mode select from debugger Selected when in JTAG mode (default mode) JTAG mode is enabled JTMS after power-up or by forcing NRST low Select Serial Wire mode using the ARM-defined protocol through a debugger nternal pull-up is enabled Serial Wire bidirectional data to/from debugger SWD / Enable Serial Wire mode (see JTMS description) Select Serial Wire mode using the ARM-defined protocol through a debugger nternal pull-up is enabled PB0 / Digital /

19 14 Module QFN48 Pin No. Pin No Signal Direction Description VREF Analog ADC reference output. Enable analog function with GP_PBCFGL[3:0]. ADC reference input. Enable analog function with VREF Analog GP_PBCFGL[3:0]. Enable reference output with an ST system function. RQA External interrupt source A. TRACECL K Synchronous CPU trace clock. Enable trace interface in ARM core. Select alternate output function with GP_PBCFGL[3:0]. TM1CLK Timer 1 external clock input. TM2MSK Timer 2 external clock mask input. PC1 / Digital / ADC3 Analog ADC nput 3 Enable analog function with GP_PCCFGL[7:4] SW Serial Wire utput asynchronous trace output to debugger Select asynchronous trace interface in ARM core Enable trace interface in ARM core Select alternate output function with GP_PCCFGL[7:4] Synchronous CPU trace data bit 0 Select 1-, 2- or 4-wire TRACEDAT synchronous trace interface in ARM core Enable trace A0 interface in ARM core Select alternate output function with GP_PCCFGL[7:4] PC0 Digital / Either enable with GP_DBGCFG[5], or / High enable Serial Wire mode (see JTMS description, Pin 35) and current disable TRACEDATA1 JTAG reset input from debugger Selected when in JTAG JRST mode (default mode, see JTMS description) and TRACEDATA1 is disabled nternal pull-up is enabled RQD (1) Default external interrupt source D Synchronous CPU trace data bit 1 Select 2- or 4-wire TRACEDAT A1 synchronous trace interface in ARM core Enable trace interface in ARM core Select alternate output function with GP_PCCFGL[3:0] PB7 / High current Digital / ADC2 Analog ADC nput 2 Enable analog function with GP_PBCFGH[15:12] RQC (1) Default external interrupt source C

20 15 Module QFN48 Pin No. Pin No. Signal Direction Description Timer 1 channel 2 output Enable timer output in TM1_CH2 TM1_CCER Select alternate output function with GP_PBCFGH[15:12] Timer 1 channel 2 input (Cannot be remapped) PB6 / High current Digital / ADC1 Analog ADC nput 1 Enable analog function with GP_PBCFGH[11:8] RQB External interrupt source B Timer 1 channel 1 output Enable timer output in TM1_CH1 TM1_CCER Select alternate output function with GP_PBCFGH[11:8] Timer 1 channel 1 input (Cannot be remapped) PB5 / Digital / ADC nput 0 Enable analog function with ADC0 Analog GP_PBCFGH[7:4] TM2CLK Timer 2 external clock input TM1MSK Timer 2 external clock mask input 29 NC - No connect GND - Ground 3.4.

21 16 The return data includes basic configuration info of module: Pwr=+08:means TX is +8dBm; PMode=0000:means power mode is standard mode. : 1.

22 17 2. : AT+SETPWRMDE=0000

23 REX3S has 4 antennas, buyer need to confirm with sales about the type before purchasing. Figure Jumper indication

24 19 Use PCB antenna: Use other 3 exterior antenna:

25 PCB antenna Figure PCB antenna PCB antenna Attention when using PCB antenna: (1 cm at least, suggest more than 2.7 cm) 3.

26 21 User should try to avoid other components or line interfere PCB antenna when designing board: Wires or other components avoid surrounding PCB antenna PCB antenna should be extended to the board Don t use metal shell to cover the PCB antenna Figure Area supporting components Figure Steel antenna U.FL connects SMA antenna Figure U.FL connector

27 22 U.FL connector Remark: Figure antenna cable Figure SMA antenna Figure completing picture of SMA antenna

28 U.FL connects PCB antenna Figure connect PCB antenna Figure completing picture

29 When system voltage is 3.3V When system voltage is 5.0V

30 Figure JTAG SWD Figure SWD connection

31 26 Figure Relationship between JTAG and Zigbee module Pin N. 20-pin JTAG nterface Pin Number (Name) SWD connecting way and pin No. (Name) 1 2(VCC) 1(VCC) 1(VCC) 2(VCC) 3(nTRST) 4(GND) 5(JTD) (GND) 6(GND) 5(GND) 22(PC4) 7(JTMS) 7(SWD) 8(GND) 20(SWCLK) 9(JTCK) 6(SWCLK) 10(GND) 11(RTCK) 12(GND) 13(JTD) 14(GND) 7(nRESET) 15(RESET) 8(RESET) 16(GND) 17(DBGRQ) 18(GND) 19(DBGACK) 20(GND) 14(PA4) 9(PT_EN) 15(PA5) 10(PT_DATA).8. Figure RX sensitivity

32 27 Figure Figure 3-26.

33 28 4. Manufacturer REX=REXENSE REX 3 D 57 U Serial 3=Zigbee serial(cortex TM -M3 Core) Package type D=DP S=SMD U=Ultra compact L=LED lighting Chip No. 51=EM351 57=EM357(default) 64=STM32W108CBU64 Antenna U=U.FL connector(default) B=PCB antenna L=L antenna P=Pin out S=SMA antenna H=Spring antenna

34 5. 29

Content

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