CSC Trigger Motherboard
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1 CSC Trigger Motherboard Functions of TMB Tests: Performance at summer 2003 test beam Radiation, magnetic fields, etc. Plans for TMB production and testing 1
2 Cathode LCT CSC Trigger Requirements Identify cathode track segment. trigger based on angle of LCT For P t threshold of GeV requires p/p < 30% (in order to limit single muon trigger rate in Level-1 to a few KHz) Track hits must be located to within ½ strip width in each chamber layer Anode LCT Form anode track segment. Tag bunch crossing of track segment with > 92 % efficiency per chamber P t θ 2
3 CSC Muon Trigger Scheme EMU On CSC Chambers In Peripheral Crates Trigger In Counting House Cathode FE cards CFEB AFEB Anode FE cards Link Anode LCT card RPC Link Boards ALCT RAT RPC-Anode Transition board CLCT Coinc. TMB Trigger Motherboard Muon Port Card MPC 2µ / chamber OPTICAL Sector Receiver and Processor SR/SP 3µ / Port Card 3µ / sector CSC Muon Sorter RPC DT 4µ 4µ 4µ Global m Trigger 4µ Global L1 3
4 High I/O count Many signals multiplexed at 80 MHz Trigger Motherboard I/O 4
5 Trigger Motherboard Functions Each TMB serves one CSC 1 ALCT, 5 CFEB, 1 RPC Link board (ME1) Generates Cathode LCT trigger with input from CFEB (comparator) 96x5 = 480 strips ½-strip bits generated by comparator ASIC on CFEB Sends pre-trigger (fast) signals to DMB to initiate data storage Trigger matching: Matches ALCT and CLCT in time In ME1 can match RPC pads to ALCT/CLCT for ghost suppression Sends trigger primitives to MPC DAQ readout and diagnostics: Stores cathode raw hits x16 time bins upon CLCT * L1A Sends ALCT/CLCT results and all raw hits to DMB. 5
6 Fast control: More Trigger Motherboard Functions L1A and BX number synchronization Reset and initialize TMB and ALCT Slow control: VME path to TMB and ALCT Eprom and FPGA loading VME path to TMB and ALCT control registers Misc. 9U x 400mm VME slave +5v (~1A), +3.3V (~1A), 3.3v, 1.8v and 1.5v regulators Unique ID chips on base and mezzanine cards Voltage, current, and temperature monitoring 15 used for FAST site CSC testing 3 boards updated for 2003 test beam 6
7 TMB2001 Board Sections Power Conditioning VME Boot Section Mezzanine board with Main FPGA (on back) XILINX XCV1000E 5 Input connectors From CFEBs Configuration Eproms PHOS4 fine time delays (10 Channels) All I/O to FPGA buffered 2 Input connectors From ALCT GTLP Backplane Drivers Diffl.. LVDS for clock signals 7
8 TMB Firmware Features Adjustable trigger functions Hot channel masks Required number of layers Choice of CLCT, ALCT, coincidence, or external trigger Internal or external L1A Time matching windows for CLCT/ALCT coinc., L1A readout Fine time delay settings Other VME control registers (94 total) Board ID and firmware date registers Self-test pattern injector Internal logic scope readout by VME or through DAQ path VME interface to all ALCT control registers 8
9 2003 Beam Test Setup TTC crate Trigger primitives DAQ Data Track finder Crate TRIDAS Peripheral Crate 2 DMB, 2 TMB 1 CCB, 1 MPC FED crate 1 DDU PC beam S1 S2 S3 CSC 1 CSC 2 9
10 2003 Beam Test Setup m/ p From front end cards CCB + TTCRx 2 CSC s, all on-chamber boards Peripheral crate Track Finder CMS readout board Up to 80K events read out in 2.6s spill MPC 2 TMBs and DMBs 10
11 CSC Test Beam 2003 Trigger Results Implemented features: 2 full CSC sets of electronics Deadtime-less DAQ readout (8 buffers) implement Multiple CLCT patterns 16 time sample, logic analyzer DAQ readout Peripheral crate worked as designed Data analysis: ALCT bunch ID re-verified Very high efficiencies (>99%) found Chamber angle scans HV and threshold scans Pattern requirements scans (High-speed optical link trigger data transfer to Track Finder crate verified Paul s talk) 11
12 Typical Muon Event (CSC1 tilted) 12
13 CLCT Positions Relative position of key half strip from CLCTs from chamber 2 vs. Chamber 1 Note: Chamber 1 is vertically higher than Chamber 2 (thus the offset in position). Zoom 13
14 Cathode Trigger (CLCT) Patterns Simultaneous searches for distrip patterns (low-pt) and half-strip patterns (high-pt) Simulate low-pt by tilting the chamber (phi) 14
15 Quality = Layers-3 HQ bent 1/2-strip HQ straight 1/2-strip f=0 o f=5 o HQ bent 2-strip f=20 o 1/2-strip patterns 2-strip patterns 15
16 Note logarithmic scale BX Distributions With Optimal Anode Delays Cathodes: Data mostly in 3 bx (no fine timeadjustment possible) Anodes: Data 98.7% in 1 bx (after fine time-adjustment) Chamber 1 Chamber 2 16
17 Bunch Structure, ALCT Delay Tuning Expect muons in 48 out of 924 bx verified by CLCT bxn from data BX efficiency vs. ALCT delay setting 0-31 ns Chamber 1 Chamber 2 17
18 Correlated LCT Efficiency abs(strip3-strip8) abs(wg3-wg8) abs(strip3-strip8) abs(wg3-wg8) The efficiency to identify a correlated LCT (ALCT+CLCT) in one csc in a straight-line path from an LCT found in the other csc (within a ±5 strip and ±3 WG tolerance) is: 97.9% in one BX 98.9% in two BX (correct BX or one after) 99.1% in three BX (correct BX ±1) as determined from logged Track-Finder data 18
19 Correlated LCT Efficiency: timing Efficiency for the middle BX (BX#2) vs. ALCT delay time (for CSC#8) Efficiency for multi-bxs vs ALCT delay time (for CSC#8) efficiency efficiency BXs: 1,2, BX Window: Efficiency sensitive to ALCT delay (~5ns window) Multi-BX Window: Efficiency very close to 100% Less sensitive to exact ALCT timing No spatial requirement on shown efficiencies delay, ns Note the scale BXs: 2, delay, ns 19
20 Trigger Rate Tests 2,000 Chamber #1 CLCT 3,000 Chamber #1, #2 (ALCT1) OR (ALCT2) CLCT Rate (KHz) 1,500 1, Max. LHC data consistent with dead-time = 225 ns ALCT-OR Rate (KHz) 2,500 2,000 1,500 1, Max. LHC ,000 1,500 2,000 2,500 3, ,000 1,500 2,000 2,500 3,000 Beam Intensity (KHz) Beam Intensity (KHz) Expected LCT rate at LHC is 97 KHz/chamber (ME1/1) (CMS note ) 20
21 CSC Trigger Latency Budget is 80 bx to Global Muon Trigger (Sorter output) Measured with scope during the beam tests: From CSC to MPC input: From the CSC to SR/SP input: (includes 100 m fiber, 18 bx delay) Estimated latency for output of SP: Add 10 bx for SR/SP processing: 32 bx ( 1 bx) 68 bx Estimated latency for output of Muon Sorter: Add 7 bx for backplane + sorting: CMS corrections: 74 bx 57 bx Add 1 bx for time-of-flight in CMS perfect agreement with 75 bx estimated Dec 02 Will save additional ~7 bx with Virtex-2 TMB 68 bx (12 bx<budget) Estimated latency for CSC data at DT T-F: bx for SR + 2 bx for 5-10 m cable delay: 64 bx 7 bx = 56 bx 21
22 Pre-production Board TMB2003A 4 boards produced and bench-tested Replaces problematic PHOS4 fine delays with commercial DDD devices Faster and larger FPGA (Xilinx Virtex-2 XC2V3000) on mezzanine board ALCT and RPC inputs through RAT (Rpc Alct Transition) board Rad-hard regulators used, 1.5v added for RAT Spartan-3 FPGA 22
23 RAT2003A Detail To TMB and 3.3v, 1.8v power These Connectors for GND Only Spartan 2E FPGA for RPC RPC connectors ALCT SCSI input connectors 23
24 TMB2003A Radiation Test TMB2003A new components to test: - Virtex-II chip (XC2V3000) for SEUs - GTLP buffers for radiation damage TMB2003A other components: - Rad-hard regulators (OSU tests) - No other bi-polar devices SEU Test New state machine fires internal CLCT pattern injector Injects 1 muon: 6 hits, non-bending Trigger rate: 100KHz or ~10Hz Increments CFEB number each trigger Checks for correct CLCT data Checks for any CLCT data between triggers (spurious muon) Check power-monitor IC for +5V,+3.3V,+1.5V, +1.8V errors Flashes running LED at constant rate Test board: Connects to DMB TTL backplane drivers BiColor LEDs display test results Reset button forces FPGA reload (uses power-up IC on TMB) 24
25 Radiation Test Results (63.3 MeV Protons) Irradiated XC2V4000 Xilinx FPGA Found 1.2*10 9 cm -2 per SEU (141 Rad). Neutron fluence (M.Huhtinen) (1-4)*10 10 cm -2 for 10 LHC years Expect 8-33 SEUs per TMB in 10 LHC years. Eproms are not sensitive to SEU. Periodic reload from Eproms during CMS operation will keep fraction of SEU-affected boards very low (25x better than ALCTs). Also tested 6 GTLP chips up to 5 krads no problems. 25
26 TMB2003A Magnet Test 1 T rare-earth dipole magnet 3cm diameter used, scanned over all chips. Self-test runs at 100 khz no errors. Currents continuously monitored no change. Looked particularly at delay chips with oscilloscope no change. One non-stainless screw and one nut found (oops!) and replaced. 26
27 ALCT Production at UCLA Example % boards as for TMB 3 types (288-,, 384-,, 672-channel) All ALCT base boards done. Mezzanine cards need more spares. 27
28 Preparation for TMB Production ALCT production (similar boards), is ~95% done, we can now switch to TMB production. Production and assembly: Contracted to commercial firms Testing: Done in-house Test Burn-in Retest cycle useful for infant mortality as well as tester QC Burn-in 48 hours at 70 o C Self-test loopback boards and cables to test I/O were built and used for prototype checkout. Debugging firmware and software is already written. 28
29 Plans for TMB Production Pre-production: 18 TMB boards for 2-crate Slice Test in summer Bench tests and cosmic ray tests locally at UC FAST site. Full production: remainder of boards will be done during following year. RPC Link board to RAT communication for ME1: A data interchange test should be set up in spring. Cable routing between ME1 RPC and CSC crates needs to be worked out. N.B. >50% of RAT production can proceed without this for stations 2-4 where used only for ALCT. This talk and documentation at 29
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