9P960. Pin Configuration. Recommended Application. Features/Benefits. Block Diagram ICS9P SSOP DATASHEET

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1 DATASHEET DUAL CHANNEL DDRII/III ZER DELAY BUFFER 9P96 Recommended Application Dual DDR zero delay buffer Features/Benefits High performance, low jitter zero delay buffer I 2 C for functional and output control Dual bank 1-6 differential clock distribution 2 separate feedback in & out for input to output synchronization for each bank Supports up to 4 DDR DIMMs Supports up to DDRII - 166MHz Supports up to DDRIII (1.8V core) MHz utput-to-output skew: <1ps Block Diagram Pin Configuration DDRA T 1 DDRA C 2 DDRA T1 3 DDRA C1 4 DDRA T2 5 DDRA C2 6 GND 7 VDD1.8/1.5 8 AGND 9 AVDD1.8 1 SCLK 11 SDATA 12 VDD1.8/ DDRBT 14 DDRB C 15 DDRBT1 16 DDRB C1 17 DDRBT2 18 DDRB C2 19 CLK_INTB_T 2 CLK_INTB_C 21 GND 22 FB_INTB 23 FB_UTB 24 ICS9P96 48-SSP 48 FB_UTA 47 FB_INTA 46 VDD1.8/ CLK_INTA _T 44 CLK_INTA _C 43 GND 42 DDRAT3 41 DDRAC3 4 DDRAT4 39 DDRAC4 38 DDRAT5 37 DDRAC5 36 VDD1.8/ GND 34 AVDD AGND 32 GND 31 VDD1.8/1.5 3 DDRBT5 29 DDRBC5 28 DDRBT4 27 DDRBC4 26 DDRBT3 25 DDRBC3 IDT DUAL CHANNEL DDRII/III ZER DELAY BUFFER 1 9P96 REV A 51811

2 9P96 DUAL CHANNEL DDRII/III ZER DELAY BUFFER Pin Descriptions Pin# Pin Name Type Pin Description 1 DDRAT UT "True" Clock of differential pair output. 2 DDRAC UT "Complementary" Clock of differential pair output. 3 DDRAT1 UT "True" Clock of differential pair output. 4 DDRAC1 UT "Complementary" Clock of differential pair output. 5 DDRAT2 UT "True" Clock of differential pair output. 6 DDRAC2 UT "Complementary" Clock of differential pair output. 7 GND PWR Ground pin. 8 VDD1.8/1.5 PWR Power supply, nominal 1.8V or 1.5V 9 AGND PWR Analog Ground pin for Core PLL 1 AVDD1.8 PWR 1.8V Analog Power pin for Core PLL 11 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 12 SDATA I/ Data pin for SMBus circuitry, 5V tolerant. 13 VDD1.8/1.5 PWR Power supply, nominal 1.8V or 1.5V 14 DDRBT UT "True" Clock of differential pair output. 15 DDRBC UT "Complementary" Clock of differential pair output. 16 DDRBT1 UT "True" Clock of differential pair output. 17 DDRBC1 UT "Complementary" Clock of differential pair output. 18 DDRBT2 UT "True" Clock of differential pair output. 19 DDRBC2 UT "Complementary" Clock of differential pair output. 2 CLK_INTB_T IN True' reference clock input for bank B. 21 CLK_INTB_C IN Complementary' reference clock input for bank B. 22 GND PWR Ground pin. 23 FB_INTB IN True single-ended feedback input, provides feedback signal to internal PLL for synchronization with CLK INTB to eliminate phase error on bank B. 24 FB_UTB UT Feedback output, dedicated external feedback for bank B outputs. 25 DDRBC3 UT "Complementary" Clock of differential pair output. 26 DDRBT3 UT "True" Clock of differential pair output. 27 DDRBC4 UT "Complementary" Clock of differential pair output. 28 DDRBT4 UT "True" Clock of differential pair output. 29 DDRBC5 UT "Complementary" Clock of differential pair output. 3 DDRBT5 UT "True" Clock of differential pair output. 31 VDD1.8/1.5 PWR Power supply, nominal 1.8V or 1.5V 32 GND PWR Ground pin. 33 AGND PWR Analog Ground pin for Core PLL 34 AVDD1.8 PWR 1.8V Analog Power pin for Core PLL 35 GND PWR Ground pin. 36 VDD1.8/1.5 PWR Power supply, nominal 1.8V or 1.5V 37 DDRAC5 UT "Complementary" Clock of differential pair output. 38 DDRAT5 UT "True" Clock of differential pair output. 39 DDRAC4 UT "Complementary" Clock of differential pair output. 4 DDRAT4 UT "True" Clock of differential pair output. 41 DDRAC3 UT "Complementary" Clock of differential pair output. 42 DDRAT3 UT "True" Clock of differential pair output. 43 GND PWR Ground pin. 44 CLK_INTA_C IN Complementary' reference clock input for bank A. 45 CLK_INTA_T IN True' reference clock input for bank A. 46 VDD1.8/1.5 PWR Power supply, nominal 1.8V or 1.5V 47 FB_INTA IN True single-ended feedback input, provides feedback signal to internal PLL for synchronization with CLK INTA to elimate phase error on bank A. 48 FB_UTA UT Feedback output, dedicated external feedback for bank A outputs. IDT DUAL CHANNEL DDRII/III ZER DELAY BUFFER 2 9P96 REV A 51811

3 9P96 DUAL CHANNEL DDRII/III ZER DELAY BUFFER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9P96. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS 1.8/1.5V Core Voltage AVDD1.8 With respect to GND V 1.8/1.5V Logic Voltage VDD1.8/1.5 With respect to GND V Storage Temperature Ts C Ambient perating Temp Tambient - 7 C Tcase - 95 C Input ESD protection HBM ESD prot - 2 V 1. Guaranteed by design and characterization, not 1% tested in production. 2. peration under these conditions is neither implied nor guaranteed. DDRII Specifications Recommended perating Conditions T A = - 7 C; Supply Voltage AVDD1.8, VDD1.8/1.5 = 1.8 V +/-.1V (unless otherwise stated) PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS V DD1.8 / V Supply Voltage A VDD V Low level input voltage V IL CLK_INT, CLK_INC, FB_IN.35V DD V High level input voltage V IH CLK_INT, CLK_INC, FB_IN.65V DD V perating free-air temperature T A 7 C Notes: 1. Unused inputs must be held high or low to prevent them from floating. Electrical Characteristics Input/Supply/Common utput Parameters T A = - 7 C; Supply Voltage AVDD1.8, VDD1.8/1.5 = 1.8 V +/-.1V (unless otherwise stated) PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Input High Current I IH V I = V DD or GND 1 µa Input Low Current I IL V I = V DD or GND -1 µa utput Disabled Low Current I DL E = L, V DL = 1mV 1 µa I DDA 4MHz ma perating Supply Current I DD1.8 4MHz ma I DD LD C L = pf 5 µa Input Clamp Voltage V IK V DDQ = 1.8V Iin = -18mA -1.2 V High-level output voltage V H I H = -1µA V DD -.2 V I H = -9mA 1.1 V Low-level output voltage V L I L =1µA.1 V I L =9mA.6 V Input Capacitance C IN V I = GND or V DD pf utput Capacitance C U T V UT = GND or V DD pf IDT DUAL CHANNEL DDRII/III ZER DELAY BUFFER 3 9P96 REV A 51811

4 9P96 DUAL CHANNEL DDRII/III ZER DELAY BUFFER Timing T A = - 7 C; Supply Voltage AVDD1.8, VDD1.8/1.5 = 1.8 V +/-.1V (unless otherwise stated) PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Max clock frequency freq op 25 C 15 6 MHz Application Frequency Range freq App 25 C MHz Input clock duty cycle d tin 4 6 % CLK stabilization T STAB 15 µs Switching Characteristics 1 T A = - 7 C; Supply Voltage AVDD1.8, VDD1.8/1.5 = 1.8 V +/-.1V (unless otherwise stated) PARAMETER SYMBL CNDITIN MIN TYP MAX UNITS utput enable time t en E to any output 8 ns utput disable time t dis E to any output 8 ns Period jitter t jit (per) -3 3 ps Half-period jitter t jit(hpe r) -4 4 ps Input slew rate SLr1(i) Input Clock v/ns utput Enable (E), (S).5 v/ns utput clock slew rate SLr1(o) v/ns Cycle-to-cycle jitter t jit(cc+) 4 ps t jit(cc- ) -4 ps Dynamic Phase ffset t ( )dyn -2 2 ps Static Phase ffset t (spo) -6 6 ps utput to utput Skew t skew 1 ps SSC modulation frequency f SSCMD PLL will track SSC and khz SSC clock input frequency meet dynamic phase offset f SSC% deviation in the specified range % Notes: 1. Switching characteristics guaranteed for application frequency range. IDT DUAL CHANNEL DDRII/III ZER DELAY BUFFER 4 9P96 REV A 51811

5 9P96 DUAL CHANNEL DDRII/III ZER DELAY BUFFER DDRIII Specifications Recommended perating Conditions T A = - 7 C; Supply Voltage AVDD = 1.8V+/-.1V, VDD = 1.5 V +/- 5% (unless otherwise stated) PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS V DD 1.8/ V Supply Voltage A VDD V Low level input voltage V IL CLK_INT, CLK_INC, FB_IN.35V DD V High level input voltage V IH CLK_INT, CLK_INC, FB_IN.65V DD V perating free-air temperature T A 7 C Notes: 1. Unused inputs must be held high or low to prevent them from floating. Electrical Characteristics Input/Supply/Common utput Parameters T A = - 7 C; Supply Voltage AVDD = 1.8V+/-.1V, VDD = 1.5 V +/- 5% (unless otherwise stated) PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Input High Current I IH V I = V DD or GND 1 µa Input Low Current I IL V I = V DD or GND -1 µa utput Disabled Low Current I DL E = L, V D L = 1mV 1 µa I DD A 4MHz ma perating Supply Current I DD 1.5 4MHz ma I DDLD C L = pf 5 µa Input Clamp Current V IK V I < or V I > V DD -5 ma Differential output clock swing V D I H = -11mA 5 VDD1.8/1.5 mv Input Capacitance 1 C IN V I = GND or V DD 2 5 pf utput Capacitance 1 C UT V UT = GND or V DD 2 5 pf Timing T A = - 7 C; Supply Voltage AVDD = 1.8V+/-.1V, VDD = 1.5 V +/- 5% (unless otherwise stated) PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Max clock frequency freq op 25 C 3 7 MHz Application Frequency Range freq App 25 C 3 67 MHz Input clock duty cycle d tin 4 6 % CLK stabilization T STAB 15 µs IDT DUAL CHANNEL DDRII/III ZER DELAY BUFFER 5 9P96 REV A 51811

6 9P96 DUAL CHANNEL DDRII/III ZER DELAY BUFFER Switching Characteristics 1 T A = - 7 C; Supply Voltage AVDD = 1.8V+/-.1V, VDD = 1.5 V +/- 5% (unless otherwise stated) PARAMETER SYMBL CNDITIN MIN TYP MAX UNITS utput enable time t en E to any output 8 ns utput disable time t dis E to any output 8 ns Period jitter t jit (per) -3 3 ps Half-period jitter t jit(hper) -4 4 ps Input slew rate SLr1(i) Input Clock v/ns utput Enable (E), (S).5 v/ns utput clock slew rate SLr1(o) v/ns Cycle-to-cycle jitter t jit(cc+) 4 ps t jit(cc-) -4 ps Dynamic Phase ffset t ( )dyn -2 2 ps Static Phase ffset t (spo ) -6 6 ps utput to utput Skew t skew 1 ps SSC modulation frequency f SSCMD PLL will track SSC and khz SSC clock input frequency meet dynamic phase offset f SSC% deviation in the specified range % Notes: 1. Switching characteristics guaranteed for application frequency range. IDT DUAL CHANNEL DDRII/III ZER DELAY BUFFER 6 9P96 REV A 51811

7 9P96 DUAL CHANNEL DDRII/III ZER DELAY BUFFER General SMBus Serial Interface Information How to Write Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite Beginning Byte = N Data Byte Count = X Beginning Byte N Byte N + X - 1 P stop bit Read Address D5 (H) X Byte Write Address D4 (H) How to Read Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X-1 IDT clock sends Byte through Byte X (if X (H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite Beginning Byte = N RT Repeat start Slave Address RD ReaD N P Not acknowledge stop bit X Byte Data Byte Count=X Beginning Byte N Byte N + X - 1 IDT DUAL CHANNEL DDRII/III ZER DELAY BUFFER 7 9P96 REV A 51811

8 9P96 DUAL CHANNEL DDRII/III ZER DELAY BUFFER I2C Table: utput Control Register Byte 6 Name Control Function Type 1 Default Bit 7 Freq Detect A Low Frequency Detect PLLA FF Control RW FF N 1 Bit 6 FB_IN/UTA FB_UTA Control RW Disable Enable 1 Bit 5 DDRA_T5/C5 utput Control RW Disable Enable 1 Bit 4 DDRA_T4/C4 utput Control RW Disable Enable 1 Bit 3 DDRA_T3/C3 utput Control RW Disable Enable 1 Bit 2 DDRA_T2/C2 utput Control RW Disable Enable 1 Bit 1 DDRA_T1/C1 utput Control RW Disable Enable 1 Bit DDRA_T/C utput Control RW Disable Enable 1 I2C Table: utput Control Register Byte 7 Name Control Function Type 1 Default Bit 7 Freq Detect B Low Frequency Detect PLLB FF Control RW FF N 1 Bit 6 FB_IN/UTB FB_UTB Control RW Disable Enable 1 Bit 5 DDRB_T5/C5 utput Control RW Disable Enable 1 Bit 4 DDRB_T4/C4 utput Control RW Disable Enable 1 Bit 3 DDRB_T3/C3 utput Control RW Disable Enable 1 Bit 2 DDRB_T2/C2 utput Control RW Disable Enable 1 Bit 1 DDRB_T1/C1 utput Control RW Disable Enable 1 Bit DDRB_T/C utput Control RW Disable Enable 1 I2C Table: Group Skew Control Register Byte 8 Name Control Function Type 1 Default Bit 7 CLKINA Skw3 RW Bit 6 CLKINA Skw2 RW See Table 1: 7-Step Skew CLKINA Skew Control Bit 5 CLKINA Skw1 RW Programming Table Bit 4 CLKINA Skw RW Bit 3 FB_INTA Skw3 RW Bit 2 FB_INTA Skw2 RW See Table 1: 7-Step Skew FB_INTA Skew Control Bit 1 FB_INTA Skw1 RW Programming Table Bit FB_INTA Skw RW I2C Table: Group Skew Control Register Byte 9 Name Control Function Type 1 Default Bit 7 CLKINB Skw3 RW Bit 6 CLKINB Skw2 RW See Table 1: 7-Step Skew CLKINB Skew Control Bit 5 CLKINB Skw1 RW Programming Table Bit 4 CLKINB Skw RW Bit 3 FB_INTB Skw3 RW Bit 2 FB_INTB Skw2 RW See Table 1: 7-Step Skew FB_INTB Skew Control Bit 1 FB_INTB Skw1 RW Programming Table Bit FB_INTB Skw RW IDT DUAL CHANNEL DDRII/III ZER DELAY BUFFER 8 9P96 REV A 51811

9 9P96 DUAL CHANNEL DDRII/III ZER DELAY BUFFER I2C Table: Revision ID and Vendor ID Register Byte 1 Name Control Function Type 1 Default Bit 7 Revision_ID bit 3 RW - - Bit 6 Revision_ID bit 2 RW - - Rev ID Bit 5 Revision_ID bit 1 RW - - Bit 4 Revision_ID bit RW - - Bit 3 Vendor_ID bit3 RW - - Bit 2 Vendor_ID bit2 RW - - Vendor ID Bit 1 Vendor_ID bit1 RW - - Bit Vendor_ID bit RW I2C Table: Byte Count Register Byte 15 Name Control Function Type 1 Default Bit 7 BC7 RW Bit 6 BC6 RW Bit 5 BC5 RW Writing to this register will Bit 4 BC4 Byte Count Programming RW configure how many bytes will be Bit 3 BC3 b(7:) RW read back, default is F = 15 1 Bit 2 BC2 RW bytes 1 Bit 1 BC1 RW 1 Bit BC RW 1 Table 1: 7-Steps Skew Programming Table 7 Step LSB 11 9 ps 75 ps 6 ps 45 ps 1 N/A N/A N/A 3 ps 1 N/A N/A N/A 15 ps N/A N/A N/A. ps MSB IDT DUAL CHANNEL DDRII/III ZER DELAY BUFFER 9 9P96 REV A 51811

10 9P96 DUAL CHANNEL DDRII/III ZER DELAY BUFFER Package utline and Package Dimensions (48-pin SSP, 3 Mil. Body) Package dimensions are kept current with JEDEC Publication No Millimeters Inches* INDEX AREA A2 1 2 D E1 A E Symbol Min Max Min Max A A b c D E E e.635 BASIC.25 BASIC h L α 8 8 *For reference only. Controlling dimensions in mm. A1 - C - c e b SEATING PLANE aaa C L rdering Information Part / rder Number Shipping Packaging Package Temperature 9P96AFLF Tubes 48-pin SSP to +7 C 9P96AFLFT Tape and Reel 48-pin SSP to +7 C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. A is the device revision designator (will not correlate with the datasheet revision). While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT DUAL CHANNEL DDRII/III ZER DELAY BUFFER 1 9P96 REV A 51811

11 9P96 DUAL CHANNEL DDRII/III ZER DELAY BUFFER Revision History Rev. Issue Date Description Page #.1 5/17/27 Initial Release -.2 7/1/27 Updated Product description and Pinout Various.3 9/9/28 Updated Max Frequency for DDR2 (1.8V) setting 8.4 1/19/29 Updated pin description table 2 A 5/18/ Removed advance information water marks from electrical tables. 2. Udpated ordering information 3. Updated electrical tables 4. Updated SMBus tables 5. Updated to current datasheet template Various IDT DUAL CHANNEL DDRII/III ZER DELAY BUFFER 11 9P96 REV A 51811

12 9P96 DUAL CHANNEL DDRII/III ZER DELAY BUFFER SYNTHESIZERS Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support Corporate Headquarters Integrated Device Technology, Inc Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA