Virtual Memory. CS 351: Systems Programming Michael Saelee
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1 Virtual Memory CS 351: Systems Programming Michael Saelee
2 registers cache (SRAM) main memory (DRAM) local hard disk drive (HDD/SSD) remote storage (networked drive / cloud) previously: SRAM DRAM
3 registers cache (SRAM) main memory (DRAM) local hard disk drive (HDD/SSD) remote storage (networked drive / cloud) next: DRAM HDD, SSD, etc. i.e., memory as a cache for disk
4 main goals: 1. maximize memory throughput 2. maximize memory utilization 3. provide address space consistency & memory protection to processes
5 throughput = # bytes per second - depends on access latencies (DRAM, HDD) and hit rate
6 utilization = fraction of allocated memory that contains user data (aka payload) - vs. metadata and other overhead required for memory management
7 address space consistency provide a uniform view of memory to each process
8 memory protection prevent processes from directly accessing each other s memory
9 memory addresses : what are they, really?
10 Main Memory CPU (note: cache not shown) N address: N data physical address: (byte) index into DRAM
11 int glob = 0xDEADBEEE; main() { fork(); glob += 1; } (gdb) set detach-on-fork off (gdb) break main Breakpoint 1 at 0x400508: file memtest.c, line 7. (gdb) run Breakpoint 1, main () at memtest.c:7 7 fork(); (gdb) next [New process 7450] 8 glob += 1; (gdb) print &glob $1 = (int *) 0x6008d4 (gdb) next 9 } (gdb) print /x glob $2 = 0xdeadbeef (gdb) inferior 2 [Switching to inferior 2 [process 7450] #0 0x acac49d in libc_fork () 131 pid = ARCH_FORK (); (gdb) finish Run till exit from #0 in libc_fork () 8 glob += 1; (gdb) print /x glob $4 = 0xdeadbeee (gdb) print &glob $5 = (int *) 0x6008d4 parent child
12 Main Memory N CPU address: N data instructions executed by the CPU do not refer directly to physical addresses!
13 processes reference virtual addresses, the CPU relays virtual address requests to the memory management unit (MMU), which are translated to physical addresses
14 Main Memory MMU physical address CPU virtual address address translation unit disk address (note: cache not shown) swap space
15 essential problem: translate request for a virtual address physical address this must be FAST, as every memory access from the CPU must be translated
16 both hardware/software are involved: - MMU (hw) handles simple and fast operations (e.g., table lookups) - Kernel (sw) handles complex tasks (e.g., eviction policy)
17 Virtual Memory Implementations
18 keep in mind goals: 1. maximize memory throughput 2. maximize memory utilization 3. provide address space consistency & memory protection to processes
19 1. simple relocation Main Memory CPU MMU relocation reg. N B VA: N B PA: N+B data - per-process relocation address is loaded by kernel on every context switch
20 1. simple relocation Main Memory CPU MMU limit reg. L relocation reg. N B+L B process sandbox VA: N B PA: N+B assert (0 N L) data - incorporate a limit register to provide memory protection
21 pros: - simple & fast! - provides protection
22 stack Virtual Memory Main Memory heap Main Memory stack stack data data heap heap vs. code code B data data code code B but: available memory for mapping depends on value of base address i.e., address spaces are not consistent!
23 virtual address space Main Memory L stack stack possibly unused! 0 code code B also: all of a process below the address limit must be loaded in memory i.e., memory may be vastly under-utilized
24 2. segmentation - partition virtual address space into multiple logical segments - individually map them onto physical memory with relocation registers
25 Segmented Virtual Address Space Main Memory B2+L2 0 Seg #3: Stack MMU Segment Table B2 Base Limit 0 B0 L0 1 B1 L1 B3+L3 0 Seg #2: Heap 2 B2 L2 3 B3 L3 B3 B0+L0 0 Seg #1: Data B0 0 Seg #0: Code B1+L1 B1 virtual address has form seg#:offset
26 MMU Segment Table Base Limit 0 B0 L0 1 B1 L1 2 B2 L2 3 B3 L3 Main Memory B2+L2 B2 B3+L3 CPU VA: seg#:offset PA: offset + B2 B3 B0+L0 B0 assert (offset L2) B1+L1 B1 data
27 Segment Table Base Limit 0 B0 L0 1 B1 L1 2 B2 L2 3 B3 L3 - implemented as MMU registers - part of kernel-maintained, per-process metadata (aka process control block ) - re-populated on each context switch
28 pros: - still very fast - translation = register access & addition - memory protection via limits - segmented addresses improve consistency
29 virtual address space Main Memory simple relocation: L stack stack possibly unused! 0 code code B virtual address space Main Memory segmentation: 0 stack stack better! 0 code code
30 virtual address space Main Memory x virtual address space 2 stack 0 stack x stack 0 code code 0 0 code x - variable segment sizes memory fragmentation - fragmentation potentially lowers utilization - can fix through compaction, but expensive!
31 3. paging - partition virtual and physical address spaces into uniformly sized pages - only map pages onto physical memory that contain required data
32 stack physical memory heap data code - pages boundaries are not aligned to segments! - simply aligned to multiples of page size
33 stack physical memory heap data code - minimum mapping granularity = page - not all of a given segment need be mapped
34 new mapping problem: - break a virtual address down into virtual page number & virtual page offset - map VPN physical page number
35 Given page size = 2 p bytes VA: PA: virtual page number physical page number p virtual page offset p physical page offset
36 VA: virtual page number virtual page offset address translation PA: physical page number physical page offset
37 VA: n virtual page number virtual page offset translation structure: page table valid PPN index 2 n entries if invalid, page is not mapped PA: physical page number physical page offset
38 page table entries (PTEs) typically contain additional metadata, e.g.: - dirty (modified) bit - access bits (shared or kernel-owned pages may be read-only or inaccessible)
39 e.g., 32-bit virtual address, 4KB (2 12 ) pages, 4-byte PTEs; - size of page table?
40 e.g., 32-bit virtual address, 4KB (2 12 ) pages, 4-byte PTEs; - # pages = 2 (32-12) = 2 20 =1M - page table size = 1M 4 bytes = 4MB
41 4MB is much too large to fit in the MMU insufficient registers and SRAM! Page table resides in main memory
42 The translation process (aka page table walk) is performed by hardware (MMU). The kernel must initially populate, then continue to manage a process s page table The kernel also populates a page table base register on context switches
43 translation: hit CPU ➊ VA: N Address Translator (part of MMU) ➋ page table walk Main Memory Page Table ➌ PA: N' ➍ data
44 translation: miss ➍ transfer control to kernel CPU ➊ VA: N ➐ VA: N (retry) ➌ page fault Address Translator (part of MMU) ➋ page table ➑ walk ➒ PA: N' Main Memory Page Table ➏ PTE update kernel Disk (swap space) ➎ data transfer ➓ data
45 kernel decides where to place page, and what to evict (if memory is full) - e.g., using LRU replacement policy
46 this system enables on-demand paging i.e., an active process need only be partly in memory (load rest from disk dynamically)
47 but if working set (of active processes) exceeds available memory, we may have swap thrashing
48 integration with caches?
49 Q: do caches use physical or virtual addresses for lookups?
50 Virtual address based Cache Process A Virtual Address Space CPU Process B Virtual Address Space Cache Address L M N Data X Y Z Z N M?? ambiguous! M L X 0 0
51 Physical address based Cache Process A Virtual Address Space CPU Process B Virtual Address Space Cache Address S Q R Data X Y Z Z N M Physical Memory X S Y M L 0 X Z Y R Q 0
52 Q: do caches use physical or virtual addresses for lookups? A: caches typically use physical addresses
53 Main Memory page table walk process page table CPU VA MMU (address translation unit) PA Cache (miss) data (hit) (update)
54 saved by hardware: the Translation Lookaside Buffer (TLB) a cache used solely for VPN PPN lookups
55 only if TLB miss! MMU address translation unit page table walk Main Memory process page table CPU TLB Cache (VPN PPN cache) VA PA (miss) data (hit) (update) TLB + Page table (exercise for reader: revise earlier translation diagrams!)
56 virtual address n-1 p p-1 0 virtual page number (VPN) page offset valid tag physical page number (PPN) TLB = TLB Hit physical address valid tag data byte offset Cache Cache Hit = Data
57 TLB mappings are process specific requires flush & reload on context switch - some architectures store PID (aka virtual space ID) in TLB
58 Familiar caching problem: - TLB caches a few thousand mappings - vs. millions of virtual pages per process!
59 we can improve TLB hit rate by reducing the number of pages by increasing the size of each page
60 compute # pages for 32-bit memory for: - 1KB, 512KB, 4MB pages = 2 22 = 4M pages = 2 13 = 8K pages = 2 10 = 1K pages (not bad!)
61 Process A Virtual Memory lots of wasted space! Process B Virtual Memory Physical Memory
62 Process A Virtual Memory Process B Virtual Memory Physical Memory
63 increasing page size results in increased internal fragmentation and lower utilization
64 i.e., TLB effectiveness needs to be balanced against memory utilization
65 so what about 64-bit systems? 2 64 = 16 Exabyte address space 4 billion x 4GB
66 most modern implementations support a max of 2 48 (256TB) addressable space
67 page table size? - # pages = = PTE size = 8 bytes (64 bits) - PT size = 2 36 x 8 = 2 39 bytes = 512GB
68 512GB (just for the virtual memory mapping structure) (and we need one per process)
69 (these things aren t going to fit in memory)
70 instead, use multi-level page tables: - split an address translation into two (or more) separate table lookups - unused parts of the table don t need to be in memory!
71 toy memory system - 8 bit addresses - 32-byte pages VPN page offset Page Table (unmapped) PPN (unmapped) PPN (unmapped) (unmapped) (unmapped) (unmapped) all 8 PTEs must be in memory at all times
72 toy memory system - 8 bit addresses - 32-byte pages page offset page directory 1 0 all unmapped; don t need in memory! (unmapped) PPN (unmapped) PPN (unmapped) (unmapped) (unmapped) (unmapped)
73 toy memory system - 8 bit addresses - 32-byte pages page offset (unmapped) PPN (unmapped) PPN
74 Intel Architecture Memory Management (Software Developer s Manual Volume 3A)
75 Logical Address (or Far Pointer) Segment Selector Offset Linear Address Space Global Descriptor Table (GDT) Linear Address Dir Table Offset Physical Address Space Segment Descriptor Segment Lin. Addr. Page Directory Page Table Entry Page Phy. Addr. Entry Segment Base Address Page Segmentation Paging
76 Segment Registers CS Segment Descriptors Access Limit Base Address Linear Address Space (or Physical Memory) Stack SS Access Limit Base Address DS Access Limit Base Address Code ES FS GS Access Limit Base Address Access Limit Base Address Access Limit Base Address Access Limit Base Address Data Data Data Access Limit Base Address Access Limit Base Address Data Access Limit Base Address Segment descriptors
77 Segment Registers CS SS Code- and Data-Segment Descriptors Linear Address Space (or Physical Memory) Code Not Present FFFFFFFFH DS ES Access Limit Base Address Data and Stack 0 FS GS Flat model
78 Paging Mode CR0.PG CR4.PAE LME in IA32_EFER Linear- Address Width Physical- Address Width 1 Page Size(s) Supports Execute- Disable? None 0 N/A N/A N/A No 32-bit Up to KByte 4-MByte 4 No PAE Up to 52 4-KByte 2-MByte Yes 5 IA-32e Up to 52 4-KByte 2-MByte 1-GByte 6 Yes 5 NOTES: Paging modes
79 Linear Address Directory Table Offset KByte Page 10 Page Directory 10 Page Table Physical Address PDE with PS=0 20 PTE CR3 IA-32 paging (4KB pages)
80 Linear Address Directory Offset 22 4-MByte Page 10 Page Directory Physical Address PDE with PS= CR3 IA-32 paging (4MB pages)
81 Address of page directory 1 Ignored P C D P W T Ignored CR3 Bits 31:22 of address of 2MB page frame Reserved (must be 0) Bits 39:32 of address 2 P A T Ignored G 1 D A P C D P W T U / S R / W 1 PDE: 4MB page Address of page table Ignored 0 I P g n A C D P U W / T S R / W 1 PDE: page table Ignored 0 PDE: not present Address of 4KB page frame Ignored G P A T D A P C D P W T U / S R / W 1 PTE: 4KB page Ignored 0 PTE: not present Figure 4-4. Formats of CR3 and Paging-Structure Entries with 32-Bit Paging PTE formats
82 47 PML4 Linear Address Directory Ptr Directory Table Offset KByte Page Physical Addr Page-Directory- Pointer Table PDPTE PDE with PS=0 40 Page-Directory 40 PTE Page Table 40 9 PML4E CR3 IA-32e paging (4KB pages)
83 47 PML Directory Ptr Linear Address Offset Page-Directory- Pointer Table 1-GByte Page Physical Addr 9 PDPTE with PS=1 22 PML4E CR3 IA-32e paging (1GB pages)
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