Optical SerDes Test Interface for High-Speed and Parallel Testing

Transcription

1 June 7-10, 2009 San Diego, CA SerDes Test Interface for High-Speed and Parallel Testing Sanghoon Lee, Ph. D Sejang Oh, Kyeongseon Shin, Wuisoo Lee Memory Division, SAMSUNG ELECTRONICS

2 Why Interface? High speed up to 10GHz, Significant scalability Smaller cross-sectional area than electrical cable or trace. [T. Okayasu, et al., JLT, vol. 22, no. 9, Sept. 2004] Immune to electromagnetic interference Impedance matching not needed Electrical Path Electrical signal Electrical stub Reflection 1 2 Path signal coupler Opt. RX Opt. RX 1 2 IEEE SW Test Workshop 2/22

3 Contents 1. Introduction 2. Three optical Issue in Test Interface 3. Proposed SerDes Test System 4. 3D Electromagnetic Board Simulation 5. Measurement and Analysis 6. Summary IEEE SW Test Workshop 3/22

4 Introduction Basic concept Interface is applied onto PCB of Probe Card For what? More high-speed Test Scalability for expansion of s resource Good PCB noise immunity Test Interface Main Frame PCB Probe Card (Wafer) Needle IEEE SW Test Workshop 4/22

5 Issue in Test Interface (1) Many of optical modules required ( TX/RX + Fiber) Total of about 80 optical modules including transmitter and receiver when evaluate a single memory chip with only write operation. Solution: SerDes (Serialization/De-serialization) technique which combines 8 electrical channels into 1 channel CLK RAS CAS A0 A1 DQ0 DQ1 SerDes Parallel to Serial TX RX SerDes TX RX 4 4 Serial fiber to Parallel CLK RAS CAS A0 A1 DQ0 DQ1 IEEE SW Test Workshop 5/22

6 Issue in Test Interface (2) Interface mismatching Different interface standards between / and TX/RX Signal Reflection and degradation Solution: Signal level conversion using FPGA logic for the same interface standards FPGA Reflection TX RX FPGA Reflection SSTL SSTL CML CML CML CML SSTL SSTL SSTL: Stub No Series Reflection Terminated Logic (+ 0.8 V ~ No V) Reflection CML : Current Mode Logic (+ 0.6 V ~ 0.6 V) IEEE SW Test Workshop 6/22

7 Issue in Test Interface (3) Signal skew in multi-channel interconnects Impossible to calibrate skews because the optical modules inserted into the electrical path. Solution: Simple skew adjustment technique in optical & electrical channel by using FPGA delay FPGA TX RX FPGA Delay Control Channel Channel Skew-free Electrical Channel Skew-free Skew Skew Delay Control IEEE SW Test Workshop 7/22

8 Proposed SerDes Interface Probe Card PCB Link FPGA _ FPGA _ Splitter De- De- SSTL18 CML CML SSTL18 [8 bit Serialization ] [8 bit De-serialization ] SerDes IEEE SW Test Workshop 8/22

9 Details [FPGA_ ] -DELAY FPGA Fabric SERDES 1 1 DQ 0_W DQ 1_W DQ 2_W DQ 3_W DQ_R DQ 0 DQ 1 DQ 2 DQ 3 IOB IOB IOB IOB DQ 0_W DQ 1_W DQ 2_W DQ 3_W DQ_R Delay Delay Chain Chain Delay Delay Chain Chain DQ_R (IDDR) (IDDR) (FIFO) (FIFO) (ODDR) (ODDR) (IDDR) (IDDR) (FIFO) (FIFO) (ODDR) (ODDR) DQ_R -DELAY FPGA Fabric DQ 0_R DQ 0_R DQ_R DQ 1_R DQ 1_R DQ 2_R DQ 3_R DQ 0_W DQ 1_W DQ 2_W DQ 3_W DQ 0_W DQ 1_W DQ 2_W DQ 3_W DQ 2_R DQ 3_R DQ 0_W DQ 1_W DQ 2_W DQ 3_W DQ 0_W DQ 1_W DQ 2_W DQ 3_W DQ 0_W DQ 1_W DQ 2_W DQ 3_W OUTPUT DQ_W OUTPUT SERDES SERDES DQ_R INPUT INPUT SERDES SERDES SERDES DQ_R OUTPUT OUTPUT SERDES SERDES DQ_W INPUT INPUT SERDES SERDES TX TX RX RX TX TX RX RX Fiber 1 4 Splitter [FPGA_ ] IEEE SW Test Workshop 9/22

10 3D Electromagnetic Board Simulation IEEE SW Test Workshop 10/22

11 Serialized 2.5 Gbps Performance FPGA Input Signal (2.5 Gbps) Differential Line Back-drilling at all DQ via channel 95 % PCB fiber 0 m1 RX FPGA DDR2 db(s(1,2)) db(s(1,1)) m1 freq= 1.250GHz db(s(1,2))= freq, GHz Voltage of 7 % decreases IEEE SW Test Workshop 11/22

12 Write Signal 125 MHz Performance DDR2 Input Signal (125 MHz) Single ended 98 % PCB fiber RX FPGA DDR m1 db(s(1,2)) db(s(1,1)) freq, GHz m1 freq= 125.0MHz db(s(1,2))= Voltage of 2 % decreases IEEE SW Test Workshop 12/22

13 Measurement and Analysis IEEE SW Test Workshop 13/22

14 ZIF Connector Structure & Operation Probe Card Main PCB FPGA TX Fiber Splitter RX FPGA DRAM Package Read Path Multi-Channel Module (Transmitter) Multi-Channel Module (Receiver) 1 4 Splitter Write Path DDR2 Package Write/Read Operation FPGA IEEE SW Test Workshop 14/22

15 Experimental Setup Items TX/RX Module Resource Expansion Transmission Test Condition Specification DDR2-533 (60 BOC)_4ea 5 ea (12 optical channel / Module) Bandwidth: 2.7 Gbps 4 Expansion using Splitter SerDes (2.5 Gbps) X-March Pattern trcd = 4 CL = 4 Speed = 125 MHz (8 ns) Background Write/Read IEEE SW Test Workshop 15/22

16 Output Write Signal (125 MHz) _FPGA _FPGA Link De- De- IEEE SW Test Workshop 16/22

17 Input Signal into FPGA _ (125 MHz) _FPGA _FPGA Link De- De- Active Write Write Out Active Write Write Out Precharge Precharge - The same logic compared with function logic IEEE SW Test Workshop 17/22

18 Received Serialized Signal (2.5 Gbps) _FPGA _FPGA Link De- De- Using Oscilloscope 2.5 Gbps Amplitude = 270 mv Jitter = 54 ps tr/tf = 180 ps/164 ps IEEE SW Test Workshop 18/22

19 Input Signal at FPGA _ (125 MHz) _FPGA _FPGA Link De- De- [ Skew Control using FPGA IO-delay ] CLK vs. CAS CLK = 2 ns Delay CLK vs. CAS (skew-free) DQS vs. DQ_7 DQS = 2 ns Delay DQS vs. DQ_7 (skew-free) IEEE SW Test Workshop 19/22

20 Read Signal into Comparator _FPGA _FPGA Link De- De- All good read signal with synchronous operation in front of. IEEE SW Test Workshop 20/22

21 Hardware Performance Type Performance Conventional System SerDes System Advantage # of fiber for 1 40 ch 5 ch 1/8 reduction # of Module (TX and RX) 80 ea (only write-mode) 2 ea (Parallel modules used) 1/40 reduction channel expansion Not expanded by Splitter 4 times expansion IEEE SW Test Workshop 21/22

22 Summary signal 4 times splitting scheme and SerDes techniques for a multi-parallel high speed memory test An actual write/read optical memory test operation fiber channels of 87 % and module of 95 % are reduced dramatically, compared to a conventional optical interface Further, this scheme, with proper modifications and optimizations in terms of size and power, might be applied for CPU-memory optical interconnects in the future computing environment. IEEE SW Test Workshop 22/22