Babbage Analytical Machine

Transcription

1 Von Neumann Machine

2 Babbage Analytical Machine The basis of modern computers is proposed by a professor of mathematics at Cambridge University named Charles Babbage ( ). He has invented a mechanical machine known as differential machine. This mechanical device can only add and subtract, designed to calculate the number of charts that are useful in piloting. This engine is the first ever computer that has four components: Store (memory) Contains 1000 words of 50 decimal digits which is used to hold variables and results Memory unit Receive operand from store, add, subtract, multiply or divide and will return the result to store Input punch cards Output output punch cards

3 Konrad Zuse German Engineering Student Create an automatic calculation machine which uses electromagnetic currents

4 John Atanasoff From College of Iowa States Create Atanasoff Machine Use binary arithmetic and capacitors to store memory But.. This machine is not working because of technology constraints

5 Howard Aiken Create computer for general use The extended of Babbage Machine Mark 1 Completed in Havard (1944) Use 72 words Input/Output punched on tape

6 ENIAC ENIAC is stand for Electronic Numerical Integrated And Computer The first ever electronic computer Used to understand the secret codes used by the German army but it was never completed Organization vacuum tube 1500 relay Weight 30 tan Power 140 KW 20 register each one capable of handling up to 10 digits decimal number 6000 multi position switch Many cables and sockets

7 Eckert & Arithmetic ENIAC

8 Motivation from ENIAC EDSAC The first electronic computer operating properly (1945) Build at University of Cambridge, UK by Maurice Wilkes JOHNIAC Rand Company ILLIAC University of Illinois MANIAC Built at Alanos Lab WEIZAC Built at Institute of Weizmann, Israel EDVAC unsuccessful

9 Von Neumann Machine John Von Neumann research of ENIAC machine ENIAC Built IAS another version of EDVAC Improvement made: Use the binary number system in parallel. Use the concept of stored programs Von Neumann bottleneck referred to: The separation between CPU and memory The limited throughput between CPU and memory compared to the amount of memory. In modern computers, throughput is much smaller that the rate at which CPU can work. This seriously limits the effective processing speed when CPU is required to perform minimal processing on large amount of data. The CPU is forced to wait for needed data to be transferred to or from memory. The bottleneck has become more of a problem whose severity increases with every newer generation of CPU.

10 Von Neumann Machine 5 important parts Memory Control Unit Arithmetic and Logic Unit Input Output

11 Bus System Direct connection of each component in a computer Began to be used on the PDP-8 machine Consist of parallel wires are covered with copper

12 Bus System Type of buses: System Bus Connect all the chips that form a computer system Local bus Special bus that connecting 2 components directly Example: connection between the microprocessor and co-processor Internal Bus Connecting components in one chip

13 Bus System System bus Register Internal Bus ALU Memory I/O Coprocessor Local bus

14 Bus Structure Although there are many different bus designs, on any bus the lines can be classified into three functional groups: data, address and control lines. Data lines: Provide a path for moving data among system modules. These lines, collectively are call data bus. The data bus may consist of , 128 or even more separate lines. The number of lines referred to as the width of the data bus.

15 Bus Structure Address Line: Used to designate the source or destination of the data on the data bus. Example: if the processor wishes to read a word of data from memory, it put the address of the desired word on the address lines. Clearly, the width of the address bus determines the maximum possible memory capacity of the system. Furthermore, the address lines are generally also used to address I/O ports.

16 Bus structure Control line: Used to control the access to and the used of the data and address line. Because the data and address line are shared by all components, there must be a means of controlling their use. Control signal transmit both command and timing information among system modules. Typical control line include: memory write, memory read, I/O write, I/O read, Transfer ACK, Bus request, bus grant, clock, reset, etc

17 Bus System Omnibus Connect all components use only one bus CPU Ingatan Konsol I/O

18 Bus Operation Master the device that gives instructions Slave the device that receive instructions Example: CPU directs disk controller to read data Master CPU Slave disk controller Disk controller directs the memory to receive a word from disk drive Master disk controller Slave memory

19 Bus Operations Bus Driver Used to strengthen the signal to be sent Bus Receiver Used to strengthen the received signal Transceiver Chip consisting bus driver and bus receiver

20 Bus System 3 important types of bus Data Bus Transfer data from one place to another Addressing Bus State memory address such as memory address, address of I/O peripherals Control Bus Carrying control signals such as signal for read or write

21 Bus System CPU MEMORY I/O Control Bus Address Bus Bus System Data Bus

22 Bus Synchronization Bus Synchronization: Bus driven by a crystal oscillator The crystal oscillator will produce a signal wave 5 to 50 MHz

23 Bus Arbitration Mechanism for determining which device to use the bus at the time 2 mechanism: Centralized requires hardware that will grant the bus to one of the requesting devices. This hardware can be part of the CPU or it can be a separate device on the motherboard. Distributed there isn t an arbiter, so the devices have to decide who goes next. This makes the devices more complicated, but saves the expense of having an arbiter. Arbitration: Device arbitration mechanism In CPU Chip Also in separated chip

24 Operation of Bus Arbitration The arbitration received a bus request Take over the bus and end the recognition yes Arbitration was a recognition in the bus line recognition Nearest device will check whether there is a bus request Send acknowledgment to the device next to his no

25 Operation of Bus Arbitration Arbitration Device 1 Device 2 Device 3 This arbitration mechanism is called daisy chain

26 Bus Arbitration Disadvantage of daisy chain The remote device low priority Other technique Each device is given priority repectively High priority device will make revisions before the other device For devices that have the same priority Used daisy chain

27 Distributed Bus Arbitration Does not need arbitration Use different bus requests 1 device 1 bus Each line has its own priorities High priority was given first review

28 Multi-programming and Input/Output Processor Execution of several programs in memory is done at the same time I/O Processor (IOP) Handle I/O device Modify the received data to a format adapted to the CPU data After IOP processing is complete, it will interrupt the CPU CPU stop doing his duties and perform operations duties for the IOP

29 Input Output Processor IOP for the IBM Machine known as channel 3 types of channel Multiplexor Connected to several devices that slow or medium speed. Selector Handle only one device with high-speed data transfer is done byte by byte Blocked-Multiplexor Provide facilities to handle multiple high-speed device transfer I/O performed by block.

30 Microcomputer Use a single bus Processor Main memory DMA-Direct Memory Access DMA controller IO Controller IO device

31 DMA Direct Memory Access Fully controlled by the CPU DMA request from the CPU to control bus If the CPU allows: It will take over the bus Do data transfer between the I/O and memory without the CPU DMA Controller Intel 8237A Interfaces to the 80x86 family of processors and to DRAM memory to provide a DMA capability.

32 DMA Direct Memory Access The DMA mechanism can be configured in a variety of ways. Some possible ways are; Single bus, detached DMA The DMA module, acting as surrogate processor, uses programmed I/O to exchange data between memory and an I/O module through DMA This configuration may inexpensive, is clearly inefficient. Single bus, integrated DMA-I/O The DMA may actually a part of an I/O module using an I/O bus. This reduces the number of I/O interfaces in the DMA module to one and provides for an easily expandable configuration. I/O Bus. The DMA module shares with the processor and memory is used by the DMA module only to exchange data with memory. The exchange of data between DMA and I/O modules takes place of the system bus. Turn to page 256 (Stalling, Eight Edition)

33 Other Bus EISA Extended Industry Standard Architecture To handle data size 32 bit VESA Video Electronics Standard Association Disk and monitor connected directly to the microprocessor SCSI Small Computer System Interface Connect the I/O device to a PC PCI Peripheral Control Interface

34 PCI Peripheral Control Interface Very popular with high bandwidth processor-independent bus. Deliver better system performance for high speed I/O subsystems. Designed to meet economically the I/O requirements of modern system. It requires very few chips to implement and supports other buses attached to the PCI Bus. Provides 2 type of busses 32 bit bus 64 bit bus Can support 1 processor or multiprocessor. The structure of PCI can be divided into the following functional groups: System pins. Address and data pins Interface control pins. Arbitration pins Error reporting pins.