WBS Trigger. Wesley H. Smith, U. Wisconsin CMS Trigger Project Manager. DOE/NSF Review June 5, 2002
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1 WBS Trigger Wesley H. Smith, U. Wisconsin CMS Trigger Project Manager DOE/NSF Review June 5, 2002 This talk is available on: W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 1
2 Outline Overview of Calorimeter Trigger Calorimeter Trigger Status & Plans Overview of Muon Trigger Muon Trigger Status & Plans Cost and Schedule Performance Concerns Summary and Conclusions W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 2
3 Trigger & DAQ Systems Level-1 Trigger Detector Frontend Readout Systems Event Manager Builder Networks Run Control Computing Services Filter Systems Level-1 Trigger Requirements: Input: 10 9 events/sec at 40 MHz at full L = Output: 100 khz (50 khz for initial running) Latency: 3 µsec for collection, decision, propagation W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 3
4 US CMS Trigger (this talk) L1 Trigger Hardware Overview US CMS fully responsible US CMS partially responsible W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 4
5 Calorimeter Trig.Overview (all located in underground counting room) W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 5
6 Data from calorimeter FE on Cu 1.2 Gbaud Into 126* rear Receiver Cards Prototype tested w/ ASICs Calorimeter Trigger Crate 160 MHz point to point backplane (proto. tstd.) 18 Clock&Control (proto. tstd.), 126 Electron ID (proto. tstd.), 18 Jet/Summary Cards -- all cards 160 MHz Use 5 Custom Gate-Array 160 MHz GaAs Vitesse Digital ASICs Phase, Adder, Boundary Scan, Electron Isolation, Sort (manufactured) Spares not included* W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 6
7 Successful Prototyping Program Crate & 160 MHz Backplane tested Clock Card tested Receiver Card tested (w/ Adder ASIC) Adder ASIC tested & production finished Electron Isolation Card tested 4 x 1.2 Gbaud Copper Serial Link system: Successfully transmits data at 4 Gbit/s over 20 m cable Clear eye pattern shows good signal after 20 m cable w/ all 4 links Measured Bit Error Rate < st Generation Calorimeter Trigger Prototype Tests (U. Wisconsin) Serial Receiver Mezzanine Card Serial Transmitter Mezzanine Card Serial Link Test Card Receiver Card Clock Card Backplane Electron Isolation Card W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 7
8 VME Slots Front Rear Cal. Trig. 2nd Gen. Prototypes DC- DC Conv (U. Wisconsin) New High-Speed Backplane 160 MHz with 0.4 Tbit/sec dataflow Mostly tested Designed to incorporate algorithm changes New Non-Isolated Electron, Tau & Jet Triggers New Clock & Control Card Fans out 160 MHz clock & adjusts phases for all boards 50% tested DC-DC Converters Clock delay adjust W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 8
9 New Cal. Trig. 4 Gbaud Copper Link Cards & Tester (U. Wisconsin) 8 Compact Mezzanine Cards for each Receiver Card accept 4 x 20 m 1.2-Gbaud copper pairs transmitting 2 cal. tower energies every 25 ns with low cost & power. Uses new Vitesse Link Chips ( ). New Serial Link Test Card Status: under test W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 9
10 New Calorimeter Trigger Receiver Card (U. Wisconsin) Full featured final prototype board is in test - initial results are good. Continue to test on-board ASICs & copper link mezzanine cards mezz link cards Adder BSCAN ASICs MLUs PHASE ASICs DC-DC Top side with 1 of 8 mezzanine cards & 2 of 3 Adder ASICs Bottom side with all Phase & Boundary Scan ASICs W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 10
11 EISO EISO Cal. Trig. New Electron Isolation & Jet/Summary Cards (Wisconsin) SORT ASICs Full featured final E.I. Proto. board is finished & ready for testing. JSC Proto. ready to build pending tests of other boards E.I. Proto will test Electron Isolation ASICs & Sort ASICs W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 11
12 Cal Trigger Status/Plans Second generation prototype tests underway Crate, Backplane, Clock & Control, ASICs, Receiver Card & Electron Isolation Card done & under test Jet/Summary Card designed & laid out Serial Link Mezzanine Card Receiver, Transmitter &, Tester Card done & under test Goals for 2002 Complete of prototype tests, validate ASICs Integrate Serial Links w/ecal,hcal front-ends Prototype Jet/Summary card manufacture Ready for manufacture -- waiting for other board tests Finalize Jet Cluster crate design W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 12
13 CSC Muon Trigger Overview (red = trigger responsibility) Muon Track-Finder Crate in underground counting room: Sector Receiver/Processor + Muon Sorter + Clock & Control Board ϕ θ Muon Port Card Clock Control Board Optical Link Slow Control Start w/ wire & strip segment combinations: Wires:25ns bunch xing Strips: precision ϕ Form Trigger Primitives Link into tracks Assign p T, ϕ, and η Send highest quality tracks to Global L1 D T D T D T D T D T C M T D T D T D T D M M M M M M M M M M C P M M M M M M M M C B B B B B B B B B B B C B B B B B B B B O N T R O L L E R CFEB CFEB CFEB CFEB CFEB LVDB CSC 1 of 2 ALCT Trig Motherboard 1 of 5 1 of 5 1 of 24 DAQ Motherboard Peripheral Crate on iron disk Cathode Front-end Board Anode Local Charged T rack Board LV Distribution Board Anode Front-end Board W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 13
14 EMU On-Chamber Trigger Primitives Strip FE cards FE FE Wire LCT* card Wire FE cards *Local Charged Track CSC Muon Trigger Scheme LCT RIM RPC Interface Module Trigger Motherboard (UCLA) LCT TMB Combination of all 3 Muon Systems Muon Port Card (Rice) MPC 2µ / chamber In counting house RPC Sector Receiver/ Processor (U. Florida) OPTICAL 3µ / port card Global µ Trigger SR/SP CSC Muon Sorter (Rice) W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 14 4µ DT Trigger 3-D Track-Finding and Measurement 4µ 4µ 3µ / sector 4µ SP Global L1
15 1st Muon Trigger Prototypes (Florida, Rice, UCLA) Successful CSC Trigger Integration test Prototype Muon Port Card, Sector Receiver, Sector Processor, Clock Board, Backplane work & communicate -- Result in 2000 ORCA full simulation working Agreement/use with hardware test W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 15
16 Sector Processor (Florida) Bit3 VME Interface Custom Backplane (Florida) Prototype crate for original six crate design 1st Track-Finder Crate Tests Sector Receiver (UCLA) Clock Control Board (Rice) Muon Port Card (Rice) Very successful, but overall CSC front end through trigger processing latency too high -- New design in m optical fibers W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 16
17 New EMU Trigger Design: U. Florida Track-Finder Single Track-Finder Crate Design with 1.6 Gbit/s optical links Clock and Control Board Muon Sorter BIT3 Controller SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP MS CCB SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR/SP Card (3 Sector Receivers + Sector Processor) (60 sector) From MPC (chamber 4) From MPC (chamber 3) From Trigger Timing & Control To Global Trigger From MPC (chamber 2) From MPC (chamber 1B) From MPC (chamber 1A) To DAQ Reduces processing time from 525 ns (old design) to 175 ns Total Latency ~ 15 Bx (from input of SR/SP card to output of MS card) Crate Power Consumption ~ 1000 W 16 Optical connections per SR/SP card Custom Backplane for SR/SP CCB and MS connection W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 17
18 New MPC Design uses new high speed links (TLK2501) to send one muon per optical fiber (needed for new compact track-finder design) New Muon Port Card Design & Optical Link Tests (Rice) 3 OPTICAL CABLES TO SECTOR PROCESSOR OPTICAL TRANSCEIVERS 9U * 400 MM BOARD OPTO OPTO OPTO SERIALIZERS SER SER SER CCB INTERFACE SORTER LOGIC INPUT AND OUTPUT FIFO FPGA VME INTERFACE VME J1 CONNECTOR TMB_1 TMB_2 CUSTOM TMB_3 PERIPHERAL TMB_4 BACKPLANE TMB_5 TMB_6 TMB_7 TMB_8 TMB_9 GTLP TRANSCEIVERS Optical Link Radiation Tests: Three serializers: up to 270 krad TID. No permanent damage or SEU Two Finisar optical modules: No errors up to 70 krad. Failed at 70kRad (well above ~10 krad TID inner CSC dose for 10 years) W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 18
19 EEPROM Indicators TLK2501 Transceiver SR/SP 2002 Board Layout Phi Global LUT Eta Global LUT Phi Local LUT (U. Florida) DC-DC Converter EEPROM EEPROM VME/CCB FPGA Front FPGA From CCB DDU FPGA Optical Transceiver Main FPGA Mezzanine Card PT LUT To MS TRANSITION BOARD WITH LVDS TRANSCEIVERS TO/ FROM BARREL W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 19
20 CSC Track Finder Backplane (U. Florida) Standard VME J2/P2 backplane Design Approved Technology same as EMU peripheral crates Standard VME 64x J1/P1 backplane SRSP 6 SRSP 5 SRSP 4 SRSP 3 SRSP 2 SRSP 1 Clock and control Rice Muon sorter Custom GTLP 6U backplane SRSP 10 SRSP 9 SRSP 8 SRSP 7 SRSP 11 GTLP backplane avoids latency penalty of previous Channel-Link backplane (~3BX) SRSP 12 These SRSP feedthru connectors are for DT information exchange via transition board W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 20
21 New Muon Sorter Design (Rice) Reduced to single board -- reduces latency, cost LVDS DRIVERS 9U * 400 MM BOARD VME INTERFACE VME J1 CONNECTOR CONNECTORS TO GMT CABLES TO GLOBAL MUON TRIGGER CRATE New: Will use common Xilinx mezzanine card with Sector Processor CCB INTERFACE SORTER LOGIC INPUT AND OUTPUT FIFO SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9 SP10 SP11 SP12 CUSTOM BACKPLANE GTLP TRANSCEIVERS W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 21
22 CSC Trigger Status/Plans Prototype 1 tests now complete Prototype 2 and production follow EMU components to optimize technology MPC, SP, CCC modules, backplane* milestones: Apr-02 Prototype 2 designs done Freeze CSC-DT interface Determine DAQ interface w/ EMU readout Nov-02 Prototype 2 construction done Apr-03 Prototype 2 testing done (begin EMU integration) Sep-03 Final designs done Oct-04 Production done Apr-05 Installation done (*backplane schedule ~3 months ahead of above dates to provide platform for testing and integration) Muon Sorter module: only 1, design by Jan-04 W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 22
23 US Trigger FY02 Planning Trigger SOWs FY02 -- $1.7M Muon Trigger Sector Receiver/Processor & Backplane Prototypes (Florida) Muon Trigger Muon Port Card & Clock/Control Prototypes (Rice) University of California-Los Angeles University of Florida Rice University University of Wisconsin Cal Trigger Prototype Boards, Production ASICs & Validated Production Components w/long order time or obsolescence risk (Wisconsin) W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 23
24 RCT Delays of 3-5 months: Reorganized board schedule to accelerate Vitesse ASIC testing Delay JSC since not needed for ASIC tests Success with 1st generation prototypes make 2nd generation prototypes preproduction Longer design time delays testing Saves time later in schedule Recent Trigger Milestone Performance (v31) Not US W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 24
25 Installation in Underground Counting Room Expect access by March 05 Delay of 1 year from baseline Sufficient time for installation & some testing but not for complete commissioning with detectors Slice Test (on surface) With both HCAL and EMU Verify trigger functions & Completion &Transition to M&O UXC55 W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 25 USC55 Underground Counting Room interfaces by testing w/detectors on surface at CERN. Suggest as substitute for commissioning completion step. Will check as much on surface before gaining access to underground facilities. Planned for October 04 - March 05
26 Baseline Trigger L2 Task Schedule & Updates Tasks start finish new Produce TDR 8/00 12/00 Design Final Prototypes 11/00 12/01 Construct Final Prototypes 6/01 6/02 11/02 Test/Integrate Final Prototypes 12/01 12/02 4/03 Pre-Production Design & Test 6/02 6/03 11/03 Production 12/02 6/04 Production Test 6/03 11/04 Trigger System Tests 5/04 5/05 "Slice Test" (NEW) 10/04 3/05 Trigger Installation 3/05 9/05 Integration & Test w/daq & FE 6/05 12/05 Maintenance & Operations 10/ months civil engineering delay of installation date With respect to date reported at Lehman 01 W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 26
27 US Trigger Estimate-to-Complete US Trigger Estimate-to-Complete = $4.6M AY 1998 Project Baseline Total Cost = $7.6M AY 2002 Project Total Cost = $8.5M AY 0% 62% 38% EDIA M&S Labor As of May 02 Trigger Project is 46% Complete Costs up 12% over 98 baseline (50% contingency) W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 27
28 FTE's US TRIG Project Resources (FTE s) US CMS Trigger Construction Project Resources Production & Test FY98 FY99 FY00 FY01 FY02 FY03 FY04 FY05 Installation: ramp down to M&O Technicians Engineers Post-Docs W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 28
29 US Trigger M&O Resources FTE's Commissioning M&O Slice Test M&O Physics M&O Maintain critical eng/tech personnel Technician Engr/Comp Prof Physicist/Post-Doc FY02 FY03 FY04 FY05 FY06 FY07 FY08 FY09 From April 02 DOE/NSF Review of U.S. LHC Research Program W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 29
30 Trigger Commitments Trigger - Construction and Operations AY$ Slice Test Begins TRIG-Ops TRIG Installation Begins Production & Tests End Installation Ends Physics Data FY96 FY98 FY00 FY02 FY04 FY06 FY08 FY10 W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 30
31 Concerns Installation Schedule New schedule has reduced installation time Significant time needed for integration in a synchronous pipelined system. Base Program Manpower Major effort on trigger software required Tasks include board testing, monitoring/controls, diagnostics, configuration downloading and documentation, modeling, physics simulation, etc. Major effort on testing & installation Planned as activity of base program manpower New Major Effort on Slice Test Motivated by installation delay Also needs base program manpower W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 31
32 Calorimeter Trigger Conclusions - Trigger All second generation prototype boards and ASICs built and under test Except jet summary card -- ready for manufacture Initial test results look good Integration tests w/ecal,hcal start this Fall Muon Trigger All second generation prototype boards and their FPGA logic are designed Construction is starting Integration tests start w/emu next Spring W. Smith, U. Wisconsin, US CMS DOE/NSF Review, June 5, 2002: Trigger 32
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