4-Mbit (256K words 16 bit) Static RAM

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1 4-Mbit (256K words 16 bit) Static RAM 4-Mbit (256K words 16 bit) Static RAM Features High speed t AA = 10 ns / 15 ns Low active and standby currents Active current: I CC = 38-mA typical Standby current: I SB2 = 6-mA typical Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V to 5.5 V 1.0-V data retention TTL-compatible inputs and outputs Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA packages Functional Description CY7C1041GN is high-performance CMOS fast static RAM Organized as 256K words by 16-bits. Data writes are performed by asserting the Chip Enable (CE) and Write Enable (WE) inputs LOW, while providing the data on I/O 0 through I/O 15 and address on A 0 through A 17 pins. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control write operations to the upper and lower bytes of the specified memory location. BHE controls I/O 8 through I/O 15 and BLE controls I/O 0 through I/O 7. Data reads are performed by asserting the Chip Enable (CE) and Output Enable (OE) inputs LOW and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O 0 through I/O 15 ). Byte accesses can be performed by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O 0 through I/O 15 ) are placed in a high-impedance state during the following events: The device is deselected (CE HIGH) The control signals (OE, BLE, BHE) are de-asserted The logic block diagram is on page 2. Product Portfolio Product Range V CC Range (V) Power Dissipation Speed (ns) Operating I CC, (ma) Standby, I SB2 (ma) f = f 10/15 max Typ [1] Max Typ [1] Max CY7C1041GN V 2.2 V CY7C1041GN30 Industrial 2.2 V 3.6 V CY7C1041GN 4.5 V 5.5 V Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V CC = 1.8 V (for a V CC range of 1.65 V 2.2 V), V CC = 3 V (for a V CC range of 2.2 V 3.6 V), and V CC = 5 V (for a V CC range of 4.5 V 5.5 V), T A = 25 C. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number: Rev. *D Revised September 9, 2016

2 Logic Block Diagram CY7C1041GN INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER MEMORY ARRAY SENSE AMPLIFIERS I/O 0 I/O 7 I/O 8 I/O 15 COLUMN DECODER A10 A11 A12 A13 A14 A15 A16 A17 BHE WE OE BLE CE 1 Document Number: Rev. *D Page 2 of 18

3 Contents Pin Configurations... 4 Maximum Ratings... 5 Operating Range... 5 DC Electrical Characteristics... 5 Capacitance... 6 Thermal Resistance... 6 AC Test Loads and Waveforms... 6 Data Retention Characteristics... 7 Data Retention Waveform... 7 AC Switching Characteristics... 8 Switching Waveforms... 9 Truth Table Ordering Information Ordering Code Definitions Package Diagrams Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Cypress Developer Community Technical Support Document Number: Rev. *D Page 3 of 18

4 Pin Configurations Figure ball VFBGA ( mm) pinout, Figure Package/Grade ID: BVXI [2, 3] ball VFBGA ( mm) pinout, Package/Grade ID: BVJXI [2] BLE OE A 0 A 1 A 2 NC A BLE OE A 0 A 1 A 2 NC A I/O 0 BHE A 3 A 4 CE I/O 8 B I/O 8 BHE A 3 A 4 CE I/O 0 B I/O 1 I/O 2 A 5 A 6 I/O 10 I/O 9 C I/O 9 I/O 10 A 5 A 6 I/O 1 I/O 2 C VSS I/O 3 A 17 A 7 I/O 11 VCC D VSS I/O 11 A 17 A 7 I/O 3 VCC D VCC I/O 4 NC A 16 I/O 12 VSS E VCC I/O 12 NC A 16 I/O 4 VSS E I/O 6 I/O 5 A 14 A 15 I/O 13 I/O 14 F I/O 14 I/O 13 A 14 A 15 I/O 5 I/O 6 F I/O 7 NC A 12 A 13 WE I/O 15 G I/O 15 NC A 12 A 13 WE I/O 7 G NC A 8 A 9 A 10 A 11 NC H NC A 8 A 9 A 10 A 11 NC H Figure pin TSOP II / 44-pin SOJ pinout [2] A A A A A /CE 6 39 I/O I/O I/O pin TSOP II I/O VCC VSS I/O I/O I/O I/O /WE A A A A A A17 A16 A15 /OE /BHE /BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 2. NC pins are not connected internally to the die. 3. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O [7:0] and I/O [15:8] balls are swapped. Document Number: Rev. *D Page 4 of 18

5 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature C to +150 C Ambient temperature with power applied C to +125 C Supply voltage on V CC relative to GND [4] V to V CC V DC voltage applied to outputs in HI-Z State [4] V to V CC V DC input voltage [4] V to V CC V DC Electrical Characteristics Current into outputs (in LOW state) ma Static discharge voltage (MIL-STD-883, Method 3015)... > 2001 V Latch-up current... > 140 ma Operating Range Grade Ambient Temperature V CC Industrial 40 C to +85 C 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V Over the operating range of 40 C to 85 C Parameter Description Test Conditions V OH V OL V IH Output HIGH voltage Output LOW voltage Input HIGH voltage 10 ns / 15 ns Min Typ [5] Max 1.65 V to 2.2 V V CC = Min, I OH = 0.1 ma V to 2.7 V V CC = Min, I OH = 1.0 ma V to 3.0 V V CC = Min, I OH = 4.0 ma V to 3.6 V V CC = Min, I OH = 4.0 ma V to 5.5 V V CC = Min, I OH = 4.0 ma V to 5.5 V V CC = Min, I OH = 0.1 ma V CC 0.5 [6] 1.65 V to 2.2 V V CC = Min, I OL = 0.1 ma V to 2.7 V V CC = Min, I OL = 2 ma V to 3.6 V V CC = Min, I OL = 8 ma V to 5.5 V V CC = Min, I OL = 8 ma V to 2.2 V 1.4 V CC [4] 2.2 V to 2.7 V 2 V CC [4] 2.7 V to 3.6 V 2 V CC [4] 4.5 V to 5.5 V 2 V CC [4] 1.65 V to 2.2 V 0.2 [4] 0.4 V IL Input LOW voltage 2.2 V to 2.7 V 0.3 [4] V to 3.6 V 0.3 [4] 0.8 V 4.5 V to 5.5 V 0.5 [4] 0.8 I IX Input leakage current GND < V IN < V CC 1 +1 A I OZ Output leakage current GND < V OUT < V CC, Output disabled 1 +1 A I CC Operating supply current Automatic CE power-down current I SB1 TTL inputs I Automatic CE power-down current SB2 CMOS inputs Max V CC, I OUT = 0 ma, CMOS levels f = 100 MHz f = 66.7 MHz 40 Max V CC, CE > V IH, V IN > V IH or V IN < V IL, f = f MAX 15 ma Max V CC, CE > V CC 0.2 V, V IN > V CC 0.2 V or V IN < 0.2 V, f = 0 Unit V V V ma 6 8 ma 4. V IL(min) = 2.0 V and V IH(max) = V CC + 2 V for pulse durations of less than 20 ns. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V CC = 1.8 V (for V CC range of 1.65 V 2.2 V), V CC =3V (for V CC range of 2.2 V 3.6 V), and V CC = 5 V (for V CC range of 4.5 V 5.5 V), T A = 25 C. 6. This parameter is guaranteed by design and not tested. Document Number: Rev. *D Page 5 of 18

6 Capacitance Parameter [7] Description Test Conditions 48-ball VFBGA 44-pin SOJ 44-pin TSOP II Unit C IN Input capacitance T A = 25 C, f = 1 MHz, pf C OUT I/O capacitance V CC = V CC(typ) pf Thermal Resistance Parameter [7] Description Test Conditions 48-ball VFBGA 44-pin SOJ 44-pin TSOP II Unit JA JC Thermal resistance (junction to ambient) Thermal resistance (junction to case) Still air, soldered on a inch, four-layer printed circuit board C/W C/W AC Test Loads and Waveforms Figure 4. AC Test Loads and Waveforms [8] Output Z 0 = 50 (a) * Capacitive load consists of all components of the test environment 50 V TH 30 pf* V HIGH 90% 10% GND Rise Time: > 1 V/ns All Input Pulses (c) High-Z Characteristics: V CC Output 5 pf* * Including jig and scope (b) 90% 10% Fall Time: > 1 V/ns R1 R2 Parameters 1.8 V 3.0 V 5.0 V Unit R R V TH V V HIGH V 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full-device AC operation assumes a 100-µs ramp time from 0 to V CC(min) and a 100-µs wait time after V CC stabilization. Document Number: Rev. *D Page 6 of 18

7 Data Retention Characteristics Over the operating range of 40 C to 85 C Parameter Description Conditions Min Max Unit V DR V CC for data retention 1 V I CCDR t CDR [10] t R [9, 10] Data retention current Chip deselect to data retention time Operation recovery time V CC = 1.2 V, CE > V CC 0.2 V [9], V IN > V CC 0.2 V, or V IN < 0.2 V 8 ma 0 ns V CC > 2.2 V 10 ns V CC < 2.2 V 15 ns Data Retention Waveform Figure 5. Data Retention Waveform [9] V CC V CC(min) DATA RETENTION MODE V DR = 1.0 V V CC(min) t CDR t R CE 9. Full-device operation requires linear V CC ramp from V DR to V CC(min) > 100 s or stable at V CC (min) > 100 s. 10. These parameters are guaranteed by design. Document Number: Rev. *D Page 7 of 18

8 AC Switching Characteristics Over the operating range of 40 C to 85 C Parameter [11] Read Cycle Description 10 ns 15 ns Min Max Min Max t RC Read cycle time ns t AA Address to data ns t OHA Data hold from address change 3 3 ns t ACE CE LOW to data [12] ns t DOE OE LOW to data ns t LZOE OE LOW to low impedance [13, 14] 0 0 ns t HZOE OE HIGH to HI-Z [13, 14] 5 8 ns t LZCE CE LOW to low impedance [12, 13, 14] 3 3 ns t HZCE CE HIGH to HI-Z [12, 13, 14] 5 8 ns t PU CE LOW to power-up [12, 14, 15] 0 0 ns t PD CE HIGH to power-down [12, 14, 15] ns t DBE Byte enable to data valid ns t LZBE Byte enable to low impedance [14] 0 0 ns t HZBE Byte disable to HI-Z [14] 6 8 ns Write Cycle [15, 16] t WC Write cycle time ns t SCE CE LOW to write end [12] 7 12 ns t AW Address setup to write end 7 12 ns t HA Address hold from write end 0 0 ns t SA Address setup to write start 0 0 ns t PWE WE pulse width 7 12 ns t SD Data setup to write end 5 8 ns t HD Data hold from write end 0 0 ns t LZWE WE HIGH to low impedance [13, 14] 3 3 ns t HZWE WE LOW to HI-Z [13, 14] 5 8 ns t BW Byte Enable to write end 7 12 ns Unit 11. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for V CC > 3 V) and V CC /2 (for V CC < 3 V), and input pulse levels of 0 to 3 V (for V CC > 3 V) and 0 to V CC (for V CC < 3 V). Test conditions for the read cycle use output loading, as shown in part (a) of Figure 4 on page 6, unless specified otherwise. 12. For all dual chip enable devices, CE is the logical combination of CE 1 and CE 2. When CE 1 is LOW and CE 2 is HIGH, CE is LOW; when CE 1 is HIGH or CE 2 is LOW, CE is HIGH. 13. t HZOE, t HZCE, t HZWE, t HZBE, t LZOE, t LZCE, t LZWE, and t LZBE are specified with a load capacitance of 5 pf, as shown in part (b) of Figure 4 on page 6. Transition is measured 200 mv from steady state voltage. 14. These parameters are guaranteed by design and are not tested. 15. The internal write time of the memory is defined by the overlap of WE = V IL, CE = V IL, and BHE or BLE = V IL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 16. The minimum write cycle pulse width in Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of t SD and t HZWE. Document Number: Rev. *D Page 8 of 18

9 Switching Waveforms Figure 6. Read Cycle No. 1 (Address Transition Controlled) [17, 18] t RC ADDRESS t AA t OHA DATA I/O PREVIOUS DATA OUT VALID DATA OUT VALID Figure 7. Read Cycle No. 2 (OE Controlled) [18, 19] ADDRESS t RC CE t PD t ACE t HZCE OE t DOE t HZOE BHE/ BLE t LZOE t DBE t LZBE t HZBE DATA I/O HIGH IMPEDANCE DATA OUT VALID HIGH IMPEDANCE t LZCE t PU V CC SUPPLY CURRENT I SB 17. The device is continuously selected, OE = V IL, CE = V IL, BHE or BLE or both = V IL. 18. WE is HIGH for the read cycle. 19. Address valid prior to or coincident with CE LOW transition. Document Number: Rev. *D Page 9 of 18

10 Switching Waveforms (continued) Figure 8. Write Cycle No. 1 (CE Controlled) [20, 21] t W C ADDRESS t SA t SCE CE t AW t HA t PW E WE t BW BHE/ BLE OE t HZOE t SD t HD DATA I/O DATAIN VALID [20, 21, 22] Figure 9. Write Cycle No. 2 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE BHE / BLE t BW WE t SA t AW t PWE t HA t LZWE t HZWE t SD t HD DATA I/O DATA IN VALID 20. The internal write time of the memory is defined by the overlap of WE = V IL, CE = V IL, and BHE or BLE = V IL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 21. Data I/O is in HI-Z state if CE = V IH, or OE = V IH, or BHE, and/or BLE = V IH. 22. The minimum write cycle pulse width should be equal to sum of t SD and t HZWE. Document Number: Rev. *D Page 10 of 18

11 Switching Waveforms (continued) Figure 10. Write Cycle No. 3 (BLE or BHE Controlled) [23, 24] t WC ADDRESS CE t SCE t AW t SA t BW t HA BHE/ BLE WE t PWE t HZWE t SD t HD t LZWE DATA I /O DATA IN VALID Figure 11. Write Cycle No. 4 (WE Controlled) [23, 24, 25] t WC ADDRESS t SCE CE 1 CE 2 t AW t HA WE t SA t PWE BHE/BLE t BW OE t HD DATA I/O NOTE 26 t SD DATA IN VALID t HZOE 23. The internal write time of the memory is defined by the overlap of WE = V IL, CE = V IL, and BHE or BLE = V IL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 24. Data I/O is in HI-Z state if CE = V IH, or OE = V IH, or BHE, and/or BLE = V IH. 25. Data I/O is high impedance if OE = V IH. 26. During this period the I/Os are in output state. Do not apply input signals. Document Number: Rev. *D Page 11 of 18

12 Truth Table CE OE WE BLE BHE I/O 0 I/O 7 I/O 8 I/O 15 Mode Power H X [27] X [27] X [27] X [27] HI-Z HI-Z Power down Standby (I SB ) L L H L L Data out Data out Read all bits Active (I CC ) L L H L H Data out HI-Z Read lower bits only Active (I CC ) L L H H L HI-Z Data out Read upper bits only Active (I CC ) L X L L L Data in Data in Write all bits Active (I CC ) L X L L H Data in HI-Z Write lower bits only Active (I CC ) L X L H L HI-Z Data in Write upper bits only Active (I CC ) L H H X X HI-Z HI-Z Selected, outputs disabled Active (I CC ) 27. The input voltage levels on these pins should be either at V IH or V IL. Document Number: Rev. *D Page 12 of 18

13 Ordering Information Speed (ns) Voltage Range Ordering Code Package Diagram Package Type (all Pb-free) Operating Range CY7C1041GN30-10ZSXI pin TSOP II CY7C1041GN30-10ZSXI pin TSOP II, Tape & Reel CY7C1041GN30-10VXI pin SOJ 2.2 V 3.6 V CY7C1041GN30-10VXIT CY7C1041GN30-10BVXI pin SOJ, Tape & Reel ball VFBGA ( mm) 10 CY7C1041GN30-10BVXIT CY7C1041GN30-10BVJXI ball VFBGA ( mm), Tape & Reel ball VFBGA ( mm), JEDEC Compatible Industrial CY7C1041GN30-10BVJXIT ball VFBGA ( mm), JEDEC Compatible, Tape & Reel CY7C1041GN-10ZSXI pin TSOP II 4.5 V 5.5 V CY7C1041GN-10ZSXIT CY7C1041GN-10VXI pin TSOP II, Tape & Reel pin SOJ CY7C1041GN-10VXIT pin SOJ, Tape & Reel Ordering Code Definitions CY 7 C GN XX - XX XX X I X X: T = Tape & Reel; Blank = Bulk Temperature Range: I = Industrial Pb-free Package Type: XX = ZS or BV or BVJ ZS = 44-pin TSOP II; V = 44-pin SOJ; BV = 48-ball VFBGA; BVJ = 48-ball VFBGA JEDEC Compatible Speed: XX = 10 ns Voltage Range: 30 = 2.2 V 3.6 V Process Technology: Revision Code GN = 65 nm Data Width: 1 = 16-bits Density: 04 = 4-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: Rev. *D Page 13 of 18

14 Package Diagrams Figure pin TSOP II (Z44) Package Outline, *E Figure pin SOJ (400 Mils) Package Outline, *E Document Number: Rev. *D Page 14 of 18

15 Package Diagrams (continued) Figure ball VFBGA ( mm) BV48/BZ48 Package Outline, *H Document Number: Rev. *D Page 15 of 18

16 Acronyms Document Conventions Acronym BHE BLE CE CMOS I/O OE SRAM TSOP TTL VFBGA WE Description byte high enable byte low enable chip enable complementary metal oxide semiconductor input/output output enable static random-access memory thin small outline package transistor-transistor logic very fine-pitch ball grid array write enable Units of Measure Symbol Unit of Measure C Degrees Celsius MHz megahertz A microamperes s microseconds ma milliamperes mm millimeters ns nanoseconds ohms % percent pf picofarads V volts W watts Document Number: Rev. *D Page 16 of 18

17 Document History Page Document Title: CY7C1041GN, 4-Mbit (256K words 16 bit) Static RAM Document Number: Rev. ECN No. Orig. of Change Submission Date ** NILE 01/06/2016 New data sheet. Description of Change *A NILE 01/12/2016 Updated Logic Block Diagram CY7C1041GN. Updated Ordering Information: Updated part numbers. *B VINI 02/01/2016 Updated Logic Block Diagram CY7C1041GN. *C VINI 06/24/2016 *D NILE 09/09/2016 Updated Ordering Information: Updated part numbers. Updated to new template. Updated Ordering Information: Updated part numbers. Added Tape & Reel ordering codes. Updated DC Electrical Characteristics: Enhanced V OH for voltage range 3.0V to 3.6V from 2.2V to 2.4V. Enhanced V IH for voltage range 4.5V to 5.5V from 2.2V to 2.0V. Updated Note 4. Updated Copyright and Disclaimer. Document Number: Rev. *D Page 17 of 18

18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM Cortex Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/powerpsoc cypress.com/memory cypress.com/psoc cypress.com/touch cypress.com/usb cypress.com/wireless PSoC Solutions PSoC 1 PSoC 3 PSoC 4 PSoC 5LP Cypress Developer Community Forums Projects Video Blogs Training Components Technical Support cypress.com/support Cypress Semiconductor Corporation, This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: Rev. *D Revised September 9, 2016 Page 18 of 18

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