LAB #1 BASIC DIGITAL CIRCUIT
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1 LAB #1 BASIC DIGITAL CIRCUIT OBJECTIVES 1. To study the operation of basic logic gates. 2. To build a logic circuit from Boolean expressions. 3. To introduce some basic concepts and laboratory techniques in working with digital logic gates. INTRODUCTIONS A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two binary conditions low (0) or high (1), represented by different voltage levels. The logic state of a terminal can, and generally does, change often, as the circuit processes data. In most logic gates, the low state is approximately zero volts (0 V), while the high state is approximately five volts positive (+5 V). Logic gates are the simplest component of any logic circuit. So, to understand the computer logic, you should understand and master the logic operators (gates). A gate is a digital electronic circuit having only one output but one or more inputs. The output or a signal will appear at the output of the gate only for certain input-signal combinations. There are many types of logic gates; such as AND, OR and NOT, which are usually called the three basic gates. Other popular gates are the NAND and the NOR gates; which are simply combinations of an AND or an OR gate with a NOT gate inserted just before the output signal. Other gates include the XOR Exclusive-OR and the XNOR "Exclusive NOR" gates. Using combinations of logic gates, complex operations can be performed. In theory, there is no limit to the number of gates that can be arrayed together in a single device. But in practice, there is a limit to the number of gates that can be packed into a given physical space. Arrays of logic gates are found in digital integrated circuits (ICs). As IC technology advances, the required physical volume for each individual logic gate decreases and digital devices of the same or smaller size become capable of performing ever-more-complicated operations at ever-increasing speeds. In this experiment, we will investigate all known logic gates and study their operations according to the truth table. REQUIREMENT 1. Full pack of HBE-LogicCircuit-Digital 2. Cooper Cable PRE-LAB WORK TASK 1. Read the Lab Work s Technical Guide first!
2 2. Learn the Data Sheet of each Logic Gates used in this lab work! 3. Name the three families used in Digital IC and its advantage(s)! 4. What is a Truth Table? 5. Draw a series of 2-input NAND and NOT by using BJT transistors, explain how it works! 6. Write the equation of De Morgan s Law! 7. What is the operation of POS and SOP? Explain! 8. What do you know about Binary Half Adder and Binary Full Adder! = -3, explain the reduction of these equations in binary! EXPERIMENT 1 : LOGIC GATES [Trial 1] AND Operation AND Gate 1. As Fig. I-1, use AND module and connect the circuit with cable. Fig. I-1. AND Operation Test Diagram 2. Check the result of output Y by input A and B on LED and write the result on Table I-1. Table I-1. Result Table of AND Operation [Trial 2] OR Operation OR Gate
3 1. As Fig. I-2, use OR module and connect the circuit with cable. Fig. I-2. OR Operation Test Diagram 2. Check the result of output Y by input A and B on LED and write the result on Table I-2. Table I-2. Result Table of OR Operation [Trial 3] NOT Operation Slide Switch (SW1), LED (D1) NOT Gate 1. As Fig. I-3, use NOT module and connect the circuit with cable. Fig. I-3. NOT Operation Test Diagram 2. Check the result of output Y by input A on LED and write the result on Table I-3. Table I-3. Result Table of NOT Operation A Y 0 1
4 [Trial 4] NAND Operation NAND Gate 1. As Fig. I-4, use NAND module and connect the circuit with cable. Fig. I-4. NAND Operation Test Diagram 2. Check the result of output Y by input A and B on LED and write the result on Table I-4. Table I-4. Result Table of NAND Operation [Trial 5] NOR Operation NOR Gate 1. As Fig. I-5, use NOR module and connect the circuit with cable. Fig. I-5. NOR Operation Test Diagram
5 2. Check the result of output Y by input A and B on LED and write the result on Table I-5. Table I-5. Result Table of NOR Operation [Trial 6] XOR Operation XOR Gate 1. As Fig. I-6, use XOR module and connect the circuit with cable. Fig. I-6. XOR Operation Test Diagram 2. Check the result of output Y by input A and B on LED and write the result on Table I-6. Table I-6. Result Table of XOR Operation EXPERIMENT 2 : BOOLEAN ALGEBRA [Trial 7] Distributive Law : A + ( B. C ) = ( A + B ). ( A + C ) Slide Switch (SW1, SW2, SW3), LED (D1)
6 AND Gate, OR Gate 1. Use AND module and OR module in order to make 2 circuits of (a) and (b) on Fig. I- 7 on the logic circuit block. (a) (b) Fig. I-7. Distributive Law Operation Test Diagram 2. Check the result of output Y(a) and Y(b) by input A, B, and C on LED and write the result on Table I-7. Table I-7. Result Table of Distributive Law A B C Y(a) Y(b) EXPERIMENT 3 : COMBINATIONAL LOGIC CIRCUIT [Trial 8] Half Adder Slide Switch (SW1, SW2), LED (D1, D2)
7 XOR Gate, AND Gate 1. Prepare the gate modules in order to make a Half Adder circuit on Fig. I-8 on the logic circuit block. Fig. I-8. Half Adder Operation Test Diagram 2. Check the result of output S and C by input A and B on LED and write the result on Table I-8. Table I-8. Result Table of Half Adder A (SW1) B (SW2) S (D1) C (D2) 3. Simulate it using DAQ simulation. And then, save the waveform and attach it in your report. [Trial 9] Full Adder Slide Switch (SW1, SW2, SW3), LED (D1, D2) XOR Gate, AND Gate, OR Gate 1. Prepare the gate modules for Full Adder circuit diagram on Fig. I-9 and connect the circuit.
8 Fig. I-9. Full Adder Operation Test Diagram 2. Check the result of output S and C o by input A, B and C o on LED and write the result on Table I-9. Table I-9. Result Table of Full Adder A (SW1) B (SW2) C i (SW3) S (D1) C o (D2) Simulate it using DAQ simulation. And then, save the waveform and attach it in your report. [Trial 10] Full Substracter Slide Switch (SW1, SW2, SW3), LED (D1, D2) XOR Gate, AND Gate, OR Gate, NOT Gate 1. Prepare the gate modules for Full Substracter circuit diagram on Fig. I-10 and connect the circuit.
9 Fig. I-10. Full Substracter Operation Test Diagram 2. Check the result of output S and B o by input A, B and B o on LED and write the result on Table I-10. Table I-10. Result Table of Full Substracter A (SW1) B (SW2) B i (SW3) S (D1) B o (D2) Simulate it using DAQ simulation. And then, save the waveform and attach it in your report. ASSIGNMENT 1. Simulate all of Trial in Circuit Maker! 2. Fill this table : A B A B A. B A. B A + B 3. Make OR and XOR gate module from NAND and NOT gate module! 4. In Distributive Law, which one is easier and cheaper to make : a. Only use NAND gate module in order to make the circuit b. Using AND and OR gate module as in the Trial Explain your answer! 5. Explain how Half Adder, Full Adder, and Full Substracter works!
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