Running Applications
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1 Running Applications
2 Computer Hardware
3 Central Processing Unit (CPU) CPU PC IR MAR MBR I/O AR I/O BR To exchange data with memory Brain of Computer, controls everything Few registers PC (Program Counter): Contains the address (in memory) of the instruction to be executed next IR (Instruction Register): Contains the instruction being executed MAR (Memory Address Register): Contains the address in memory for the next read/write to/from MBR MBR (Memory Buffer Register): Contains the data to be read/written from/to memory
4 CPU MAR Memory Read Write Address In MBR Data In Data Out To exchange data with I/O devices I/O AR (I/O Address Register): Contains the ID (address) of an I/O device I/O BR (I/O Buffer Register): Contains the data to be sent/received to/from the I/O device
5 Instruction Execution Start Fetch Next Instruction Execute Instruction Halt Instruction Cycle : Execution of a program Basic function of a computer: Program execution Program: Set of instructions in memory waiting to be executed
6 Instruction Execution PC contains the address of the instruction to be fetched next Processor fetches the pointed instruction and puts into IR PC is incremented to point to the next instruction Processor interprets the instruction Processor-memory: Data transfer between processor-memory Processor-I/O: Data transfer between processor and I/O device via an I/O module Data processor: Some arithmetic or logical operation is performed on data Control: Execution sequence is altered
7 Instruction Execution Instruction phase Step 1: Fetch instruction Step : Decode instruction Execution phase Step : Execute the instruction Step 4: Store the results
8 Program execution example opcode memory address 0001 : Load AC from memory 0010 : Load AC to memory 0101 : Add to AC from memory Program: Write a program that adds the contents of memory word at address (940) to contents of the memory word at address (941) and store the result in (941) Load (940) to AC Add (941) to AC 941 Store AC to (941) When instruction is fetched and put to IR, PC incremented to point to the next instruction PC IR AC FETCH
9 Program execution example opcode memory address 0001 : Load AC from memory 0010 : Load AC to memory 0101 : Add to AC from memory Program: Write a program that adds the contents of memory word at address (940) to contents of the memory word at address (941) and store the result in (941) Load (940) to AC Add (941) to AC 941 Store AC to (941) PC IR PC IR AC AC FETCH EXECUTE
10 Program execution example opcode memory address Program: Write a program that adds the contents of memory word at address (940) to contents of the memory word at address (941) and store the result in (941) 0001 : Load AC from memory 0010 : Load AC to memory 0101 : Add to AC from memory Load (940) to AC Add (941) to AC 941 Store AC to (941) PC IR AC FETCH
11 Program execution example opcode memory address Program: Write a program that adds the contents of memory word at address (940) to contents of the memory word at address (941) and store the result in (941) 0001 : Load AC from memory 0010 : Load AC to memory 0101 : Add to AC from memory Load (940) to AC Add (941) to AC 941 Store AC to (941) PC IR PC IR AC AC 5 FETCH EXECUTE
12 Program execution example opcode memory address Program: Write a program that adds the contents of memory word at address (940) to contents of the memory word at address (941) and store the result in (941) 0001 : Load AC from memory 0010 : Load AC to memory 0101 : Add to AC from memory Load (940) to AC Add (941) to AC 941 Store AC to (941) PC IR AC 5 FETCH
13 Program execution example opcode memory address Program: Write a program that adds the contents of memory word at address (940) to contents of the memory word at address (941) and store the result in (941) 0001 : Load AC from memory 0010 : Load AC to memory 0101 : Add to AC from memory Load (940) to AC Add (941) to AC 941 Store AC to (941) PC IR PC IR AC 5 AC 5 FETCH EXECUTE
14 Interrupts User Program Interrupt Handler 1 a small piece of code e.g instructions i i+1 interrupt occurs here Handling interrupts: Normal sequence of program execution is interrupted. When the interrupt processing is completed, execution resumes. This mechanism is under the responsibility of the processor and the OS; the program is unaware of it.
15 Instruction cycle with interrupts Interrupts disabled Start Fetch Next Instruction Execute Instruction Interrupts enabled Check for interrupt; Process interrupted Halt
16 Question What happens when we don t have interrupts? Let s consider a scenario of a user program that contains output instructions 1 write write 4 I/O execution 5 I/O program User Program
17 Let s examine times Suppose: Code Execution time (ms) 1 10 ms 10 ms 10 ms 4 5 ms 5 5 ms I/O 10 ms
18 Multiple Interrupts While an interrupted is being serviced, another interrupt is raised Three approaches: Discard Not preferable, should be handled Defer Interrupts are disabled while another interrupt is being processed
19 Deferred interruption 1 4 Interrupt Handler X Interrupt Handler Y Program Only after the current interrupt is completed, pending interrupts are accepted Interrupts are handled in sequential order Advantage: Simple to design Disadvantage: Does not consider relative priority or timecritical needs
20 Priorities: Multiple Interrupts 1 4 Interrupt Handler X Interrupt Handler Y Process Priorities are defined for interrupts Program If an interrupts with a higher priority arrives, a lower priority interrupt can be interrupted
21 Direct Memory Access (DMA) Permission for certain hardware systems to read and/or write independently of CPU Disk drive Graphics card Network card Sound card
22 How? Copies a block of memory from one device to another CPU initiates the transfer DMA Controller performs the transfer When transfer is complete it interrupts the CPU
23 Why DMA? Allows devices with different speeds to operate without causing huge CPU interrupt loads. If devices could not do I/O independently CPU would have to copy data from source to register and write it back CPU would be busy a LOT and unavailable for other tasks.
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