GR-MCC-C ProAsic3E Development Board
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1 GR-MCC-C ProAsicE Development Board AEROFLEX GAISLER AB Rev.., 0-0-
2 Information furnished by Aeroflex Gaisler AB is believed to be accurate and reliable. However, no responsibility is assumed by Aeroflex Gaisler AB for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Aeroflex Gaisler AB. Aeroflex Gaisler AB tel + 0 Kungsgatan fax + 0 Göteborg sales@gaisler.com Sweden Copyright 0 Aeroflex Gaisler All information is provided as is. There is no warranty that it is correct or suitable for any purpose, neither implicit nor explicit.
3 TABLE OF CONTENTS INTRODUCTION Overview... Actel ProASIC FPGAs... References... Handling... Abbreviations... INTERFACES AND CONFIGURATION List of Connectors... List of Oscillators... List of Switches... List of Jumpers... Note about pin Numbering of expansion connectors... List of Test Points... LIST OF TABLES Table -: List of Connectors... 0 Table -: J SPW-0 interface connections... Table -: J SPW- interface connections... Table -: J CANBUS interface connections... Table -: Ja GPIO Connector... Table -: Jb GPIO Connector... Table -: Ja Analog/Power Connector... Table -: Jb Analog/Power Connector... Table -: J POWER External Power Connector... Table -0: J FPGA JTAG Connector... Table -: Expansion connector J Pin-out... Table -: J PIO Header Pin out... Table -: Expansion connector J0 Pin-out... Table -: List and definition of Oscillators... Table -: List and definition of Switches... Table -: List and definition of PCB Jumpers... Table -: List of Test Points... LIST OF FIGURES Figure -: GR-MCC-C Development Board... Figure -: GR-MCC-C Block Diagram... Figure -: PCB Top View... Figure -: GR-MCC-C Assembly Photo - Top...0
4 REVISION HISTORY Revision Date Page 0.0 DRAFT All New document/draft All Text corrections to draft document All Revised for version.0 of GR-MCC-C Board , Clarified: Nominal input voltage to voltage regulators is V (range +V to +V DC), Description Changed GPIO/ in Table - and GPIO/ in Table - back to logic ordering, acc. Correction in rev. of PCB..a 0-0- Table - Corrected 0 pin to 0 pin RD- &. Added reference document and information on expansion connector pin numbering
5 INTRODUCTION. Overview This document describes the GR-MCC-C Development Board. The GR-MCC-C FPGA board has been created to support early development and fast prototyping of digital computer designs. The board incorporates a footprint for an Actel ProASICE or RT ProASICE field programmable gate array (or a corresponding socket), and is capable of operating stand-alone or in conjunction with other analogue boards. To provide more I/O possibilities, additional mezzanine and accessory boards are available. As the board is based on a programmable FPGA device, the actual functionality depends mainly on the logic which is designed and implemented in the FPGA device. Figure -: GR-MCC-C Development Board Features: Double-Euro style PCB (.mm x 0mm) form factor Actel ProASIC FPGA in FGG package (APE000-FGG) (optional socket for FPGA)
6 One bank of SRAM memory on-board, Mword x 0bits (nd bank as option, not normally fitted) One bank of Mbit (Mbyte x bit).v Flash PROM memory on board Dual LVDS transceivers (with opto-isolation) for dual SpaceWire interfaces Dual CAN transceivers (ISO, with opto-isolation) Quad bit ADC devices providing analogue input channels (of which input channels are dedicated for on-board supply, current and temperature monitoring) JTAG interface for programming and debug link On-board linear regulators supply for V,.V,.V generated from a nom. +V input Optional mezzanine connector compatible with existing GR Mezzanine boards Optional PIO expansion connector compatible with existing GR Accessory boards Power on reset, with optional reset button On-board MHz oscillator Suitable for Single Event Upset (SEU) testing LEON and LEONFT compatible FPGA template designs available ANALOG/POWER CONNECTIONS GPIO CONNECTIONS PIO CONNECTIONS x octal bit ADC POWER CIRCUITS APE000 FPGA SRAM BANK SRAM BANK 0 FLASH PROM JTAG/ DSU I/F OPTOCOUPLER OPTOCOUPLER OPTOCOUPLER CAN TRANSCEIVERS LVDS TRANSCEIVERS LVDS TRANSCEIVERS DUAL CAN I/F SPW I/F SPW I/F Figure -: GR-MCC-C Block Diagram The interface connectors on the front of the edge of the board provide: Dual CAN interface (MDMP connector) Two Spacewire interfaces (MDMS connectors) JTAG DSU interface (0 pin connector)
7 The interface connectors on the back of the edge of the board provide: 0 GPIO pins (on two x pin 0. standard headers) Analog connections (on two x pin 0. standard headers) ADC input channels ( bit ADC) Assorted power Connections.mm connector for external DC power supply (+V to +V DC, centre pin +ve). Actel ProASIC FPGAs The ProASIC low-cost, low-power FPGA family offers a breakthrough in power, price, performance, density, and features for today's most demanding high-volume applications. The ProASIC low-cost, low-power FPGAs are based on nonvolatile flash technology and support,000 to,000,000 gates and up to 0 high-performance I/Os. RT ProASIC FPGAs offer designers of space-flight hardware a radiation-tolerant (RT), reprogrammable, nonvolatile logic integration vehicle. Unlike all of Actel's other radiationtolerant, space-flight FPGAs, which use antifuse programming technology, devices in the RT ProASIC family use flash cells to store configuration information. Technical notes and further information can be found from the Actel website: References RD- GR-MCC-C_schematic.pdf, Schematic RD- GR-MCC-C_assy_drawing.pdf, Assembly Drawing RD- GR-MCC-C_bom.pdf, Bill of Materials RD- GR-MEZZ Technical Note, Technical Note about Mezzanine connectors. Handling ATTENTION : OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES This unit contains sensitive electronic components which can be damaged by Electrostatic Discharges (ESD). When handling or installing the unit observe appropriate precautions and ESD safe practices. When not in use, store the unit in an electrostatic protective container or bag. When configuring the jumpers on the board, or connecting/disconnecting cables, ensure that the unit is in an unpowered state.. Abbreviations ADC FPGA DIL Analog to Digital Converter Field Programmable Gate Array Dual In-Line
8 ESD FP FT GPIO I/O IP LVDS MII MUX PCB PROM SRAM CAN LVDS JTAG RT FT SEU SPW Electro-Static Discharge Front Panel Fault-Tolerant General Purpose Input / Output Input/Output Intellectual Property Low Voltage Digital Signalling Media Independent Interface Multiplexer Printed Circuit Board Programmable Read only Memory Static Random Access Memory Controller Area Network Low Voltage Digital Signalling Joint Test Action Group Radiation Tolerant Fault Single Event Upset Spacewire
9 INTERFACES AND CONFIGURATION. List of Connectors Function Type Description J SPW-0 MDM-S (female) LVDS connections for Spacewire Interface-0 J SPW- MDM-S (female) LVDS connections for Spacewire Interface- J CAN0/ MDMP (male) Dual CAN bus interface Ja GPIO xpin 0. header GPIO digital signals GPIO[..0] (0 signals) Jb GPIO xpin 0. header GPIO digital signals GPIO[..0] (0 signals) Ja ANALOG xpin 0. header ADC inputs ( signals) Jb ANALOG xpin 0. header Assorted ADC ( signals) and Power Connections J POWER-IN.mm center +ve DC power input connector J JTAG xpin 0. header JTAG programming & DSU interface J MEM I/O AMP - PIO/GPIO I/O connector ( signals) -0 pin 0.mm pitch J PIO x0pin 0. header PIO connections compatible with GR Accessories J0 GEN I/O AMP - GPIO I/O connector ( signals) 0 pin 0.mm pitch Table -: List of Connectors
10 0 Pin Comment DIN0+ Data In +ve DIN0- Data In -ve SIN0+ Strobe In +ve SIN0- Strobe In -ve SHIELD Inner Shield SOUT0+ Strobe Out +ve SOUT0- Strobe Out -ve DOUT0+ Data Out +ve DOUT0- Data Out -ve Table -: J SPW-0 interface connections Pin Comment DIN+ Data In +ve DIN- Data In -ve SIN+ Strobe In +ve SIN- Strobe In -ve SHIELD Inner Shield SOUT+ Strobe Out +ve SOUT- Strobe Out -ve DOUT+ Data Out +ve DOUT- Data Out -ve Table -: J SPW- interface connections Pin Comment CAN0_H CAN Dominant High (Interface 0) CAN0_L CAN Dominant Low (Interface 0) nc no connection GND Ground CANSHD Shield/Ground GND Ground nc no connection CAN_L CAN Dominant Low (Interface ) CAN_H CAN Dominant High (Interface ) Table -: J CANBUS interface connections
11 FUNCTION FPGA pin CONNECTOR PIN GPIO E0 GPIO E GPIO D GPIO D0 GPIO0 D GPIO D GPIO C0 GPIO C GPIO B GPIO B0 GPIO B GPIO B GPIO B GPIO A GPIO0 A FPGA pin FUNCTION E GPIO E GPIO 0 E GPIO D GPIO D GPIO 0 D GPIO C GPIO C GPIO C GPIO B GPIO0 B GPIO B GPIO 0 B GPIO A0 GPIO A GPIO 0 0 Table -: Ja GPIO Connector GPIO E GPIO D GPIO F GPIO C GPIO0 A GPIO B GPIO F GPIO E GPIO E GPIO A GPIO E GPIO G GPIO G GPIO F GPIO0 F E GPIO A GPIO 0 G GPIO C GPIO D GPIO 0 A GPIO G GPIO B GPIO H GPIO F GPIO0 G GPIO H GPIO 0 G0 GPIO F0 GPIO F GPIO 0 0 Table -: Jb GPIO Connector
12 FUNCTION FPGA pin CONNECTOR PIN FPGA pin FUNCTION ADC_ ADC_ ADC_ ADC_ 0 ADC_ ADC_ ADC_ ADC_0 ADC_ 0 ADC_ ADC_ ADC_ ADC_ 0 ADC_ ADC_ ADC_0 ADC_ ADC_ 0 ADC_ ADC_ ADC_ ADC_ ADC_ 0 ADC_0 Table -: Ja Analog/Power Connector V_COM V_COM GND_EXT V_EXT V_EXT V V V V V_EXT V_EXT V_EXT HEATER- HEATER- HEATER+ HEATER+ PT000-_ PT000-_ PT000-_0 ADC0_ ADC0_ ADC0_ V_COM GND_EXT GND_EXT V_EXT 0 V V V V 0 V_EXT V_EXT 0 V_EXT HEATER- HEATER- HEATER+ HEATER+ 0 PT000+_ PT000+_ PT000+_0 0 Table -: Jb Analog/Power Connector
13 Pin Comment +VE +VE Inner Pin, nom. +V, typically TBD A -VE GND Outer Pin Return Table -: J POWER External Power Connector Pin Comment TCK JTAG: TCK Ground TDO JTAG: TDO nc no connect TMS JTAG: TMS VREF.V VPUMP Programming Voltage TRSTN JTAG: TRSTN TDI JTAG: TDI Ground 0 Table -0: J FPGA JTAG Connector
14 FUNCTION FPGA pin CONNECTOR PIN 0 FPGA pin FUNCTION PIO T R PIO PIO V T0 PIO PIO0 U0 W0 PIO PIO V U PIO PIO U T PIO PIO R P PIO PIO P 0 P PIO PIO0 P 0 T 0 PIO 0 A 0 D GPIO GPIO F 0 G GPIO GPIO C 0 C GPIO GPIO0 A 0 D GPIO 0 0 GPIO GPIO A 0 0 B GPIO GPIO F 00 G GPIO GPIO B E GPIO GPIO E H GPIO GPIO0 F A GPIO GPIO E G GPIO GPIO H G GPIO GPIO G G0 GPIO 0 0 GPIO F0 F GPIO GPIO0 F F GPIO GPIO E0 E GPIO GPIO E E GPIO GPIO D E GPIO GPIO D D0 GPIO GPIO0 D 0 D GPIO GPIO D 0 D GPIO Table -: Expansion connector J Pin-out
15 FUNCTION FPGA pin CONNECTOR PIN PIO0 P PIO R PIO R PIO U PIO V PIO0 U0 PIO V PIO T FPGA pin FUNCTION T PIO P PIO P PIO T PIO 0 U PIO T0 PIO W0 PIO R PIO 0 Table -: J PIO Header Pin out FUNCTION FPGA pin CONNECTOR PIN FPGA pin FUNCTION E E GPIO GPIO0 A D GPIO GPIO D B GPIO GPIO B A GPIO GPIO A B GPIO GPIO A B GPIO GPIO0 B0 B GPIO GPIO C0 C GPIO 0 0 C C GPIO GPIO C B GPIO GPIO B0 B GPIO0 GPIO B B GPIO GPIO B B GPIO GPIO B B GPIO GPIO A A0 GPIO GPIO A A GPIO0 0 GPIO GPIO Table -: Expansion connector J0 Pin-out
16 . List of Oscillators Function Description X CLK_MAIN Main oscillator for FPGA (.0MHz) SMD oscillator soldered to board X CLK_USER pin DIL socket for User installed oscillator (.V DIL type) Table -: List and definition of Oscillators. List of Switches Function Description S RESET Push button RESET switch S DSUBREAK Push button DSUBREAK switch S PIO[..0] pole DIP SWITCH for GPIO signals [..0] S PIO[..] pole DIP SWITCH for GPIO signals [..] Table -: List and definition of Switches. List of Jumpers Function Type Description JP CONFIG x pin 0. Header Header to configure ground/power connections JP RESET pin 0. Header Header for external RESET switch JP DSU_BREAK pin 0. Header Header for external DSU_BREAK switch Table -: List and definition of PCB Jumpers (for details refer to schematic)
17 . Note about pin Numbering of expansion connectors To make it feasible for users to define peripherals connected to from the FPGA and to implement mezzanine boards, GPIO and PIO signals from the FPGA are connected to a 0 pin AMP connector (AMP --), J and 0 pin connector (AMP --), J0 on the board. Table - and Table - list these signals and the pin numbers for these connectors. Figure - shows the pin numbering scheme as implemented on the expansion connector. Figure -: Mezzanine Connector Pin Number Ordering Please note that this pin ordering does not match exactly the pin ordering which you will find on the Tyco part datasheets for the Mezzanine board mating connectors. The reason for this is explained in more detail in the Technical Note, RD-. Therefore please take care when designing your own mezzanine boards to take account of this pin ordering. If there is any confusion, or you have any doubts, please do not hesitate to contact info@pender.ch. Additional dimensional data or Gerber layout information can be provided, if required to aid in the layout of the User's mezzanine board.
18 . List of Test Points Comment TP V_COM V TP V_LVDS V TP V_CAN V TP V_Digital V TP V V TP VREF.V TP CLK_MAIN MHz,.V TP ROMRYBY Busy/Ready signal of Flash TP V.V TP0 V.V TP 0V TP 0V TP 0V TP 0V TP RESETn High (low during RESET) TP AUXRESETn High (low when S pressed) TP PRSTn High (low when S pressed) TP DSU_BREAK Low (high when S pressed) TP CLK_USER User Defined Oscillator Frequency Table -: List of Test Points
19 Figure -: PCB Top View
20 0
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