AMBA 3 AHB Lite Bus Architecture
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1 AMBA 3 AHB Lite Bus Architecture 1
2 Module Syllabus What is a Bus Bus Types ARM AMBA System Buses AMBA3 AHB-Lite Bus Bus Operation in General AHB Bus Components AHB Bus Signals AHB Bus Basic Timing AHB Bus Implementation Resources 2
3 Bus in General 3
4 What is Bus Traditionally, a bus is a communication system that allows data to be transferred between different components in a computer. The infrastructures is defined in both hardware and software : Hardware infrastructure includes the physical implementation, such as cables or wires. For example, the PCI uses PCI cable to connect components inside a desktop. Software infrastructure includes the bus protocol, e.g. PCI bus protocol. PCI socket on a mother board PCI bus cable 4
5 Bus Types Buses can be categorized into two types: External bus Used to connect external devices, such as a computer to a printer; Internal bus Used to connect internal components inside a computer, such as a CPU to a memory; Also known as system bus; Less overhead, e.g. not need for electrical characteristics handling and configuration detection etc.. Thus typically runs faster than the external bus; In a SoC design, the internal bus is integrated onto a single chip, thus can also be referred on-chip system bus. 5
6 ARM AMBA Buses 6
7 ARM AMBA System Bus AMBA: Advanced Microcontroller Bus Architecture AMBA protocol is an open standard (except AMBA-5), on-chip interconnect specification; Used as the on-chip bus in ARM-based SoC designs; Provides the interface standard that enables IP re-use; Facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals; Widely used in modern portable mobile devices, such as tablets and smartphones. 7
8 ARM AMBA Bus Families AMBA family Bus protocol Processor AMBA 5 CHI Cortex-A57, A53 AMBA 4 AMBA 3 ACE AXI4 AXI AHB (AHB-Lite) APB ATB Cortex-A7, A15 Cortex-A9, A8, R4, R5 Cortex-M0, M3, M4 Cortex-M0, M3, M4 AMBA 2 AHB, APB ARM7, ARM9 AMBA 1 ASB, APB As of Sept
9 AMBA3 AHB-Lite Bus AHB: Advanced High Performance Bus High-performance synthesizable designs; Supports multiple bus masters; Provides high-bandwidth operation; AHB-Lite: A subset of AHB; Simplifies the design of AHB bus, e.g. typically with a single master. 9
10 Bus Operation in General Processor controls all peripherals via an AHB-Lite system bus; The AHB-Lite bus consists of a data bus and an address bus, with additional control signals; Data bus is used to exchange data information; Address bus is used to select one of the peripherals (or one register of a peripheral); Control signals are used to synchronize and identify transactions, such as ready, write/ read, transfer mode signals. System on Chip Master (microprocessor) 32-bit Data bus Control signals 32-bit Address bus ARM AMBA 3 AHB-Lite System Bus Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave 6 10
11 Bus Operation in General A typical operation to access a peripheral mainly consists of: Processor Peripheral Select one peripheral (or one register) by giving the address to the address bus; At the same time, set control signals, such as read or write, transfer size and so forth; Wait for the peripheral to be ready, and then read the data from data bus. Address bus Select a peripheral Control bus Read operation, transfer size at the same time Data bus Send data back to processor Apart from above, AHB-Lite bus (or any other commercialized bus) has more functionalities, such as transfer size, burst mode, etc The following slides explain the components and signals used in AHB-Lite bus. However, to just perform a basic data transfer, not all the signals are needed. Control bus Set ready signal at the same time Processor reads the data and starts the next operation Address bus Select a peripheral 11
12 AMBA3 AHB-Lite Bus Components 12
13 AHB-Lite Bus Block Diagram CONTROL HWDATA [31:0] HADDR [31:0] Slave 1 Address Decoder HSEL_1 HSEL_2 HSEL_3 Slave 2 Master Multiplexor select Slave 3 HRDATA [31:0] RESPONSE Slave Multiplexor HRDATA_3 [31:0] RESPONSE_3 HRDATA_2 [31:0] RESPONSE_2 HRDATA_1 [31:0] RESPONSE_1 13
14 Global Signals Signal Direction Description HCLK clock source all components The bus clock times all bus transfers. All signal timings are related to the rising edge of HCLK HRESETn Reset controller all components The bus reset signal is active low and resets the system and the bus 14
15 AHB-Lite Master Interface The AHB-Lite master provides address and control information to initiate read and write operations. The master also receives the response from the slave, including data, ready and response signal. Transfer response Global signals HREADY HRESP HRESETn HCLK Master HWRITE HSIZE [1:0] HBURST [2:0] HPROT [3:0] HTRANS [1:0] HMASTLOCK CONTROL signals Data HRDATA [31:0] HADDR [31:0] HWDATA [31:0] Address Data 15
16 AHB-Lite Master Signals Signal Direction Description HADDR [31:0] HWDATA [31:0] HWRITE HSIZE [2:0] HBURST [2:0] HPROT [3:0] HTRANS [1:0] HMASTLOCK Master slaves and decoder Master slaves Master slaves Master slaves Master slaves Master slaves Master slaves Master slaves 32-bt system address bus The write data bus transfers data from the master to the slaves during write operations Indicates the transfer direction. When HIGH this signal indicates a write transfer and when LOW a read transfer. Indicates the size of the transfer, that is typically byte, halfword, or word The burst type indicates if the transfer is a single transfer or forms part of a burst The protection control signals provide additional information about a bus access and are primarily intended for use by any module that wants to implement some level of protection. Indicates the transfer type of the current transfer. This can be: IDLE, BUSY, NONSEQUENTIAL, or SEQUENTIAL. When HIGH, this signal indicates that the current transfer is part of a locked sequence. 16
17 AHB-Lite Slave Interface An AHB-Lite slave responds to transfer initiated by the master in the system. The signal HSELx is the output from the address decoder, which is used to select one of the slaves at one time. Select signal HSELx CONTROL signals HWRITE HSIZE [1:0] HBURST [2:0] HPROT [3:0] HTRANS [1:0] HMASTLOCK HREADY Slave x HREADYOUT HRESP HRDATA [31:0] Transfer response Data Address HADDR [31:0] Data HWDATA [31:0] Global signals HRESETn HCLK 17
18 AHB-Lite Slave Signals Signal Direction Description HRDATA [31:0] Slave multiplexor During read operations, the read data bus transfers data from the selected slave to the slave multiplexor. The multiplexor then transfers the data to the master. HREADYOUT Slave multiplexor When HIGH, the HREADYOUT signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer. HRESP Slave multiplexor The transfer response, after passing through the multiplexor, provides the master with additional information on the status of a transfer. When LOW, the HRESP signal indicates that the transfer status is OKAY. When HIGH, the HRESP signal indicates that the transfer status is ERROR. 18
19 Address Decoder and Slave Multiplexor Address decoder Selects one of the slaves depending on the current address bus; Also informs the slave multiplexor. Slave multiplexor Inputs the response signals (HRDATA, HREADY and HRESP) from all the slaves, and outputs one of them depending on the selecting signal from the address decoder. HADDR [31:0] Address Decoder Multiplexor select HSEL_1 HSEL_2 HRDATA_1 RESPONSE_3 HRDATA_2 RESPONSE_2 HRDATA_3 Slave Multiplexor HREADY HRESP HRDATA [31:0] HSEL_3 RESPONSE_1 19
20 Decoder and Multiplexor Signals Signal Direction Description HRDATA [31:0] HREADY Multiplexor master Multiplexor master and slaves The read data from the multiplexor to the master The ready signal from the multiplexor to the master When HIGH, the HREADY signal indicates to the master and all slaves, that the previous transfer is complete. HRESP Multiplexor master The transfer response signal from the multiplexor to the master HSELx Decoder slaves Each AHB-Lite slave has its own slave select signal HSELx and this signal indicates that the current transfer is intended for the selected slave. When the slave is initially selected, it must also monitor the status of HREADY to ensure that the previous bus transfer has completed, before it responds to the current transfer. 20
21 AHB-Lite Bus Timing 21
22 AHB-Lite Bus Timing An AHB-Lite transfer consists of two phases: Address phase Lasts for a single HCLK cycle unless its extended by the previous bus transfer; Data phase That might require several HCLK cycles. Use the HREADY signal to control the number of clock cycles required to complete the transfer. Pipelined transfer The data access of the current operation is overlapped with the address access of the next operation; Enables high performance operation while still providing adequate time for a slave to provide the response to a transfer. 22
23 AHB-Lite Bus Timing In our EDK teaching material, we only present the basic bus operation, namely: No BURST transaction; HBURST[2:0] is always 3 b000; Never generates locked transactions HMASTLOCK is always 1 b0; All transactions issued are non-sequential transfer HTRANS[1:0] is either 2 b00 (IDLE) or 2 b10 (Non Sequential) More advanced bus transaction can be found in the given reference1: AMBA 3 AHB-Lite Protocol Specification 23
24 Basic Read Transfer Address phase (first clock cycle) Give Address and control signals, clear HWRITE to zero; Data phase (second clock cycle) Data is available at HRDATA. No wait states (the slave is always ready to give its data); HCLK CONTROL Control 0 Control 1 Control 2 Control 3 HADDR [31:0] Address 0 Address 1 Address 2 Address 3 HRDATA [31:0] Read Data 0 Read Data 1 Read Data 2 HWRITE HREADY 24
25 Basic Write Transfer Address phase (first clock cycle) Give Address and control signals, set HWRITE to one; Data phase (second clock cycle) Give data to HWDATA. No wait states (the slave is always ready to receive the data); HCLK CONTROL Control 0 HADDR [31:0] Address 0 HWDATA [31:0] Write Data 0 HWRITE HREADY 25
26 Read Transfer with Wait State Address phase (first clock cycle) Give Address and control signals, set HWRITE to one; Data phase (multiple clock cycles) The slave holds HREADY to zero if its is not ready to provide its data; the master delays its next transaction; When the slave is ready, the data will be given at HRDATA; at the same time, HREADY is set to one. The master will then continue its next transaction. HCLK CONTROL Control 0 HADDR [31:0] Address 0 HRDATA [31:0] Data 0 HWRITE HREADY 26
27 Write Transfer with Wait State Address phase (first clock cycle) Give Address and control signals, clear HWRITE to zero; Data phase (multiple clock cycles) The master gives its data at HWDATA; the slave holds HREADY to zero if its is not ready to receive the data; the master delays its next transaction; When the slave is ready, it will receive the data and set HREADY to one. The master will then continue its next transaction. HCLK CONTROL Control 0 HADDR [31:0] Address 0 HWDATA [31:0] Data 0 HWRITE HREADY 27
28 Hardware Implementation Due to the pipelined operation, some signals have to be deliberately delayed including: The selecting signals from the decoder to the multiplexor is delayed for one clock cycle; The HREADY signal is delayed for one clock cycle before it is feedback to the multiplexor; The detailed implementation can be referred in the code that is provided in the EDK. Flip-flop HADDR [31:0] Address Decoder Multiplexor select HSEL_1 HSEL_2 HRDATA_1 RESPONSE_3 HRDATA_2 RESPONSE_2 HRDATA_3 Slave Multiplexor HREADY HRESP HRDATA [31:0] HSEL_3 RESPONSE_1 Flip-flop 28
29 Useful Resources Reference1 AMBA 3 AHB-Lite Protocol Specification topic=/com.arm.doc.ihi0033a/index.html 29
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