Interrupt/Timer/DMA 1
|
|
- Victoria Singleton
- 6 years ago
- Views:
Transcription
1 Interrupt/Timer/DMA 1
2 Exception An exception is any condition that needs to halt normal execution of the instructions Examples - Reset - HWI - SWI 2
3 Interrupt Hardware interrupt Software interrupt Trap 3
4 Hardware devices sources of interrupts Hardware sources can be internal or external of ongoing routine and thereby diversion to corresponding ISR The internal sources from devices differ in different process or microcontroller or devices and their version and their families External sources and ports also differ in different processors or microcontrollers 4
5 Interrupt sources Each of the interrupt sources demands a temporary transfer of control from the presently executed routine to the ISR corresponding to the source 5
6 Internal Hardware Device Sources Parallel port UART port (receive and transmit) ADC (start and end conversion) Real-time clock time-outs Watch dog timer reset Pulse Accumulator overflow 6
7 Keyboard interrupt Take about 10ms to send the code for a key and maximum 10 keys per second Interval between two successive keys are not fixed Interrupt driven mode, when a key is pressed 7
8 Example of keyboard interrupt 8
9 Printer Interrupt Maximum 300 characters can be printed in 1 second When does a print operation completes is not fixed Intervals between two successive print are not fixed Interrupt driven mode when a print action is completed 9
10 Example of printer interrupt 10
11 Interrupt type Maskable interrupt To execute timing critical interrupt Non-maskable interrupt 11
12 Interrupt driven data transfer 12
13 Flow chart for interrupt service 13
14 Interrupt in a typical microcontroller 14
15 Example of Interrupt table 15
16 Bus arbitration To service more than one device Priority arbiter Daisy chain arbiter 16
17 Priority arbiter 1. The processor is executing its program 2. Peripheral1 needs servicing so asserts Ireq1. Peripheral2 also needs servicing so assert Ireq2. 3. Priority arbiter sees at least one Ireq input asserted, so asserted Int. 4. Processor stops executing its program and stores its state. 5. Processor asserts Inta 6. Priority arbiter asserts Iack1 to acknowledge Perpheral1 7. Peripheral1 puts its interrupt address vector on the system bus 8. Processor jumps to the address of ISR read from data bus, ISR executes, and return 17
18 Priority arbiter 18
19 Daisy chain arbiter 1. The processor is executing its program 2. Any Peripheral needs servicing asserts Req out goes to the Req in of the subsequent device in the chain 3. Thus, the peripheral nearest to the processor asserts Int 4. The processor stops executing its program and stores its state 5. Processor asserts Inta the nearest device 6. The Inta passes through the chain till it finds a flag which is set by the device which has generated the interrupt. 7. The interrupting device sends the Interrupt Address Vector to the processor for its interrupt service routine 8. The processor jumps to the address of ISR read from data bus, ISR executes and returns. 9. The flag is reset 19
20 Daisy chain arbiter 20
21 Sources of Software Interrupt Software sources of interrupt are related to software detecting computation error or exceptional condition during execution or execute a software interrupt instruction (SWI) 21
22 Software interrupt Example Division by Zero by hardware Over-flow detection by hardware Under-flow detection by hardware Illegal opcode detection by hardware Software Interrupt instruction 22
23 Trap Special case of Software Interrupt Used for trapping some run-time error conditions (called throwing exceptions) and execute exception handlers on catching the exceptions Also used in debugger 23
24 Question? An Embedded System has three periodic devices Service time: how long it takes to run interrupt handler for each device Interrupt latency: maxim elapse time between an interrupt request and the start of interrupt handler routine If program P takes 100 seconds with interrupt disabled,how long will it takes with interrupt enabled, assuming no interrupt overlapped? 24
25 Solution Device 1 shall take (150+50)/800 = 0.25 Device 2 shall take (50+50)/1000 = 0.10 Device 3 shall take ( )/800 = 0.25 In one unit real time, it will take 0.6 unit time to service interrupt For a program with 100 seconds, it will take 250 seconds to finish the entire program with interrupt enabled 25
26 ARM Interrupt ARM has 7 modes of operation Switching between modes can be done by modifying CPSR register Most applications execute in user mode Non-user modes are entered to serve interrupts or exceptions 26
27 Modes of operation 27
28 Exceptions and modes Each exception causes ARM to enter to different modes 28
29 Vector Tables It is a table address of ARM core branches to when exception is raised and there is always branching instructions that direct the core to ISR 29
30 Exception Priority Newer ARM, Primask,Faultmask, and Basepri are used instead 30
31 Link Register Used to return the PC to the appropriate place in the interrupt task since this is not always the old PC value. It is modified depending on the type of execution. 31
32 Exception Handler Entering exception handler 1) Save the address of the next instruction in the appropriate LR 2) Save CPSR 3) Modify CPSR for the new mode 4) Fetch next instruction from the vector table Leaving exception handler 1) Return CPSR before calling the handler 2) Clear the interrupt disable flag (if set) 3) Move LR to the PC 32
33 Interrupts Assigning interrupts It is up to the system designer who can decide which HW peripheral can produce with interrupt Standard design: SWI are used to called privilege OS routines IRQ are designed to call general purpose interrupts FIQ is reserved for one single interrupt source that require fast response time 33
34 Interrupt latency It is the interval of time from an internal interrupt signal being raised to the first fetch of an instruction of ISR of the raised interrupt signal System architect tries to achieve two main goals: To handle multiple interrupt simultaneously To minimize the interrupt latency It can be done by 2 methods Allow nested interrupt handling Give priorities to different interrupt sources 34
35 Enable/Disable Interrupt This can be done by modifying CPSR using 4 ARM instructions: MRS to read CPSR MRS to store CPSR BIC Bit clear instruction ORR Or instruction 35
36 Interrupt Stack Stacks are needed extensively for context switching between different modes when interrupt are raised The design of stack depends on OS requirements Target hardware 36
37 Interrupt stack Two design decision are needed to be made Location Size 37
38 Non-nested Interrupt Handle Simple interrupt Handler Interrupt is disabled until the control is returned back to the interrupted task One interrupted can be served at a time Not suited for complex embedded system Scheme 38
39 Interrupt latency Device 1 : interrupt latency 50 s, ISR time 150 s Device 2 : interrupt latency 50 s, ISR time 50 s Device 3 : interrupt latency 100 s, ISR time 200 s What s the average interrupt latency if all interrupt happens at the same time? 39
40 Nested Interrupt Handler Handling more than one interrupt at a time Latency is improved System is more complex Normal interrupt can block critical interrupt 40
41 Nested Interrupt Handler Scheme Handler tests the flag that is updated by ISR Re-enabling interrupt requires switching out of current interrupt mode to either SVC or system mode Context switching involving emptying IRQ stack into reserved block 41
42 Interrupt latency Device 1 : interrupt latency 50 s, ISR time 150 s Device 2 : interrupt latency 50 s, ISR time 50 s Device 3 : interrupt latency 100 s, ISR time 200 s What s the average interrupt latency if all interrupt happens at the same time? 42
43 Prioritize Interrupt Handler Associate a priority level with a particular interrupt source Handling prioritization can be done either by software or hardware When an interrupt is raised, a fixed amount of comparison is done 43
44 Interrupt latency Device 1 : interrupt latency 50 s, ISR time 150 s Device 2 : interrupt latency 50 s, ISR time 50 s Device 3 : interrupt latency 100 s, ISR time 200 s What s the average interrupt latency if all interrupt happens at the same time? Assume that the shortest total latency time has the highest priority. 44
45 Other Schemes Re-entrant interrupt handler: re-enable interrupts earlier Priority standard interrupt handler: arranges priorities in a special way to decide which interrupt get higher priorities Prioritized group interrupt handler: group some interrupts into subset 45
46 Advantages/Drawback Non-Nested Interrupt handler Easy to implement and debug High interrupt latency Sequential service Not suitable for complex system Nested Interrupt handler Handle multiple interrupts No prioritization Medium interrupt latency Prioritize Interrupt handler Low latency Handle multiple interrupts Deterministic interrupt latency More complex Need time for priority comparison 46
47 Timer Timer is a device, which count the input at a regular interval T using clock pulse at its input The counts increment on each pulse and store in a register called count register 47
48 Evaluation of the time The count multiplies with the interval T gives the time The (present counts initial count ) * T gives the time interval between initial time and current time 48
49 Timer Has an input pin or a control bit in a control register for resetting the count bits Has an output pin or a status bit in a control register for the output value 49
50 Counter A device, which count the input due to the events at regular or irregular intervals The counts give the number of input events or pulses since it was last read. Has a register to enable read of present counts Functions as timer when counting regular interval clock pulses 50
51 Timer or Counter Interrupt When a timer or counter becomes 0x00 or 0x0000 after 0xFF or 0xFFFF(Maximum value), it can generate an Interrupt or output Time-Out signal or setting a status bit Timer Overflow (TOV) 51
52 Basic Hardware Timer 52
53 More complex timer 53
54 Timer with a terminal count 54
55 The timer count and its output 55
56 Block diagram of an Embedded System 56
57 Hardware Timer 57
58 Real-time clock Real-time clock ticks (System Heart Beats) Real-time clock is a clock which once the system starts, does not stop and can t be reset and its count value can t be reloaded Real-time clock is set for ticks using prescale bit in control register to control tick rate 58
59 Usage of a timer device To issue some service routing every some pre-set counter interval Count some special events within some timing interval Finding the time interval between two events Waiting for synchronization for other tasks such as from mutex, message queue 59
60 Usage of timer device Watchdog timer Bit-rate control for data communication Input-pulse counting for non-periodic inputs Context switch for multi-tasking OS Schedule tasks for RTOS Time division multiplexing (TDM) 60
61 Timer state 61
62 Timer state 62
63 Software Timer A software which executes and increases or decreases a count-variable on an interrupt from a system timer or from a real-time clock interrupt The software timer also generates interrupt on overflow of count-value or on finishing value of the count-variable 63
64 System clock An hardware-timing device is programmed to tick at constant intervals At each tick, there is an interrupt The interrupts are called system clock interrupts, when use to control the schedule and timings of the system 64
65 Software Timer (SWT) 65
66 SWT Actions are analogous to that of a hardware timer. While there is a physical limit of hardware timer, SWTs can be limited by the number of entry in the interrupt vector 66
67 Watchdog timer A timing device such that after preset time interval is set, an event must occur during the interval else the device will generate the timeout signal on failure If the event occurs, the watchdog timer is disabled Timeout may result in a service routine call, or even a processor reset 67
68 Example Assume that we anticipate that a set of tasks must finish in 100ms interval If the program finishes before 100ms, the watchdog timer is disabled and stopped If the program does not finish within 100ms, watchdog timers will generate an interrupt to reset the system 68
69 Watchdog timer application An application in mobile is that display is off in case that there is no user interaction takes place within watched time interval (e.g, 20 second) This can help save power of the mobile phone 69
70 Watchdog timer application An application in temperature control system: if the controller takes no action to switch off the boiler within preset watched time interval, a service routine is called to switch off the boiler Failure to switch off, may burst a boiler in which water is heated 70
71 Provision of watchdog timer A software interrupt can be programmed as a watchdog timer Microcontroller may provide hardware support for a watchdog timer 71
72 ARM SYSTICK Timer TICKINT to generate interrupt CLKSOURCE external or core clock COUNTFLAG timer history (1 means overflow) Reload value when timer reaches zero TENMS Calibration value for 10ms NoREF No external reference clock 72
73 Direct Memory Access (DMA) A DMA is required when multi-data set or burst of data or a block is to be transferred between the external device and system or two systems A device facilitates DMA transfer with a processor element and that device is called DMAC (DMA Controller) 73
74 Using a DMA controller DMA based method is useful when a block of bytes are transferred. E.g, disk to RAM or RAM to disk System performance improves by separate the processing of the transfer to the peripherals 74
75 An example of DMA architecture 75
76 DMA controller architecture 76
77 DMAC hold request After an ISR from CPU initializes and programs DMAC, the DMAC sends the hold request to the CPU CPU acknowledges and gives the control of the bus to DMAC 77
78 Three modes of data transfer Single transfer at a time and then release the control of the system bus Burst transfer at a time and then release the control of the system bus, a burst can be a few kb Bulk transfer and the release the control of the system bus after the transfer is complete 78
79 CPU and DMAC interaction At the start for DMAC programming and initializing At the end to return control back to CPU ISRs of the CPU is called only at the beginning and at the end of DMA transfer 79
80 Programming the DMAC registers The ISR from CPU will program the DMA registers for : Transfer command Data count Memory block address I/O bus address 80
81 Multiple channels DMAC Provides DMA action from system with two I/O devices or more Separate set of registers for programming each channels Separate interrupt signals in the case of multi-channel DMAC 81
82 Question? 82
83 Fly-by DMA transfer Single cycle, single address transfer Efficient data transfer First a device or CPU issues DMA request DMAC gains control of the bus from CPU DMAC sends acknowledge back to the device 83
84 Fly-by DMA transfer 84
85 Fetch-and-Deposit transfer Dual-cycle, dual address, flow-through Involves two memories or I/O cycles Data first transfer from I/O into a temporary register inside DMAC The data is written to memory or I/O in the next cycle Inefficient, but useful for interfacing devices with different bus sizes, e.g., read two 16 bits read and write one 32-bit data 85
86 Fetch-and-deposit DMA transfer 86
Module 3. Embedded Systems I/O. Version 2 EE IIT, Kharagpur 1
Module 3 Embedded Systems I/O Version 2 EE IIT, Kharagpur 1 Lesson 15 Interrupts Version 2 EE IIT, Kharagpur 2 Instructional Objectives After going through this lesson the student would learn Interrupts
More informationEEL 4744C: Microprocessor Applications. Lecture 7. Part 1. Interrupt. Dr. Tao Li 1
EEL 4744C: Microprocessor Applications Lecture 7 Part 1 Interrupt Dr. Tao Li 1 M&M: Chapter 8 Or Reading Assignment Software and Hardware Engineering (new version): Chapter 12 Dr. Tao Li 2 Interrupt An
More informationReading Assignment. Interrupt. Interrupt. Interrupt. EEL 4744C: Microprocessor Applications. Lecture 7. Part 1
Reading Assignment EEL 4744C: Microprocessor Applications Lecture 7 M&M: Chapter 8 Or Software and Hardware Engineering (new version): Chapter 12 Part 1 Interrupt Dr. Tao Li 1 Dr. Tao Li 2 Interrupt An
More informationHercules ARM Cortex -R4 System Architecture. Processor Overview
Hercules ARM Cortex -R4 System Architecture Processor Overview What is Hercules? TI s 32-bit ARM Cortex -R4/R5 MCU family for Industrial, Automotive, and Transportation Safety Hardware Safety Features
More informationMicroprocessors & Interfacing
Lecture Overview Microprocessors & Interfacing Interrupts (I) Lecturer : Dr. Annie Guo Introduction to Interrupts Interrupt system specifications Multiple sources of interrupts Interrupt priorities Interrupts
More informationInterrupts (I) Lecturer: Sri Notes by Annie Guo. Week8 1
Interrupts (I) Lecturer: Sri Notes by Annie Guo Week8 1 Lecture overview Introduction to Interrupts Interrupt system specifications Multiple Sources of Interrupts Interrupt Priorities Interrupts in AVR
More informationCourse Introduction. Purpose: Objectives: Content: 27 pages 4 questions. Learning Time: 20 minutes
Course Introduction Purpose: This course provides an overview of the Direct Memory Access Controller and the Interrupt Controller on the SH-2 and SH-2A families of 32-bit RISC microcontrollers, which are
More informationChapter 4. Enhancing ARM7 architecture by embedding RTOS
Chapter 4 Enhancing ARM7 architecture by embedding RTOS 4.1 ARM7 architecture 4.2 ARM7TDMI processor core 4.3 Embedding RTOS on ARM7TDMI architecture 4.4 Block diagram of the Design 4.5 Hardware Design
More informationDesign and Implementation Interrupt Mechanism
Design and Implementation Interrupt Mechanism 1 Module Overview Study processor interruption; Design and implement of an interrupt mechanism which responds to interrupts from timer and UART; Program interrupt
More informationThe control of I/O devices is a major concern for OS designers
Lecture Overview I/O devices I/O hardware Interrupts Direct memory access Device dimensions Device drivers Kernel I/O subsystem Operating Systems - June 26, 2001 I/O Device Issues The control of I/O devices
More informationComputer System Overview
Computer System Overview Operating Systems 2005/S2 1 What are the objectives of an Operating System? 2 What are the objectives of an Operating System? convenience & abstraction the OS should facilitate
More informationECE 372 Microcontroller Design Parallel IO Ports - Interrupts. ECE 372 Microcontroller Design Parallel IO Ports - Interrupts
Interrupts An interrupt can be compared with a phone call interrupting your task which you will resume when the call is finished You can mask an interrupt just as you can decide not to answer any phone
More informationQuestion Bank Microprocessor and Microcontroller
QUESTION BANK - 2 PART A 1. What is cycle stealing? (K1-CO3) During any given bus cycle, one of the system components connected to the system bus is given control of the bus. This component is said to
More informationComputer System Overview OPERATING SYSTEM TOP-LEVEL COMPONENTS. Simplified view: Operating Systems. Slide 1. Slide /S2. Slide 2.
BASIC ELEMENTS Simplified view: Processor Slide 1 Computer System Overview Operating Systems Slide 3 Main Memory referred to as real memory or primary memory volatile modules 2004/S2 secondary memory devices
More information18-349: Introduction to Embedded Real-Time Systems
18-349: Introduction to Embedded Real-Time Systems Embedded Real-Time Systems Lecture 6: Timers and Interrupts Anthony Rowe Electrical and Computer Engineering Carnegie Mellon University Embedded Real-Time
More informationInterrupts (Exceptions) (From LM3S1968) Gary J. Minden August 29, 2016
Interrupts (Exceptions) (From LM3S1968) Gary J. Minden August 29, 2016 1 Interrupts Motivation Implementation Material from Stellaris LM3S1968 Micro-controller Datasheet Sections 2.5 and 2.6 2 Motivation
More informationChapter 7 Central Processor Unit (S08CPUV2)
Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more
More informationINPUT/OUTPUT ORGANIZATION
INPUT/OUTPUT ORGANIZATION Accessing I/O Devices I/O interface Input/output mechanism Memory-mapped I/O Programmed I/O Interrupts Direct Memory Access Buses Synchronous Bus Asynchronous Bus I/O in CO and
More informationINPUT/OUTPUT ORGANIZATION
INPUT/OUTPUT ORGANIZATION Accessing I/O Devices I/O interface Input/output mechanism Memory-mapped I/O Programmed I/O Interrupts Direct Memory Access Buses Synchronous Bus Asynchronous Bus I/O in CO and
More informationInput Output (IO) Management
Input Output (IO) Management Prof. P.C.P. Bhatt P.C.P Bhatt OS/M5/V1/2004 1 Introduction Humans interact with machines by providing information through IO devices. Manyon-line services are availed through
More informationLecture 10 Exceptions and Interrupts. How are exceptions generated?
Lecture 10 Exceptions and Interrupts The ARM processor can work in one of many operating modes. So far we have only considered user mode, which is the "normal" mode of operation. The processor can also
More informationChapter 2. Overview of Architecture and Microcontroller-Resources
Chapter 2 Overview of Architecture and Microcontroller-Resources Lesson 4 Timers, Real Time Clock Interrupts and Watchdog Timer 2 Microcontroller-resources Port P1 Port P0 Port P2 PWM Timers Internal Program
More informationInterrupts (Exceptions) Gary J. Minden September 11, 2014
Interrupts (Exceptions) Gary J. Minden September 11, 2014 1 Interrupts Motivation Implementation Material from Stellaris LM3S1968 Micro-controller Datasheet Sections 2.5 and 2.6 2 Motivation Our current
More informationProgramming Embedded Systems
Programming Embedded Systems Lecture 5 Interrupts, modes of multi-tasking Wednesday Feb 1, 2012 Philipp Rümmer Uppsala University Philipp.Ruemmer@it.uu.se 1/31 Lecture outline Interrupts Internal, external,
More informationARM Cortex core microcontrollers
ARM Cortex core microcontrollers 2 nd Cortex-M3 core Balázs Scherer Budapest University of Technology and Economics Department of Measurement and Information Systems BME-MIT 2016 The Cortex-M3 core BME-MIT
More informationChapter 3. Top Level View of Computer Function and Interconnection. Yonsei University
Chapter 3 Top Level View of Computer Function and Interconnection Contents Computer Components Computer Function Interconnection Structures Bus Interconnection PCI 3-2 Program Concept Computer components
More informationInterrupts in Zynq Systems
Interrupts in Zynq Systems C r i s t i a n S i s t e r n a U n i v e r s i d a d N a c i o n a l d e S a n J u a n A r g e n t i n a Exception / Interrupt Special condition that requires a processor's
More informationMACHINE CONTROL INSTRUCTIONS: 1. EI
Lecture-33 MACHINE CONTROL INSTRUCTIONS: 1. EI (Enable interrupts): The interrupt system is disabled just after RESET operation. There is an internal INTE F/F (Interrupt enable flipflop) which is reset
More information2. List the five interrupt pins available in INTR, TRAP, RST 7.5, RST 6.5, RST 5.5.
DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EE6502- MICROPROCESSORS AND MICROCONTROLLERS UNIT I: 8085 PROCESSOR PART A 1. What is the need for ALE signal in
More informationMobile Operating Systems Lesson 01 Operating System
Mobile Operating Systems Lesson 01 Operating System Oxford University Press 2007. All rights reserved. 1 Operating system (OS) The master control program Manages all software and hardware resources Controls,
More informationHANDLING MULTIPLE DEVICES
HANDLING MULTIPLE DEVICES Let us now consider the situation where a number of devices capable of initiating interrupts are connected to the processor. Because these devices are operationally independent,
More informationMigrating to Cortex-M3 Microcontrollers: an RTOS Perspective
Migrating to Cortex-M3 Microcontrollers: an RTOS Perspective Microcontroller devices based on the ARM Cortex -M3 processor specifically target real-time applications that run several tasks in parallel.
More information1 MALP ( ) Unit-1. (1) Draw and explain the internal architecture of 8085.
(1) Draw and explain the internal architecture of 8085. The architecture of 8085 Microprocessor is shown in figure given below. The internal architecture of 8085 includes following section ALU-Arithmetic
More informationUnit 3 and Unit 4: Chapter 4 INPUT/OUTPUT ORGANIZATION
Unit 3 and Unit 4: Chapter 4 INPUT/OUTPUT ORGANIZATION Introduction A general purpose computer should have the ability to exchange information with a wide range of devices in varying environments. Computers
More informationINTERRUPTS in microprocessor systems
INTERRUPTS in microprocessor systems Microcontroller Power Supply clock fx (Central Proccesor Unit) CPU Reset Hardware Interrupts system IRQ Internal address bus Internal data bus Internal control bus
More informationOutline. Operating Systems: Devices and I/O p. 1/18
Outline Diversity of I/O devices block and character devices Organization of I/O subsystem of kernel device drivers Common hardware characteristics of device I/O subsystem tasks Operating Systems: Devices
More informationExceptions and Interrupts ARM Cortex M3
Exceptions and Interrupts ARM Cortex M3 ผศ.ดร. ส ร นทร ก ตต ธรก ล และ อ.สรย ทธ กลมกล อม 1 Introduction! Exception are events! They occur during the execution of the program! ARM exceptions! Exceptions
More informationARM Processors for Embedded Applications
ARM Processors for Embedded Applications Roadmap for ARM Processors ARM Architecture Basics ARM Families AMBA Architecture 1 Current ARM Core Families ARM7: Hard cores and Soft cores Cache with MPU or
More informationGrundlagen Microcontroller Interrupts. Günther Gridling Bettina Weiss
Grundlagen Microcontroller Interrupts Günther Gridling Bettina Weiss 1 Interrupts Lecture Overview Definition Sources ISR Priorities & Nesting 2 Definition Interrupt: reaction to (asynchronous) external
More informationCMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 09, SPRING 2013
CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 09, SPRING 2013 TOPICS TODAY I/O Architectures Interrupts Exceptions FETCH EXECUTE CYCLE 1.7 The von Neumann Model This is a general
More informationby I.-C. Lin, Dept. CS, NCTU. Textbook: Operating System Concepts 8ed CHAPTER 13: I/O SYSTEMS
by I.-C. Lin, Dept. CS, NCTU. Textbook: Operating System Concepts 8ed CHAPTER 13: I/O SYSTEMS Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests
More informationModule Introduction. PURPOSE: The intent of this module is to explain MCU processing of reset and interrupt exception events.
Module Introduction PURPOSE: The intent of this module is to explain MCU processing of reset and interrupt exception events. OBJECTIVES: - Describe the difference between resets and interrupts. - Identify
More informationUNIT- 5. Chapter 12 Processor Structure and Function
UNIT- 5 Chapter 12 Processor Structure and Function CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data CPU With Systems Bus CPU Internal Structure Registers
More informationEE458 - Embedded Systems Exceptions and Interrupts
EE458 - Embedded Systems Exceptions and Interrupts Outline Exceptions Interrupts References RTC: Chapters 10 CUG: Chapters 8, 21, 23 1 Introduction An exception is any event that disrupts the normal execution
More information8086 Interrupts and Interrupt Responses:
UNIT-III PART -A INTERRUPTS AND PROGRAMMABLE INTERRUPT CONTROLLERS Contents at a glance: 8086 Interrupts and Interrupt Responses Introduction to DOS and BIOS interrupts 8259A Priority Interrupt Controller
More informationProgrammed I/O Interrupt-Driven I/O Direct Memory Access (DMA) I/O Processors. 10/12/2017 Input/Output Systems and Peripheral Devices (02-2)
Programmed I/O Interrupt-Driven I/O Direct Memory Access (DMA) I/O Processors 1 Principle of Interrupt-Driven I/O Multiple-Interrupt Systems Priority Interrupt Systems Parallel Priority Interrupts Daisy-Chain
More informationTypes of Interrupts:
Interrupt structure Introduction Interrupt is signals send by an external device to the processor, to request the processor to perform a particular task or work. Mainly in the microprocessor based system
More informationECE 485/585 Microprocessor System Design
Microprocessor System Design Lecture 3: Polling and Interrupts Programmed I/O and DMA Interrupts Zeshan Chishti Electrical and Computer Engineering Dept Maseeh College of Engineering and Computer Science
More informationOctober, Saeid Nooshabadi. Overview COMP 3221
Overview COMP 3221 Microprocessors and Embedded Systems Lectures 28: Exceptions & Interrupts - II http://www.cse.unsw.edu.au/~cs3221 Instruction Set Support for Exceptions Role of O/S in Handling Exceptions
More information6 Direct Memory Access (DMA)
1 License: http://creativecommons.org/licenses/by-nc-nd/3.0/ 6 Direct Access (DMA) DMA technique is used to transfer large volumes of data between I/O interfaces and the memory. Example: Disk drive controllers,
More informationPin Description, Status & Control Signals of 8085 Microprocessor
Pin Description, Status & Control Signals of 8085 Microprocessor 1 Intel 8085 CPU Block Diagram 2 The 8085 Block Diagram Registers hold temporary data. Instruction register (IR) holds the currently executing
More informationM68HC08 Microcontroller The MC68HC908GP32. General Description. MCU Block Diagram CPU08 1
M68HC08 Microcontroller The MC68HC908GP32 Babak Kia Adjunct Professor Boston University College of Engineering Email: bkia -at- bu.edu ENG SC757 - Advanced Microprocessor Design General Description The
More informationReset, Interrupts, Exceptions, and Break ECE 3534
Reset, Interrupts, Exceptions, and Break ECE 3534 1 Reset, Interrupts, Exceptions, Break These topics are closely related Both software and hardware aspects of a processor are involved On the MicroBlaze,
More informationARM Advanced Interrupt Controller
ARM Advanced Interrupt Controller Considering AT91SAM7X256 Device Microcontrollers and Course Isfahan University of Technology Dec 2010 1 Advanced Interrupt Controller (AIC) AIC used in ATMEL device Not
More informationMicroprocessor Architecture
Microprocessor - 8085 Architecture 8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. It has the following configuration
More informationCOSC 243. Input / Output. Lecture 13 Input/Output. COSC 243 (Computer Architecture)
COSC 243 Input / Output 1 Introduction This Lecture Source: Chapter 7 (10 th edition) Next Lecture (until end of semester) Zhiyi Huang on Operating Systems 2 Memory RAM Random Access Memory Read / write
More informationCPUs. Input and output. Supervisor mode, exceptions, traps. Co-processors. Computers as Components 4e 2016 Marilyn Wolf
CPUs Input and output. Supervisor mode, exceptions, traps. Co-processors. I/O devices Usually includes some non-digital component. Typical digital interface to CPU: CPU status reg data reg mechanism Application:
More informationInput/Output Problems. External Devices. Input/Output Module. I/O Steps. I/O Module Function Computer Architecture
168 420 Computer Architecture Chapter 6 Input/Output Input/Output Problems Wide variety of peripherals Delivering different amounts of data At different speeds In different formats All slower than CPU
More informationThese three counters can be programmed for either binary or BCD count.
S5 KTU 1 PROGRAMMABLE TIMER 8254/8253 The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors to perform timing and counting functions using three 16-bit registers.
More informationEEL 4744C: Microprocessor Applications. Lecture 7. Part 2. M68HC12 Interrupt. Dr. Tao Li 1
EEL 4744C: Microprocessor Applications Lecture 7 Part 2 M68HC12 Interrupt Dr. Tao Li 1 Reading Assignment Software and Hardware Engineering (New version): Chapter 12 or SHE (old version) Chapter 8 And
More informationFIFTH SEMESTER DIPLOMA EXAMINATION IN ENGINEERING/ TECHNOLOGY-MARCH 2014 EMBEDDED SYSTEMS (Common for CT,CM) [Time: 3 hours] (Maximum marks : 100)
(Revision-10) FIFTH SEMESTER DIPLOMA EXAMINATION IN ENGINEERING/ TECHNOLOGY-MARCH 2014 EMBEDDED SYSTEMS (Common for CT,CM) [Time: 3 hours] (Maximum marks : 100) PART-A (Maximum marks : 10) I. Answer all
More informationInput/Output Systems
Input/Output Systems CSCI 315 Operating Systems Design Department of Computer Science Notice: The slides for this lecture have been largely based on those from an earlier edition of the course text Operating
More informationS.R.M. INSTITUTE OF SCIENCE & TECHNOLOGY SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING
S.R.M. INSTITUTE OF SCIENCE & TECHNOLOGY SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING QUESTION BANK Subject Code : EC307 Subject Name : Microprocessor and Interfacing Year & Sem : III Year, V Sem
More informationInput / Output. School of Computer Science G51CSA
Input / Output 1 Overview J I/O module is the third key element of a computer system. (others are CPU and Memory) J All computer systems must have efficient means to receive input and deliver output J
More informationUnit 1. Chapter 3 Top Level View of Computer Function and Interconnection
Unit 1 Chapter 3 Top Level View of Computer Function and Interconnection Program Concept Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signals
More informationChapter 13: I/O Systems
Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests to Hardware Operations Streams Performance Objectives Explore the structure of an operating
More information9/25/ Software & Hardware Architecture
8086 Software & Hardware Architecture 1 INTRODUCTION It is a multipurpose programmable clock drive register based integrated electronic device, that reads binary instructions from a storage device called
More informationAVR XMEGA Product Line Introduction AVR XMEGA TM. Product Introduction.
AVR XMEGA TM Product Introduction 32-bit AVR UC3 AVR Flash Microcontrollers The highest performance AVR in the world 8/16-bit AVR XMEGA Peripheral Performance 8-bit megaavr The world s most successful
More informationCOEN-4720 Embedded Systems Design Lecture 4 Interrupts (Part 1) Cristinel Ababei Dept. of Electrical and Computer Engineering Marquette University
COEN-4720 Embedded Systems Design Lecture 4 Interrupts (Part 1) Cristinel Ababei Dept. of Electrical and Computer Engineering Marquette University Outline Introduction NVIC and Interrupt Control Interrupt
More informationSECTION 5 RESETS AND INTERRUPTS
SECTION RESETS AND INTERRUPTS Resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched. A reset immediately stops execution
More informationCISC RISC. Compiler. Compiler. Processor. Processor
Q1. Explain briefly the RISC design philosophy. Answer: RISC is a design philosophy aimed at delivering simple but powerful instructions that execute within a single cycle at a high clock speed. The RISC
More informationMicroprocessors/Microcontrollers
Microprocessors/Microcontrollers A central processing unit (CPU) fabricated on one or more chips, containing the basic arithmetic, logic, and control elements of a computer that are required for processing
More informationI/O - input/output. system components: CPU, memory, and bus -- now add I/O controllers and peripheral devices. CPU Cache
I/O - input/output system components: CPU, memory, and bus -- now add I/O controllers and peripheral devices CPU Cache CPU must perform all transfers to/from simple controller, e.g., CPU reads byte from
More informationFundamental concept in computation Interrupt execution of a program to handle an event
Interrupts Fundamental concept in computation Interrupt execution of a program to handle an event Don t have to rely on program relinquishing control Can code program without worrying about others Issues
More informationPC Interrupt Structure and 8259 DMA Controllers
ELEC 379 : DESIGN OF DIGITAL AND MICROCOMPUTER SYSTEMS 1998/99 WINTER SESSION, TERM 2 PC Interrupt Structure and 8259 DMA Controllers This lecture covers the use of interrupts and the vectored interrupt
More informationNorthern India Engineering College, Delhi (GGSIP University) PAPER I
PAPER I Q1.Explain IVT? ANS. interrupt vector table is a memory space for storing starting addresses of all the interrupt service routine. It stores CS:IP PAIR corresponding to each ISR. An interrupt vector
More informationInterrupt-Driven Input/Output
Interrupt-Driven Input/Output Textbook: Chapter 11 (Interrupts) ARM Cortex-M4 User Guide (Interrupts, exceptions, NVIC) Sections 2.1.4, 2.3 Exceptions and interrupts Section 4.2 Nested Vectored Interrupt
More informationEN1640: Design of Computing Systems Topic 07: I/O
EN1640: Design of Computing Systems Topic 07: I/O Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown University Spring 2017 [ material
More informationARM Embedded Systems: ARM Design philosophy, Embedded System Hardware, Embedded System Software
Department of Technical Education DIPLOMA COURSE IN ELECTRONICS AND COMMUNICATION ENGINEERING Sixth Semester ARM MICROCONTROLLER Contact Hours/Week : 04 Contact Hours/Semester : 64 CONTENTS Unit-I No.
More informationARM Interrupts. EE383: Introduction to Embedded Systems University of Kentucky. James E. Lumpp
ARM Interrupts EE383: Introduction to Embedded Systems University of Kentucky James E. Lumpp Includes material from: - Jonathan Valvano, Introduction to ARM Cortex-M Microcontrollers, Volume 1 Ebook, EE
More informationFredrick M. Cady. Assembly and С Programming forthefreescalehcs12 Microcontroller. шт.
SECOND шт. Assembly and С Programming forthefreescalehcs12 Microcontroller Fredrick M. Cady Department of Electrical and Computer Engineering Montana State University New York Oxford Oxford University
More informationInstruction Set Architecture of MIPS Processor
CSE 3421/5421: Introduction to Computer Architecture Instruction Set Architecture of MIPS Processor Presentation B Study: 2.1 2.3, 2.4 2.7, 2.10 and Handout MIPS Instructions: 32-bit Core Subset Read:
More informationOverview of Microcontroller and Embedded Systems
UNIT-III Overview of Microcontroller and Embedded Systems Embedded Hardware and Various Building Blocks: The basic hardware components of an embedded system shown in a block diagram in below figure. These
More informationInput/Output Programming
Input/Output Programming Chapter 3: Section 3.1, 3.2 Input and output (I/O) programming Communicating with I/O devices Busy-wait I/O Interrupt-driven I/O I/O devices Devices may include digital and non-digital
More informationInterconnects, Memory, GPIO
Interconnects, Memory, GPIO Dr. Francesco Conti f.conti@unibo.it Slide contributions adapted from STMicroelectronics and from Dr. Michele Magno, others Processor vs. MCU Pipeline Harvard architecture Separate
More informationGeneric Model of I/O Module Interface to CPU and Memory Interface to one or more peripherals
William Stallings Computer Organization and Architecture 7 th Edition Chapter 7 Input/Output Input/Output Problems Wide variety of peripherals Delivering different amounts of data At different speeds In
More informationEC2304-MICROPROCESSOR AND MICROCONROLLERS 2 marks questions and answers UNIT-I
EC2304-MICROPROCESSOR AND MICROCONROLLERS 2 marks questions and answers 1. Define microprocessors? UNIT-I A semiconductor device(integrated circuit) manufactured by using the LSI technique. It includes
More informationWilliam Stallings Computer Organization and Architecture 10 th Edition Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+ William Stallings Computer Organization and Architecture 10 th Edition 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. 2 + Chapter 3 A Top-Level View of Computer Function and Interconnection
More informationARM Cortex-M and RTOSs Are Meant for Each Other
ARM Cortex-M and RTOSs Are Meant for Each Other FEBRUARY 2018 JEAN J. LABROSSE Introduction Author µc/os series of software and books Numerous articles and blogs Lecturer Conferences Training Entrepreneur
More informationChapter 13: I/O Systems
Chapter 13: I/O Systems Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests to Hardware Operations Streams Performance 13.2 Silberschatz, Galvin
More informationChapter 13: I/O Systems. Chapter 13: I/O Systems. Objectives. I/O Hardware. A Typical PC Bus Structure. Device I/O Port Locations on PCs (partial)
Chapter 13: I/O Systems Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests to Hardware Operations Streams Performance 13.2 Silberschatz, Galvin
More informationComputer and Hardware Architecture I. Benny Thörnberg Associate Professor in Electronics
Computer and Hardware Architecture I Benny Thörnberg Associate Professor in Electronics Hardware architecture Computer architecture The functionality of a modern computer is so complex that no human can
More informationWilliam Stallings Computer Organization and Architecture 8 th Edition. Chapter 12 Processor Structure and Function
William Stallings Computer Organization and Architecture 8 th Edition Chapter 12 Processor Structure and Function CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data
More informationUnit DMA CONTROLLER 8257
DMA CONTROLLER 8257 In microprocessor based system, data transfer can be controlled by either software or hardware. To transfer data microprocessor has to do the following tasks: Fetch the instruction
More informationHardware OS & OS- Application interface
CS 4410 Operating Systems Hardware OS & OS- Application interface Summer 2013 Cornell University 1 Today How my device becomes useful for the user? HW-OS interface Device controller Device driver Interrupts
More informationThe Purpose of Interrupt
Interrupts 3 Introduction In this chapter, the coverage of basic I/O and programmable peripheral interfaces is expanded by examining a technique called interrupt-processed I/O. An interrupt is a hardware-initiated
More informationToday: Computer System Overview (Stallings, chapter ) Next: Operating System Overview (Stallings, chapter ,
Lecture Topics Today: Computer System Overview (Stallings, chapter 1.1-1.8) Next: Operating System Overview (Stallings, chapter 2.1-2.4, 2.8-2.10) 1 Announcements Syllabus and calendar available Consulting
More informationMICROPROCESSOR MICROPROCESSOR. From the above description, we can draw the following block diagram to represent a microprocessor based system: Output
8085 SATISH CHANDRA What is a Microprocessor? The word comes from the combination micro and processor. Processor means a device that processes whatever. In this context, processor means a device that processes
More informationComputer Organization ECE514. Chapter 5 Input/Output (9hrs)
Computer Organization ECE514 Chapter 5 Input/Output (9hrs) Learning Outcomes Course Outcome (CO) - CO2 Describe the architecture and organization of computer systems Program Outcome (PO) PO1 Apply knowledge
More informationControl Unit: The control unit provides the necessary timing and control Microprocessor resembles a CPU exactly.
Unit I 8085 and 8086 PROCESSOR Introduction to microprocessor A microprocessor is a clock-driven semiconductor device consisting of electronic logic circuits manufactured by using either a large-scale
More information