MICROPROCESSOR TECHNOLOGY

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1 MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 15 Ch.7 The and Microprocessors 21-Apr-15 1

2 Chapter Objectives Contrast the and microprocessors with earlier Intel microprocessors. Describe the operation of the and memory management unit and paging unit. Define additional 80386/80486 instructions and addressing modes. Detail the interrupt structure and direct memory access structure of 80386/80486 µp. Contrast the with the µp. 21-Apr-15 2

3 M / IO The Microprocessor The 80386DX µp is packaged in a 132-pin PGA. It addresses 4GB of memory through 32-bit data bus and 32-bit address. The 80386SX is a popular and a less costly version of the µp with 24 bit address bus and 16 bit data bus. It is used in PCs that use the same basic motherboard design like and require less than 16 MB of memory. 21-Apr-15 3

4 The Microprocessor The requires a single +5V power supply. The power supply current averages 550 ma for the 25 MHz version, 500 ma for the 20 MHz version, and 450 ma for the 16 MHz version. The 33 MHz version requires 600 ma. Each output pin is capable of providing 4 ma (address and data connections) or 5 ma (other connections). 21-Apr-15 4

5 80386DX Pin Functions A2 A31: Address bus connections address any of the 1G memory locations found in the µp system. (A0 and A1 are encoded) D0 D31: Data bus connections BE0 BE3: Bank Enable signals select the access of a byte, word, or double word of data. These signals are generated internally from address bits A0 and A1. M/IO: select memory device when a logic 1. During I/O operation, the address bus contains a 16 bit I/O address 21-Apr-15 5

6 80386DX Pin Functions W/R: Write/Read indicate that the current bus cycle is write when a logic 1. ADS: Address Data Strobe becomes active when the has issued a valid I/O or memory address. (Combined with W/R to generate the read/write signals present in earlier µp). RESET: initializes the 80386, causing it to begin executing software at memory location FFFFFFF0 CLK2: Clock times 2 is driven by a clock signal that is twice the operating frequency of the Apr-15 6

7 80386DX Pin Functions READY: Controls the number of wait states. LOCK: Lock=0 when an instruction is prefixed with the LOCK: prefix. D/C: Data/Control, if D/C=1, the data bus contains data for or from memory or I/O. If D/C=0, the µp is halted or executes an interrupt. BS16: Bus Size 16 selects either a 32 bit data bus (BS16=1) or 16-bit data bus (BS16=0). NA: Next Address causes the to output the address of the next instruction or data in next cycle 21-Apr-15 7

8 80386DX Pin Functions HOLD: Hold requests a DMA action HLDA: HOLD Acknowledge indicates that the is currently in a hold condition. PEREQ: The coprocessor request, and is a direct connection to the coprocessor. BUSY: Busy is an input used by the WAIT or FWAIT instruction that waits for the coprocessor to become not busy. (It is also a direct connection to the 80387). 21-Apr-15 8

9 80386DX Pin Functions ERROR: Error indicates to the µp that an error is detected by the coprocessor. INTR: Interrupt Request is used by external circuitry to request an interrupt. NMI: Non-Maskable Interrupt 21-Apr-15 9

10 The Memory System The memory is organized as four banks, each containing 1GB. (See Fig. 7-3 Page 169) Memory is accessed as 8, 16, or 32-bits. The 32-bit wide memory allows bytes, words, or double-words of memory data to be accessed directly. The 80386DX transfers up to 32-bit wide number in a single memory cycle. The uses a 32-bit wide memory address with bytes from H FFFFFFFFH 21-Apr-15 10

11 The Buffered System The is buffered to increase the fan-out from its address, data, and control connections. In Fig. (7-4) P. 171, the µp is operated at 25 MHz using a 50 MHz clock input signal that is generated by an integrated oscillator module. The HLDA is used to enable all buffers in a system that uses DMA. In a non DMA system, buffer enable pins are grounded. 21-Apr-15 11

12 Pipelines and Caches Pipeline is a special way of handling memory accesses so the memory has additional time to access data. Pipelining allows memory an extra clocking period to access data. The extra clock extends the access time from 50 ns to 81 ns on the operating at 16 MHz. The pipe is set up by the microprocessor. Higher speed systems can not use pipelining. Cache is used to increase memory system speeds. 21-Apr-15 12

13 Interleaved Memory Systems An interleaved memory system is used to improve the speed. Memory access times can be lengthened without the need of wait states because the address is generated to select the memory before the microprocessor accesses it. It needs two or more complete sets of address buses and a controller that provides addresses for each bus. Systems that employ two complete buses are called 2-way interleave. 21-Apr-15 13

14 The Input/Output System All systems use isolated I/O because of the I/O protection scheme provided by the in protected mode operation. The uses a full 32-bit wide I/O system divided into four banks (Fig. 7-8 Page 176). Most I/O transfers are 8-bit wide because we often use ASCII code for transferring alphanumeric data between µp and printers and keyboards. 21-Apr-15 14

15 The Input/Output System The I/O locations are numbered from 0000H to FFFFH. A portion of the I/O map is designated for the coprocessor. The coprocessor uses I/O location F8H FFH. New feature: An I/O location can be blocked in the protected mode. If the blocked location is addressed, an interrupt (Type 13) is generated. 21-Apr-15 15

16 Timing in The The timing is referenced to the CLK2 input signal. A bus cycle consists of four clocking periods. Each bus cycle contains two clocking states (T1 and T2) with each state containing two clocking periods. (Fig page 177 Non-pipelined). Compare with (Fig Pipelined) Compare also with inserted wait states (Fig. 7-12) Report (Compare between the three cases) 21-Apr-15 16

17 Special Registers Control Registers: In addition to the EFLAGS and EIP, there are other control registers found in the 80386; CR0, CR1, CR2, and CR3 CR1 is not used in the CR2 holds the linear page address of the last page accessed before a page fault interrupt. CR3 holds the base address of the page directory. 21-Apr-15 17

18 Control Registers The rightmost 12 bits of the 32 bit page table address contain zeros and combine with the remainder of the register to locate the start of the page table. CR0 is 32-bit wide: PG: Selects page table translation of linear address into physical address when PG=1. ET: Selects coprocessor when ET=0, coprocessor when ET=1. 21-Apr-15 18

19 Control Registers TS: indicates that the has switched tasks. If TS=1, a numeric coprocessor instruction causes type 7 interrupt (Coprocessor not available). EM: Is set to cause a type 7 interrupt for each ESC instruction. MP: Is set to indicate that the coprocessor is present in the system. PE: Is set to select the protected mode of operation. It may be cleared to re-enter the real mode. 21-Apr-15 19

20 Debug Registers Four debug registers (DR0, DR1,DR2, and DR3) contain 32-bit linear breakpoint addresses. The linear address is generated by the µp instruction that may or may not be the same as the physical address. The breakpoint addresses are compared with the addresses generated by the program. If a match occurs, the µp cause type 1 interrupt The breakpoint addresses are useful in debugging faulty software 21-Apr-15 20

21 Debug Registers DR4 and DR5 are not used DR6 and DR7 have control bits: BT: If Set, the debug interrupt was caused by a task switch. BS: If set, the debug interrupt was caused by the TF bit in the flag register. BD: If set, the debug interrupt was caused by an attempt to read the debug register. B0 B3: indicates which of the 4 debug breakpoint addresses caused the debug interrupt. 21-Apr-15 21

22 Debug Registers LEN: These bits define the size of access at the breakpoint address. RW: These bits select the cause of action that enabled a breakpoint address. GD: If set, it prevents any read or write of a debug registry by generating the debug interrupt. GE: If set, selects a global breakpoint address LE: If set, selects a local breakpoint address 21-Apr-15 22

23 Test Registers Test registers TR6 and TR7 are used to test the Translation Look-aside Buffer (TLB) The TLB in the holds the most common 32 entries from the page table. TR6 holds the tag field of the TLB. TR7 holds the physical address of the TLB. To write a TLB entry: 1. Write TR7 for the desired physical address 2. Write TR6 with the linear address (C=0) 21-Apr-15 23

24 Test Registers To read a TLB entry: 1. Write TR6 with the linear address (C=1) 2. Read both TR6 and TR7. If the PL bit indicates a hit, the desired values of TR6 and TR7 indicate the contents of the TLB. Bits in TR6 and TR7: V: Shows that the entry in the TLB is valid C: Selects a write (0) or immediately lookup (1) PL: Indicates a hit if PL=1 21-Apr-15 24

25 80386 Memory Management The MMU is similar to that of the except that the contains a paging unit not found in the The MMU converts linear address into physical addresses using the paging mechanism. Any linear location can be mapped into any physical location (Large flexibility). The area between ROMs is called upper memory The area above FFFFFH is extended memory 21-Apr-15 25

26 M / IO Descriptors and Selectors A descriptor is a series of 8 bytes that describe and locate a memory segment. A selector (segment register) is used to index a descriptor from a table of descriptors. The has 2 extra selectors more than the (FS and GS). The uses 32-bit base address and 20-bit limit (segment length 1M if G=0 and 4G if G=1) The granularity bit is found in the descriptor. 21-Apr-15 26

27 Descriptors and Selectors If G=0, the number stored in the limit is interpreted directly as a limit, allowing it to contain any limit between 00000H and FFFFFH giving a segment size up to 2 20 or 1MB. If G=1, the number stored in the limit is interpreted as 00000XXXH-FFFFFXXXH where XXX range from 000H FFFH This allows the limit of the segment to range between 0 4GB in steps of 4 KB. 21-Apr-15 27

28 Descriptors and Selectors In the 80386, the selector uses the leftmost 13 bits to select a descriptor from the descriptor table Thus, there are 2 13 =8192 descriptors in each table Because each segment can be 4GB in length, we can access 8192*2=16384 segments at a time with 2 descriptor tables. Thus, the can access a virtual memory size of 16384*4GB=64TB There is a third descriptor table for interrupt (IDT) 21-Apr-15 28

29 Fields in The Descriptors Base (B0 B31): define the starting 32-bit address of the segment within the 4GB physical address. Limit (L0 L19): Define the limit of the segment in units of bytes (G=0) or units of 4KB (G=1) Access Rights: Determine the privilege level of the segment. G: Granularity bit selects a multiplier of 1 or 4KB D: Selects the default register size. If D=0, the registers are 16-bit and if D=1, they are 32-bit. 21-Apr-15 29

30 Fields in The Descriptors AVL: Available bit for the OS. It often indicates that the segment described by a descriptor is available. 21-Apr-15 30

31 Segment Descriptors The segment descriptor defines data, stack, and code segment. (Fig Page 185) The access right bits are described as follows: P: Present is a logic 1 to indicate that the segment is present DPL: Descriptor privilege level (00 has the highest privilege & 11 has the lowest privilege) S: Segment indicates a data or code segment descriptor (s=1) or a system segment (S=0). 21-Apr-15 31

32 Segment Descriptors E: Executable selects a data segment (E=0) or a code segment (E=1) X: If E=0, X indicates the direction of expansion for the data segment. If E=1, X indicates whether the privilege level of the code segment is ignored (X=0) or observed (X=1). RW: If E=0, the RW indicates that the data segment may be written (RW=1) or not (RW=0). If E=1, the RW indicates that the code segment may be read (RW=1) or not (RW=0). 21-Apr-15 32

33 Thank You With all best wishes!! 21-Apr-15 33

MP Assignment IV. 1. A. Describe the 80386DX memory system and explain the purpose and operation of the bank selection signals.

MP Assignment IV. 1. A. Describe the 80386DX memory system and explain the purpose and operation of the bank selection signals. MP Assignment IV 1. A. Describe the 80386DX memory system and explain the purpose and operation of the bank selection signals. The 80386 has a 32-bit data bus and four banks of memory. A logical address