PART TOP VIEW ADDR2 ADDR3 ADDR4 SELECT S/H CONFIG V L DGND V SS AGND IN N.C. Maxim Integrated Products 1

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1 9-674; Rev ; 4/ 32-Channel Sample/Hold Amplifier General Description The MAX568 contains 32 sample/hold amplifiers and four -of-8 multiplexers. The logic controlling the muxes and sample/hold amplifiers combines the four muxes into a unified -of-32 multiplexer with a sample/hold at each output. Additional logic allows two devices to function as a single 64-channel unit. The MAX568 is available with an output impedance of 5Ω, 5Ω, or kω. The MAX568 operates with + and -5 supplies, and a separate +5 digital logic supply. Manufactured with a proprietary BiCMOS process, it provides high accuracy, fast acquisition time, a low droop rate, and a low hold step. The MAX568 has a typical linearity error of less than.% and can accurately acquire 8 step input signals to.% accuracy in 2.5µs within the +7 to -4 input signal range. Transitions from sample mode to hold mode result in only a.5m error. While in hold mode, the output voltage slowly droops at a rate of m/s. The MAX568 is available in a 48-pin TQFP package and is specified for both the commercial ( C to +7 C) and extended industrial (-4 C to +85 C) temperature ranges. 32-Channel Sample/Hold.% Accuracy of Acquired Signal.% Linearity Error Fast Acquisition Time: 2.5µs Low Droop Rate: m/s Low Hold Step:.25m Wide Output oltage Range: +7 to -4 PART MAX568LCCM MAX568MCCM MAX568NCCM MAX568LECM MAX568MECM MAX568NECM Features Ordering Information TEMP. RANGE C to +7 C C to +7 C C to +7 C -4 C to +85 C -4 C to +85 C -4 C to +85 C PIN- PACKAGE 48 TQFP 48 TQFP 48 TQFP 48 TQFP 48 TQFP 48 TQFP R OUT (Ω) 5 5 k 5 5 k MAX568 Applications Pin Configuration Automatic Test Systems (ATE) Industrial Process Controls Arbitrary Function Generators Avionics Equipment TOP IEW ADDR ADDR OUT3 OUT3 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 ADDR2 OUT2 ADDR3 2 OUT2 ADDR4 3 OUT9 SELECT 4 OUT8 S/H 5 OUT7 CONFIG L DGND SS AGND IN N.C OUT6 DD OUT5 OUT4 OUT3 OUT2 OUT N.C. OUT OUT OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT MAX568 TQFP Maxim Integrated Products For free samples and the latest literature, visit or phone For small orders, phone

2 MAX568 ABSOLUTE MAXIMUM RATINGS DD to AGND to +. SS to AGND to +.3 DD to SS L to DGND to +6. L to AGND to +6. DGND to AGND to +2. IN, OUT_... SS to DD Logic Inputs to DGND to +6. Maximum Current into OUT_...±mA Maximum Current into Logic Inputs...±2mA Continuous Power Dissipation (T A = +7 C) 48-Pin TQFP (derate 2.5mW/ C above +7 C)...mW Operating Temperature Ranges MAX568_CCM... C to +7 C MAX568_ECM...-4 C to +85 C Storage Temperature Range C to +5 C Lead Temperature (soldering, s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( DD = +., SS = -5., L = +5. ±5%, AGND = DGND =, R L = 5kΩ, C L = 5pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG SECTION Linearity Error -4. < IN < +7, R L =..8 % Hold Step HS IN = AGND.25. m Droop Rate IN = AGND, T A = +25 C 4 m/s Offset oltage OS IN = AGND, T A = +25 C +5 C T A +65 C (Note ) m µ/ C Output oltage Range OUT_ R L = SS + DD Analog Crosstalk 8 step with 5ns rising edge (Note ) C L = 25pF for MAX568L C L = nf for MAX568M/N db Input Capacitance C IN (Note ) 2 pf DC Output Impedance R OUT_ R L =, C L = 25pF MAX568L MAX568M MAX568N Ω Output Source Current I SOURCE IN =, sample mode 2 ma Output Sink Current I SINK IN =, sample mode 2 ma Output Clamp High CH SS DD TIMING PERFORMANCE Acquisition Time t AQ T A = +25 C, R L =, Figure 2 8 step to.8% m step to ±m µs Hold-Mode Settling Time t H To ±m of final value, Figure 2 (Note ) 2 µs Aperture Delay t AP Figure 2 (Note ) 2 ns 2

3 ELECTRICAL CHARACTERISTICS (continued) ( DD = +., SS = -5., L = +5. ±5%, AGND = DGND =, R L = 5kΩ, C L = 5pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) S/H Pulse Width Data Setup Time Data Hold Time PARAMETER DIGITAL INPUTS Input oltage High Input oltage Low Input Current POWER SUPPLIES Positive Analog Supply Negative Analog Supply Digital Logic Supply Positive Analog Supply Current Negative Analog Supply Current SYMBOL t PW t SET t DH IH IL I I DD SS L I DD I SS Figure 2 (Note ) Figure 2 (Note ) Figure 2 (Note ) IN = DGND or CC (Note 2) (Note 2) R L = R L = CONDITIONS MIN TYP MAX UNITS ns ns ns µa ma ma MAX568 Digital Logic Supply Current I L ADDR_ = DGND or L, S/H = DGND or L ADDR_ =.8 or 2., S/H =.8 or ma ma Power-Supply Rejection Ratio PSRR For DD and SS, sample mode, IN = AGND db Note : Guaranteed by design. Note 2: Do not exceed the absolute maximum rating for DD to SS of (see Absolute Maximum Ratings). 3

4 MAX568 Typical Operating Characteristics ( DD = +, SS = -5, L = +5, IN = +5, R L =, C L =, AGND = DGND =, CH = DD, CL = SS, T A = +25 C, unless otherwise noted.) DROOP RATE (m/s) DROOP RATE vs. INPUT OLTAGE INPUT OLTAGE () MAX568 TOC DROOP RATE (m/s) DROOP RATE vs. TEMPERATURE TEMPERATURE ( C) MAX568 TOC 2 PSRR (db) POWER-SUPPLY REJECTION RATIO SAMPLE MODE NEGATIE SUPPLY ( SS ) POSITIE SUPPLY ( DD )., FREQUENCY (khz) MAX568 TOC POWER-SUPPLY REJECTION RATIO HOLD MODE POSITIE SUPPLY ( DD ) MAX568 TOC HOLD STEP vs. INPUT OLTAGE MAX568 TOC HOLD STEP vs. TEMPERATURE MAX568 TOC 6 PSRR (db) NEGATIE SUPPLY ( SS ) HOLD STEP (µ) HOLD STEP (µ) , FREQUENCY (khz) INPUT OLTAGE () TEMPERATURE ( C) OFFSET OLTAGE (m) OFFSET OLTAGE vs. INPUT OLTAGE INPUT OLTAGE () MAX568 TOC 7 OFFSET OLTAGE (m) OFFSET OLTAGE vs. TEMPERATURE TEMPERATURE ( C) MAX568 TOC 8 4

5 PIN NAME ADDR2 Bit 2 of the Address Decoder 2 ADDR3 Bit 3 of the Address Decoder 3 ADDR4 Bit 4 of the Address Decoder 4 SELECT FUNCTION Pin Description Enables the S/H pin. The polarity of SELECT is determined by the state of the CONFIG pin. If CONFIG is low, then SELECT is active-high. If CONFIG is high, then SELECT is active-low. When SELECT is not in its active state, all 32 channels are in hold mode independent of the S/H pin. MAX568 5 S/H Puts the selected channel into sample mode when low. Places all channels into hold mode when high. 6 CONFIG Sets the polarity of the SELECT pin. 7 L +5 Logic Supply 8 DGND Digital GND 9 SS -5 Analog Supply AGND Analog GND IN Input Pin 2, 3 N.C. No connection. Not internally connected OUT OUT5 Outputs 5 Pins 3 DD + Analog Supply 3 46 OUT6 OUT3 Outputs 6 3 Pins 47 ADDR Bit of the Address Decoder 48 ADDR Bit of the Address Decoder 5

6 MAX568 S/H SELECT CONFIG CS SW ADDR ADDR4 SW2 SW3 SW3 MAX568 OUT OUT IN OUT3 OUT3 Figure. Functional Diagram Detailed Description Digital Interface The MAX568 has three logic control inputs and five address lines. The address lines are inputs to a demultiplexer that selects one of the 32 outputs in a standard addressing scheme (Table ). The analog input is connected to the addressed sample/hold when directed by the control logic (Table 2). The three logic control lines determine the state of the addressed sample/hold. The normal circuit connection for this device is to hardwire CONFIG and SELECT to opposing logic voltages. When SELECT and CONFIG are in opposite states (one high and the other low), the five address lines select one of the sample/holds. Use the S/H line to place the selected channel into sample or hold mode. The other 3 channels will remain in hold mode. If an active-high sampling mode is desired, tie S/H and CONFIG low. In this case, SELECT controls the addressed channel with a high state putting that channel into sample mode. The SELECT and CONFIG pins allow the design of a virtual 64-channel device using two of the MAX568s. See the Applications Information section for more information about 64-plus output addressing schemes. Sample/Hold The MAX568 contains 32 buffered sample/hold circuits with internal hold capacitors. Internal hold capacitors minimize leakage current, dielectric absorption, feedthrough, and required board space. The value of the hold capacitor affects acquisition time and droop rate. Smaller capacitance allows faster acquisition times but increases the droop rate. Larger values increase hold acquisition time. The hold capacitor used in the MAX568 provides fast 2.5µs (typ) acquisition time while maintaining a relatively low m/s (typ) droop rate, making the sample/hold ideal for highspeed sampling. Sample Mode When SELECT and CONFIG are in opposing logic states, the S/H line controls the mode of operation. Sample mode is entered when S/H is low. During sample mode, the 6

7 MAX Channel Sample/Hold Amplifier 7 Table. Channel/Output Selection Table 2. Logic Table for CONFIG, SELECT, and S/H X SELECT Sampling Sampling Hold Hold Hold X CHANNEL FUNCTION CONFIG S/H (SAMPLE/HOLD) OUT2 OUT OUT OUT9 OUT8 OUT7 OUT3 OUT4 OUT5 OUT6 ADDR ADDR3 ADDR4 ADDR2 ADDR OUT2 OUT OUT OUT9 OUT8 OUT7 OUT3 OUT4 OUT5 OUT6 OUT26 OUT25 OUT24 OUT3 OUT27 OUT28 OUT29 OUT3 OUT23 OUT22 OUT2 OUT2 X = Don t care. OUTPUT

8 MAX568 selected multiplexer channel connects to IN, allowing the hold capacitor to acquire the input signal. To guarantee an accurate sample, maintain sample mode for at least 4µs. The output of the sample/hold amplifier tracks the input after 4µs. Only the addressed channel on the selected multiplexer samples the input; all other channels remain in hold mode. Hold Mode No matter what the condition of the other control lines, S/H = high places the MAX568 into an all-channel hold mode. Hold mode disables the multiplexer and disconnects all 32 sample/holds from the input. When a channel is disconnected, the hold capacitor maintains the sampled voltage at the output with a m/s typical droop rate (towards DD ). Hold Step When switching between sample mode and hold mode, the voltage of the hold capacitor changes due to charge injection from stray capacitance. This voltage change, called a hold step, is minimized by limiting the amount of stray capacitance seen by the hold capacitor. The MAX568 limits the hold step to.25m (typ). An output capacitor to ground can be used to filter out this small hold-step error. Output The MAX568 contains an output buffer for each multiplexer channel (32 total), so the hold capacitor sees a high-impedance input that reduces the droop rate. The capacitor droops at m/s (typ) while in hold mode. The buffer also provides a low output impedance; however, the device contains output resistors in series with the buffer output (Figure ) for selected output filtering. To provide greater design flexibility, the MAX568 is available with an output impedance of 5Ω, 5Ω, or kω. Output loads increase the analog supply current (I DD and I SS ). Excessive loading of the output(s) drastically increases power dissipation. Do not exceed the maximum power dissipation specified in the Absolute Maximum Ratings. The resistor-divider formed by the output resistor (R O ) and load impedance (R L ) scales the sampled voltage ( SAMP ). Determine the output voltage ( OUT_ ) as follows: oltage Gain = A = R L / (R L + R O ) OUT_ = SAMP A The maximum output voltage range depends on the analog supply voltages available and the scaling factor used: when R L =, then A =, and this equation becomes ( SS +.75) OUT ( DD - 2.4) Timing Definitions Acquisition time (t AQ ) is the time the MAX568 must remain in sample mode for the hold capacitor to acquire an accurate sample. The hold-mode settling time (t H ) is the time necessary for the output voltage to settle to its final value. Aperture delay (t AP ) is the time interval required to disconnect the input from the hold capacitor. The hold pulse width (t PW ) is the time the MAX568 must remain in hold mode while the address is changed. Data setup time (t DS ) is the time an address must be maintained at the digital input pins before the address becomes valid. Data hold time (t DH ) is the time an address must be maintained after the device is placed in hold mode (Figure 2). Applications Information Multiplexing a DAC Figure 3 shows a typical demultiplexer application. Different digital codes are converted by the digital-toanalog converter (DAC) and then stored on 32 different channels of the MAX568. The 4m/s (max) droop rate requires refreshing the hold capacitors every 25ms before the voltage droops by /2LSB for an 8-bit DAC with a 5 full-scale voltage. irtual 64 Output Sample/Hold Two MAX568s can be configured to operate as a single 64 output sample/hold. The upper and lower addressed devices are identified by CONFIG s logic level. Connect the CONFIG pin of the upper device low, making its SELECT pin active high. Connect the CONFIG pin of the lower device high to make the SELECT pin active low. Figure 4 shows how to configure the devices. The devices now use only six address lines and a single S/H control to decode 64 outputs. Address lines A A4 from the control logic connect to ADDR ADDR4 on both of the 32-channel devices. The A5 line toggles the SELECT pins of both devices to select the active one. The device that has CONFIG tied high responds to the lower 32 addresses ( through ). The device that has CONFIG grounded responds to the upper 32 addresses ( through ). ( SS +.75) A OUT_ ( DD - 2.4) A 8

9 S/H ADDR_ SELECT, CONFIG t DH t PW t DS MAX568 OUT_ t H HOLD STEP IN t AQ t AP (CHANNEL x FROM HOLD TO SAMPLE) (CHANNEL x FROM SAMPLE TO HOLD) Figure 2. Timing Diagram L SELECT ADDRESS BUS ADDR ADDR4 S/H CS ADDRESS DECODER SWITCHES 3 MAX568 OUT OUT DATA BUS DAC IN OUT3 OUT3 CONFIG Figure 3. Multiplexing a DAC 9

10 MAX568 A A4 A5 WR INPUT L CONFIG ADDR ADDR4 SELECT S/H IN MAX568 OUT OUT OUT3 OUT3 ADDR ADDR4 SELECT OUT32 OUT33 S/H IN CONFIG MAX568 OUT62 OUT63 Figure Output Sample/Hold Circuit Input Drive Requirements The input of the MAX568 feeds the inputs of 32 highimpedance buffers. These buffers are what charge the sample/hold capacitor through the multiplexer switch resistance. The bias current of a selected buffer is µa, and this feeds into the pf input capacitance. Figure 5 shows an equivalent input circuit. The bias currents of the other 3 sample and holds are very small in comparison to the bias current of the selected channel. Powering the MAX568 The MAX568 does not require a special power-up sequence to avoid latchup. The device requires three separate supply voltages for operation. However, when one or two of the voltages are not available, DC-DC charge-pump (switched-capacitor) converters provide a simple, efficient solution. The MAX86 provides voltage doubling or inversion, ideal for conversions from +5 to + or from +5 to -5. I BIAS µa, I NH = LOW C IN pf Figure 5. Input Equivalent Circuit Chip Information TRANSISTOR COUNT: 696

11 Package Information 32L/48L,TQFP.EPS MAX568

12 MAX568 NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 2 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

PART TOP VIEW ADDR2 ADDR3 ADDR4 SELECT S/H CONFIG V L DGND V SS AGND IN CH. Maxim Integrated Products 1

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