Design of Embedded Hardware and Firmware

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1 Design of Embedded Hardware and Firmware Introduction on "System On Programmable Chip" NIOS II Avalon Bus - DMA Andres Upegui Laboratoire de Systèmes Numériques hepia/hes-so Geneva, Switzerland

2 Embedded system on Altera FPGA Goals : To understand the architecture of an embedded system on FPGA To be able to identify the components required for building a specific interface To have an overview of the construction of a full system based on a standard softcore bus in a FPGA with block modules 2

3 Embedded system on Altera FPGA Contents System on Programmable Chip SoPC NIOS II a softcore processor Avalon Bus Slave programmable interface on Avalon DMA Master programmable interface on Avalon Tools 3

4 SoPC from Altera : Nios II + Avalon bus + memory + system peripherals Note: The same principles are available for Altera, Xilinx, Actel or others FPGA 4

5 AVALON Switch Fabric Avalon specifications : Multi-Master Arbitrage «slave-side» Concurrent Master-Slave Access Synchronous transfers 5

6 NIOS II Softcore Processor from Altera A processor implemented with Logic Elements (LUT+DFF) in a FPGA A processor synthesized by a compiler and placed & routed on the FPGA A processor described by a HDL langage(vhdl/verilog/ ) 32 bits Architecture 3 versions 256 instructions available for user implementation 6

7 NIOS II Processor 3 processor architectures 7

8 NIOS II Processor, user instructions The ALU can be extended by user own instructions, until

9 NIOS II Processor, user instructions The instructions can be: Combinatorial, single clock cycle Multi-cycles, synchronized by clk and stall Parameterized They can have access to all the FPGA resources They can use their own internal registers Main limitation: the execution is driven by the processor and incoming data is fed from processor registers. 9

10 NIOS II Processor, hardware accelerator For cycles consuming operations, a hardware accelerator can be included/developed A Master unit which has access to Memory and Programmable Interfaces for accelerated operations or with hard real time constrains 10

11 NIOS II Processor, performances gain 11

12 Computer architecture Classical architecture : Processor Memories Peripheral interfaces Address bus Data Bus (tri-state) General decoder Address Bus MicroProcessor Control Bus D é c o d e r Memories Program Data Stack Peripherals Tri-state data bus 12

13 Computer architecture SOPC architecture (Altera) Processor Memories Input/Output (programmable) interface Address bus Separated Data Bus In/Out multiplexers Local decoder on the Avalon bus Bus transfers size adaptation is done at Avalon bus level 13

14 System on FPGA example 14

15 Avalon Interface Permits to interconnect every masters and slaves inside the FPGA: Specific master and slave interfaces Synchronous bus Separate data in and data out Wait state by configuration or dynamic Hold / Set up available 15

16 Avalon «slave» basic signals Signal Type Width Direction Required Description clk 1 In (No) Global clk for system module and Avalon bus modules. All transactions synchronous to clk rising edge nreset 1 In No Global Reset of the system address In No Address for Avalon bus modules chipselect 1 In Yes Selection of the Avalon bus module read 1 In No Read request to the slave readdata Out No Read data from the slave module write 1 In No Write request to the slave writedata In No Data from Master to Slave module irq 1 Out No Interrupt request to the master 16 AU-RB-2012

17 Avalon «slave» signals The ChipSelect is generated by the Avalon bus and selects the module The Address[n.. 0] is used to access a specific register/memory position in the selected module. Only the minimum number of address is necessary. Ex: a module with 6 internal registers needs 3 bits of addresses (6< 2**3) 17

18 Avalon «slave» signals The Read and Write signals specified the direction of the transfers. They are provided by a Master and received by the slave modules The direction is the view of the Master unit ReadData(..) and WriteData(..) bus transfers the Datas from (read)/ to (write) the Slaves 18

19 Avalon «slave» signals BE (Byte Enable) signals indicate the bytes to transfer. The number of BE activated are always a power of 2 They start at a multiple of the size to transfer A master address is a byte address A slave address is a word address The Avalon bus make the translation and performs multiple accesses if required. 19

20 Avalon «slave» advanced signals Signal Type Width Direction Required Description WaitRequest/ WaitRequest_n 1 Out No Assert by the slave when it is not able to answer in this clock cycle to read or write access ByteEnable/ ByteEnable_n 1, 2, 4, 8,.., 128 BeginTransfer 1 In No ReadDataValid/ ReadDataValid_n In No The bytes to transfer 1 Out No Inserted by Avalon fabric at and only at first clock of each transfer For read transfer with variable latency, means data are valid to master BurstCount In No Number of burst transfers BeginBurstTransfer 1 In No First cycle of a burst transfer, valid for 1 clock cycle 20

21 Avalon «slave» advanced signals Signal Type Width Direction Required Description ReadyForData 1 Out No DataAvailable 1 Out No ResetRequest/ ResetRequest_n ArbiterLock/ ArbiterLock_n 1 Out No 1 In No 21

22 Avalon Bus Transfers Slave view of transfers Transfers are synchronous on the rising edge of the Clk. A specific latency (number of clock cycles) per access must be respected according to the type of access performed. The transfer type must be defined at design-time. 22

23 Avalon slave read, 0 wait, asynchronous peripheral ReadData available at next rising edge of clk (E) 23

24 Avalon slave read, 1 wait Wait cycle specified by design 24

25 Avalon read slave, 2 wait 25

26 Avalon read slave, 1 set up and 1 wait AU-RB-2012 RB-A2010

27 Avalon read slave, wait request generated by slave device 27

28 Avalon read slave, burst of 4 from Master A, 2 from master B Pipeline of master access ReadDataValid activated by slave for each data AU-RB-2012 RB-A2010

29 Avalon write slave, 0 wait 29

30 Avalon write slave, 1 wait 30

31 Avalon write slave, wait request generated by slave 31

32 Up to now we understand how to build a peripheral, how to connect it to an Avalon bus, and how to access it from a Nios II processor. This solution is satisfactory for peripherals dealing with low data rate transfers (Timer, PWM, GPIOs) However, what about peripheral manipulating large amount of data? (cameras, graphic controllers, ethernet, ) How can data be optimally transferred from memory to peripherals? And vicecersa? 32

33 Optimizing memory and peripheral access: polling? In a computer system, peripheral access through programmable interfaces can be performed by processor transfer instructions. Control registers, present in the peripheral, allow the processor to indicate the actions to be performed. For instance, a start signal may launch a procedure. Status registers allow to check the current state of peripheral. For instance, verify whether a data transfer can be done or not. By polling of status register, the program can know when the interface is ready for the transfer 33

34 Optimizing memory and peripheral access: interruptions? If we want the processor not to loose time polling unnecessarily the different interfaces, hardware interrupts can indicate the processor when a certain condition is met in order to allow the processor to execute a special function called interrupt handler or ISR for interruption service routine. Some signals are necessary as IRQ (Interrupt Request) (at least) and sometimes Interrupt Acknowledge Some instructions need to be executed to serve the interrupt handler (context saving and switching, request testing, programmable interface servicing and acknowledge) Limited transfer bandwidth 34

35 Optimizing memory and peripheral access: Direct Memory Access - DMA - For systems where the transfer rate between the I / O and memory is high, the polling or interruptions are unusable A more efficient system is needed : DMA The transfer is carried out by a specialized unit: the DMA controller The DMA controller performs transfers instead of the processor DMA must have control of the bus as a Master: Address Data Control transfers 35

36 Example of an SoPC with a DMA controller - The DMA controller is a programmable interface that must be programmed by the processor before it is operational - When a data packet has been transferred, the processor is notified by interruption. - For the DMA to be useful, we need a certain amount of data to transfer. 36

37 DMA for Avalon DMA unit architecture Read bus Internal FIFO Write bus Programmable control unit 37

38 DMA registers Seen by the processor (NIOS) as 8 * 32 bits registers 38

39 Status Register Information on controller status A write access clear len, weop, reop, and done bits 39

40 Status done is activated at the end of the transfer An interrupt can be generated if it's enabled Bits len, weop, and reop allows to know the cause of the transfer end. When done is deactivated by a write to this register, the interrupt request is deactivated too 40

41 Control Registers Readaddress, writeaddress, length specify the source, destination addresses and the length of the transfer length is defined in the number of bytes Width of registers is specified at the DMA unit creation. 41

42 Control Register Control register specify modes and enabling functions 42

43 Control rcon et wcon specified if the read or write address is fixed ( 1 ) or to increment ( 0 ) depending the transfer width and _con specified, the addresses are incremented by 0, 1, 2 or 4 43

44 Hardware Accelerator - In addition to performing transfers your DMA controller may also perform some kind of computation before writing data on memory. - In this case we talk about a Hardware accelerator with DMA access. - Execution is still controlled by the processor through interface registers. - You can build it by yourself in VHDL!! 44

45 Avalon Interface: Master view The master starts a transfer (read or write). It provides the Addresses (32 bits on NIOSII). It drives control signals. It waits on WaitRequest signal to resume the transfer. 45

46 Avalon master signals (1) 46

47 Avalon master signals (2) 47

48 Avalon Master Basic fundamental transfers Wait Wait 48

49 Avalon read master, 0 wait 49

50 Avalon read master, wait generated by slave/avalon bus Wait cycles 50

51 Avalon write master, 0 wait 51

52 Avalon write master, wait generated by slave Wait cycles 52

53 Avalon read transfers with latency (ex. 2 cycles) Wait request here means : delay address cycle Fixed latency (here 2) 53

54 SLAVE Embedded System on FPGA (example) SDRAM 64MB 16Mx32 FLASH UART0 UART1 JTAG ALTERA CYCLONE EP1C12 Contrôleur SDRAM SLAVE Contrôleur EPCS4 SLAVE 2 x UART SLAVE JTAG SLAVE NIOS II MASTER 7'430 / 12'000 LE (61%) 76'032 / 239'613 Mb (31%) 1 /2 PLL (50%) MASTER Instruction Cache Data Cache Cpu Clk 2k bytes 2k bytes 50 MHz DMA MASTER SLAVE CAMERA SLAVE I2C SLAVE CAPTEURS SLAVE MOTEURS PWM SLAVE GPIO SLAVE GPIO SLAVE OneWire Dallas CAMERA 128 x 100 LCD 96 x 40 Capteurs TCRT AD Moteurs + Odométrie MODULE RF HEVs LEDS DS AU-RB-2012

55 Developments Tools from ALTERA Quartus II Hardware Description Qsys SOC NIOS II NIOS II IDE Eclipse environnent (C,C++) Schematic Editor, VHDL, Synthesis + placement routing Simulation (graphical éditor ) Signal TAP Configuration + SOC generation Programmable Interface library Own Programmable Interfaces. Generation SDK Project management Compiler + Link Editor Debugger SOC Programmer 55

56 Developments Tools from ALTERA Quartus // Working processus Autres Contraintes Project Navigator Vérification Edition OK Simulation Editio n Synthèse Téléchargement Status Compilation Messages Console Script 56

57 Developments Tools from ALTERA Qsys Processor Nios II Bus Arbitration Memory Map Components Library SOC Interrupts 57

58 Developments Tools from ALTERA NIOS II IDE (code input) Project Navigator Edition Windows Source messages 58

59 Developments Tools from ALTERA NIOS II IDE (debugging) Debugging Objects tree Memory Variables Source source Console messages 59

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