VCCO GND V CCOGND DE_OUT CNTL_OUT8 CNTL_OUT7 CNTL_OUT6 CNTL_OUT5 CNTL_OUT4 CNTL_OUT3 CNTL_OUT2 CNTL_OUT1T CNTL_OUT0 OUTEN PWRDWN RGB_OUT8 RGB_OUT9

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1 9-3557; Rev 5; 8/9 EVALUATION KIT AVAILABLE 27-Bit, 3MHz-to-35MHz General Description The digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 8 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take advantage of video timing to reduce the serial data rate. The pairs with the MAX927 serializer to form a complete digital video transmission system. Proprietary data decoding reduces EMI and provides DC balance. The DC balance allows AC-coupling, providing isolation between the transmitting and receiving ends of the interface. The features a selectable rising or falling output latch edge. ESD tolerance is specified for ISO 65 with ±kv contact discharge and ±3kV air discharge. The operates from a +3.3V core supply and features a separate output supply for interfacing to.8v to 3.3V logic-level inputs. This device is available in 48- lead Thin QFN and LQFP packages and is specified from -4 C to +85 C. Applications Navigation System Display In-Vehicle Entertainment System Video Camera LCD Displays Features Proprietary Data Decoding for DC Balance and Reduced EMI Control Data Deserialized During Video Blanking Five Control Data Inputs Are Single Bit-Error Tolerant Output Transition Time Is Scaled to Operating Frequency for Reduced EMI Staggered Output Switching Reduces EMI Output Enable Allows Busing of Outputs Clock Pulse Stretch on Lock Wide ±2% Reference Clock Tolerance Synchronizes to MAX927 Serializer Without External Control ISO 65 ESD Protection Separate Output Supply Allows Interface to.8v to 3.3V Logic +3.3V Core Power Supply Space-Saving Thin QFN and LQFP Packages -4 C to +85 C Operating Temperature Ordering Information PART TEMP RANGE PIN-PACKAGE ECM+ -4 C to +85 C 48 LQFP ECM/V+ -4 C to +85 C 48 LQFP ETM+ -4 C to +85 C 48 Thin QFN-EP* +Denotes a lead(pb)-free/rohs-compliant package. /V denotes an automotive qualified part. *EP = Exposed pad. Pin Configurations TOP VIEW RGB_OUT7 RGB_OUT6 RGB_OUT5 RGB_OUT4 RGB_OUT3 RGB_OUT2 RGB_OUT RGB_OUT VCCO VCCOGND RGB_OUT7 RGB_OUT6 RGB_OUT5 RGB_OUT4 RGB_OUT3 RGB_OUT2 RGB_OUT RGB_OUT VCCO GND VCCO V CCOGND V CCO RGB_OUT8 RGB_OUT9 RGB_OUT RGB_OUT RGB_OUT2 RGB_OUT3 RGB_OUT4 RGB_OUT5 RGB_OUT6 RGB_OUT CNTL_OUT8 CNTL_OUT7 CNTL_OUT6 CNTL_OUT5 CNTL_OUT4 CNTL_OUT3 CNTL_OUT2 CNTL_OUTT CNTL_OUT OUTEN V CCO GND 37 V CCO 38 RGB_OUT8 39 RGB_OUT9 4 RGB_OUT 4 RGB_OUT 42 RGB_OUT2 43 RGB_OUT3 44 RGB_OUT4 45 RGB_OUT5 46 RGB_OUT6 47 RGB_OUT CNTL_OUT8 CNTL_OUT7 CNTL_OUT6 CNTL_OUT5 CNTL_OUT4 CNTL_OUT3 CNTL_OUT2 CNTL_OUT CNTL_OUT OUTEN R/F RNG LQFP VCCPLL RNG GND VCC REFCLK R/F RNG VCCLVDS IN+ IN- LVDS GND PLL GND VCCLVDS IN+ IN- LVDS GND PLL GND THIN QFN-EP VCCPLL RNG GND VCC REFCLK Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim's website at

2 ABSOLUTE MAXIMUM RATINGS V CC_ to _GND...-.5V to +4.V Any Ground to Any Ground...-.5V to +.5V IN+, IN- to LVDS GND...-.5V to +4.V IN+, IN- Short Circuit to LVDS GND or V CCLVDS...Continuous IN+, IN- Short Through.25µF (or smaller), 25V Series Capacitor...-.5V to +6V (R/F, OUTEN, RNG_, REFCLK, ) to GND...-.5V to (V CC +.5V) (RGB_OUT[7:], CNTL_OUT[8:],,, ) to V CCO GND...-.5V to (V CCO +.5V) Continuous Power Dissipation (T A = +7 C) 48-Lead LQFP (derate 2.7mW/ C above +7 C)...739mW 48-Lead Thin QFN (derate 37mW/ C above +7 C).2963mW ESD Protection Machine Model (R D = Ω, C S = 2pF) All Pins to GND...±2V Human Body Model (R D =.5kΩ, C S = pf) All Pins to GND...±3.kV ISO 65 (R D = 2kΩ, C S = 33pF) Contact Discharge (IN+, IN-) to GND...±kV Air Discharge (IN+, IN-) to GND...±3kV Storage Temperature Range C to +5 C Junction Temperature...+5 C Lead Temperature (soldering, s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (V CC_ = +3.V to +3.6V, = high, differential input voltage V ID =.5V to.2v, input common-mode voltage V CM = V ID /2 to V CC - V ID /2, T A = -4 C to +85 C, unless otherwise noted. Typical values are at V CC_ = +3.3V, V ID =.2V, V CM =.2V, T A = +25 C.) (Notes, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (R/F, OUTEN, RNG, RNG, REFCLK, ) High-Level Input Voltage V IH 2. V CC +.3 V Low-Level Input Voltage V IL V Input Current I IN V IN = -.3V to (V CC +.3V), = high or low µa Input Clamp Voltage V CL I CL = -8mA -.5 V SINGLE-ENDED OUTPUTS (RGB_OUT[7:], CNTL_OUT[8:],,, ) I OH = -µa V CCO -. I OH = -2mA, High-Level Output Voltage V OH RNG, RNG = high I OH = -2mA, RNG, RNG both not high V CCO -.35 V simultaneously V CCO -.4 I OL = µa. I OL = 2mA, Low-Level Output Voltage V OL RNG, RNG = high I OL = 2mA, RNG, RNG both not high.3 V simultaneously High-Impedance Output Current I OZ = low or OUTEN = low, V O = -.3V to V CCO +.3V µa 2

3 DC ELECTRICAL CHARACTERISTICS (continued) (V CC_ = +3.V to +3.6V, = high, differential input voltage V ID =.5V to.2v, input common-mode voltage V CM = V ID /2 to V CC - V ID /2, T A = -4 C to +85 C, unless otherwise noted. Typical values are at V CC_ = +3.3V, V ID =.2V, V CM =.2V, T A = +25 C.) (Notes, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Short-Circuit Current I OS RNG, RNG both not high simultaneously, V O = LVDS INPUT (IN+, IN-) RNG, RNG = high, V O = Differential Input High Threshold V TH 5 mv Differential Input Low Threshold V TL -5 mv Input Current I IN+, I IN- = high or low µa Input Bias Resistor R IB VCC_ = or open, = or open, Figure = high or low kω ma kω Power-Off Input Current I INO+, I INO- V CC_ = or open, = or open µa POWER SUPPLY Worst-Case Supply Current I CCW C L = 8pF, worst-case pattern, Figure 2 RNG = low, 3MHz 2 RNG = low 7MHz 35 RNG = high, 7MHz 25 RNG = low 5MHz 47 RNG = high, 5MHz 37 RNG = high 35MHz 7 ma Power-Down Supply Current I CCZ (Note 3) 5 µa 3

4 AC ELECTRICAL CHARACTERISTICS (V CC_ = +3.V to 3.6V, C L = 8pF, = high, differential input voltage V ID =.V to.2v, input common-mode voltage V CM = V ID /2 to V CC - V ID /2, T A = -4 C to +85 C, unless otherwise noted. Typical values are at V CC_ = +3.3V, V ID =.2V, V CM =.2V, T A = +25 C.) (Notes 4, 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFCLK TIMING REQUIREMENTS Period t T ns Frequency f CLK 3 35 MHz Frequency Variation Δf CLK REFCLK to serializer PCLK_IN % Duty Cycle DC % Transition Time t TRAN 2% to 8% 6 ns SWITCHING CHARACTERISTICS Output Rise Time RNG, RNG = high t R Figure 3 RNG, RNG both not high simultaneously Output Fall Time t F Figure 3 RNG, RNG both not high simultaneously High Time t HIGH Figure 4 Low Time t LOW Figure 4 RNG, RNG = high Data Valid Before t DVB Figure 5.35 x t T.4 x t T ns Data Valid After t DVA Figure 5.35 x t T.4 x t T ns Input-to-Output Delay t DELAY Figure 6.4 x t T.4 x t T x t T x t T.45 x t T.6 x t T.6 x t T x t T ns ns ns ns ns PLL Lock to REFCLK t PLLREF Figure x t T ns Power-Down Delay t PDD Figure 7 ns Output Enable Time t OE Figure 8 3 ns Output Disable Time t OZ Figure 9 3 ns Note : Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except V TH and V TL. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at T A = +25 C. Note 3: All LVTTL/LVCMOS inputs, except at.3v or V CC -.3V. is.3v. Note 4: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma. Note 5: C L includes probe and test jig capacitance. 4

5 (V CC _ = +3.3V, C L = 8pF, T A = +25 C, unless otherwise noted.) SUPPLY CURRENT (ma) WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY FREQUENCY (MHz) toc Typical Operating Characteristics OUTPUT TRANSITION TIME (ns) OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (V CCO ) t R t F RNG = RNG = HIGH OUTPUT SUPPLY VOLTAGE (V) toc2 OUTPUT TRANSITION TIME (ns) OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (V CCO ) t R t F RNG = RNG = BOTH NOT HIGH OUTPUT SUPPLY VOLTAGE (V) toc3 BIT-ERROR RATE CAT5e BIT-ERROR RATE vs. CABLE LENGTH - 35MHz C 7Mbps DATA RATE FOR <2m, BER < CAT5e CABLE LENGTH (m) toc4 5

6 PIN NAME FUNCTION R/F 2 RNG Pin Description Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of for latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a falling latch edge. Internally pulled down to GND. LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input frequency. Internally pulled down to GND. LVDS Supply Voltage. Bypass to LVDS GND with.µf and.µf capacitors in parallel as close 3 V CCLVDS to the device as possible, with the smallest value capacitor closest to the supply pin. 4 IN+ Noninverting LVDS Serial Data Input 5 IN- Inverting LVDS Serial Data Input 6 LVDS GND LVDS Supply Ground 7 PLL GND PLL Supply Ground PLL Supply Voltage. Bypass to PLL GND with.µf and.µf capacitors in parallel as close to 8 V CCPLL the device as possible, with the smallest value capacitor closest to the supply pin. 9 RNG LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input frequency. Internal pulldown to GND. GND Digital Supply Ground V CC.µF and.µf capacitors in parallel as close to the device as possible, with the smallest value Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to GND with capacitor closest to the supply pin. 2 REFCLK LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within ±2% of the serializer PCLK_IN frequency. Internally pulled down to GND. 3 LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. 4 OUTEN 5 23 CNTL_OUT [8:] LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving low places the single-ended outputs in high impedance. Internally pulled down to GND. LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:] are latched into the next chip on the rising or falling edge of as selected by R/F when is low, and are held at the last state when is high. 24 LVTTL/LVCMOS Data Enable Output. High indicates RGB_OUT[7:] are active. Low indicates CNTL_OUT[8:] are active. 25, 37 V CCO GND Output Supply Ground Output Supply Voltage. Bypass to GND with.µf and.µf capacitors in parallel as close to the 26, 38 V CCO device as possible, with the smallest value capacitor closest to the supply pin. 27 LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when is low. 28 LVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge selected by R/F , RGB_OUT [7:] LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[7:] are latched into the next chip on the edge of selected by R/F when is high, and are held at the last state when is low. EP Exposed Pad for Thin QFN Package Only. Connect to GND. 6

7 IN+ IN- DC BALANCE/ DECODE SER-TO-PAR Functional Diagram R/F OUTEN RGB_OUT[7:] CNTL_OUT[8:] RNG RNG PLL REFCLK TIMING AND CONTROL IN+ R IB.2V LVDS RECEIVER RGB_OUT[7:].9V CCO.V CCO R IB CNTL_OUT[8:] t R t F IN- Figure. LVDS Input Bias Figure 3. Output Rise and Fall Times ODD RGB_OUT CNTL_OUT EVEN RGB_OUT CNTL_OUT t LOW t HIGH 2.V.8V RISING LATCH EDGE SHOWN (R/F = HIGH). Figure 2. Worst-Case Output Pattern Figure 4. High and Low Times 7

8 SHOWN FOR R/F = HIGH (RISING LATCH EDGE).8V 2.V t DVB t DVA RGB_OUT[7:] CNTL_OUT[8:] 2.V.8V 2.V.8V Figure 5. Synchronous Output Timing 2 SERIAL BITS SHOWN FOR R/F = HIGH IN+, IN- SERIAL-WORD N SERIAL-WORD N + t DELAY CNTL_OUT RGB_OUT PARALLEL-WORD N - PARALLEL-WORD N Figure 6. Deserializer Delay 8

9 REFCLK.8V t PLLREF TRANSITION WORD FOUND t PDD 2.V RECOVERED C HIGH IMPEDANCE HIGH IMPEDANCE RGB_OUT CNTL_OUT HIGH IMPEDANCE C STRETCH VALID DATA HIGH IMPEDANCE HIGH IMPEDANCE HIGH IMPEDANCE NOTE: R/F = HIGH Figure 7. PLL Lock to REFCLK and Power-Down Delay OUTEN OUTEN 2.V.8V t OE t OZ RGB_OUT[7:] HIGH-Z ACTIVE RGB_OUT[7:] ACTIVE HIGH-Z CNTL_OUT[8:] CNTL_OUT[8:] Figure 8. Output Enable Time Figure 9. Output Disable Time 9

10 Detailed Description The DC-balanced deserializer operates at a parallel clock frequency of 3MHz to 35MHz, deserializing video data to the RGB_OUT[7:] outputs when the data enable output is high, or control data to the CNTL_OUT[8:] outputs when is low. The video phase words are decoded using 2 overhead bits, EN and EN. Control phase words are decoded with overhead bit, EN. Encoding, performed by the MAX927 serializer, reduces EMI and maintains DC balance across the serial cable. The serial input word formats are shown in Table and Table 2. Control data inputs C to C4, each repeated over 3 serial bit times by the serializer, are decoded using majority voting. Two or three bits at the same state determine the state of the recovered bit, providing single bit-error tolerance for C to C4. The state of C5 to C8 is determined by the level of the bit itself (no voting is used). AC-Coupling Benefits AC-coupling increases the input voltage of the LVDS receiver to the voltage rating of the capacitor. Two capacitors are sufficient for isolation, but four capacitors two at the serializer output and two at the deserializer input provide protection if either end of the cable is shorted to a high voltage. AC-coupling blocks low-frequency ground shifts and common-mode noise. The MAX927 serializer can also be DC-coupled to the deserializer. Figure is the AC-coupled serializer and deserializer with two capacitors per link, and Figure is the AC-coupled serializer and deserializer with four capacitors per link. Applications Information Selection of AC-Coupling Capacitors See Figure 2 for calculating the capacitor values for AC-coupling, depending on the parallel clock frequency. The plot shows capacitor values for two- and fourcapacitor-per-link systems. For applications using less than 8MHz clock frequency, use.µf capacitors. Termination and Input Bias The IN+ and IN- LVDS inputs are internally connected to +.2V through 35kΩ (min) to provide biasing for ACcoupling (Figure ). Assuming Ω interconnect, the LVDS input can be terminated with a Ω resistor. Match the termination to the differential impedance of the interconnect. Use a Thevenin termination, providing.2v bias, on an AC-coupled link in noisy environments. For interconnect with Ω differential impedance, pull each LVDS line up to V CC with 3Ω and down to ground with 82Ω at the deserializer input (Figure and Figure ). This termination provides both differential and commonmode termination. The impedance of the Thevenin termination should be half the differential impedance of the interconnect and provide a bias voltage of.2v. Table. Serial Video Phase Word Format EN EN S S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 S4 S5 S6 S7 Bit is the LSB and is deserialized first. EN[:] are encoding bits. S[7:] are encoded symbols. Table 2. Serial Control Phase Word Format E N C C C C C C C2 C2 C2 C3 C3 C3 C4 C4 C4 C5 C6 C7 C8 Bit is the LSB and is deserialized first. C[8:] are the mapped control inputs.

11 RGB_IN CNTL_IN DE_IN INPUT LATCH DC BALANCE/ ENCODE PAR-TO-SER OUT CMF 3Ω * * 82Ω V CC 3Ω 82Ω IN DC BALANCE/ DECODE SER-TO-PAR R/F OUTEN RGB_OUT CNTL_OUT PCLK_IN RNG RNG PLL TIMING AND CONTROL RNG RNG PLL TIMING AND CONTROL REFCLK MAX927 CERAMIC RF SURFACE-MOUNT CAPACITOR Ω DIFFERENTIAL STP CABLE Figure. AC-Coupled Serializer and Deserializer with Two Capacitors per Link *CAPS CAN BE AT EITHER END. V CC RGB_IN CNTL_IN DE_IN INPUT LATCH DC BALANCE/ ENCODE PAR-TO-SER OUT CMF 3Ω 82Ω 3Ω 82Ω IN DC BALANCE/ DECODE SER-TO-PAR R/F OUTEN RGB_OUT CNTL_OUT PCLK_IN RNG RNG PLL TIMING AND CONTROL RNG RNG PLL TIMING AND CONTROL REFCLK MAX927 CERAMIC RF SURFACE-MOUNT CAPACITOR Ω DIFFERENTIAL STP CABLE Figure. AC-Coupled Serializer and Deserializer with Four Capacitors per Link

12 Input Frequency Detection A frequency-detection circuit detects when the LVDS input is not switching. When not switching, all outputs except are low, is high, and follows REFCLK. This condition occurs, for example, if the serializer is not driving the interconnect or if the interconnect is open. Frequency Range Setting (RNG[:]) The RNG[:] inputs select the operating frequency range of the and the transition time of the outputs. Select the frequency range that includes the MAX927 serializer PCLK_IN frequency. Table 3 shows the selectable frequency ranges and the corresponding data rates and output transition times. Power Down Driving low puts the outputs in high impedance and stops the PLL. With.3V and all LVTTL/LVCMOS inputs.3v or V CC -.3V, the supply current is reduced to less than 5µA. Driving high initiates lock to the local reference clock (REFCLK) and afterwards to the serial input. Lock and Loss of Lock () When is driven high, the PLL begins locking to REFCLK, drives from high impedance to high and the other outputs from high impedance to low except. outputs REFCLK while the PLL is locking to REFCLK. Locking to REFCLK takes a maximum of 6,385 REFCLK cycles. When locking to REFCLK is complete, the serial input is monitored for a transition word. When a transition word is found, is driven low indicating valid output data, and the parallel rate clock recovered from the serial input is output on. is stretched on the change from REFCLK to recovered clock (or vice versa). Table 3. Frequency Range Programming RNG RNG PARALLEL C (MHz) SERIAL DATA RATE (Mbps) 3 to 7 6 to 4 7 to 5 4 to 3 OUTPUT TRANSITION TIME Slow 5 to 35 3 to 7 Fast CAPACITOR VALUE (nf) AC-COUPLING CAPACITOR VALUE vs. PARALLEL C FREQUENCY FOUR CAPACITORS PER LINK TWO CAPACITORS PER LINK PARALLEL C FREQUENCY (MHz) Figure 2. AC-Coupling Capacitor Values vs. Clock Frequency of 8MHz to 35MHz If a transition word is not detected within 2 2 cycles of, is driven high and the other outputs except are driven low. REFCLK is output on and the deserializer continues monitoring the serial input for a transition word. See Figure 7 for the synchronization timing diagram. Output Enable (OUTEN) and Busing Outputs The outputs of two s can be bused to form a 2: mux with the outputs controlled by the output enable. Wait 3ns between disabling one deserializer (driving OUTEN low) and enabling the second one (driving OUTEN high) to avoid contention of the bused outputs. OUTEN controls all outputs. Rising or Falling Output Latch Edge (R/F) The has a selectable rising or falling output latch edge through a logic setting on R/F. Driving R/F high selects the rising output latch edge, which latches the parallel output data into the next chip on the rising edge of. Driving R/F low selects the falling output latch edge, which latches the parallel output data into the next chip on the falling edge of. The output-latch-edge polarity does not need to match the MAX927 serializer inputlatch-edge polarity. Select the latch-edge polarity required by the chip being driven by the. 2

13 Staggered and Transition Time Adjusted Outputs RGB_OUT[7:] are grouped into three groups of six, with each group switching about ns apart in the video phase to reduce EMI and ground bounce. CNTL_OUT[8:] switch during the control phase. Output transition times are slower in the 3MHz-to-7MHz and 7MHz-to-5MHz ranges and faster in the 5MHz-to- 35MHz range. Data Enable Output () The deserializes video and control data at different times. Control data is deserialized during the video blanking time. high indicates that video data is being deserialized and output on RGB_OUT[7:]. low indicates that control data is being deserialized and output on CNTL_OUT[8:]. When outputs are not being updated, the last data received is latched on the outputs. Figure 3 shows the timing. Power-Supply Circuits and Bypassing There are separate on-chip power domains for digital circuits and LVTTL/LVCMOS inputs (V CC supply and GND), outputs (V CCO supply and V CCO GND), PLL (V CCPLL supply and V CCPLL GND), and the LVDS input (V CCLVDS supply and V CCLVDS GND). The grounds are isolated by diode connections. Bypass each V CC, V CCO, V CCPLL, and V CCLVDS pin with high-frequency, surface-mount ceramic.µf and.µf capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. The outputs are powered from V CCO, which accepts a.7v to 3.6V supply, allowing direct interface to inputs with.8v to 3.3V logic levels. Cables and Connectors Interconnect for LVDS typically has a differential impedance of Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. Board Layout Separate the LVTTL/LVCMOS outputs and LVDS inputs to prevent crosstalk. A four-layer PCB with separate layers for power, ground, and signals is recommended. CONTROL DATA VIDEO DATA CONTROL DATA CNTL_OUT RGB_OUT = OUTPUT DATA HELD TIMING SHOWN FOR R/F = HIGH (RISING OUTPUT LATCH EDGE) Figure 3. Output Timing 3

14 ESD Protection The ESD tolerance is rated for the Human Body Model, Machine Model, and ISO 65. ISO 65 specifies ESD tolerance for electronic systems. MΩ R D.5kΩ The Human Body Model discharge components are C S = pf and R D =.5kΩ (Figure 4). The ISO 65 discharge components are C S = 33pF and R D = 2kΩ (Figure 5). The Machine Model discharge components are C S = 2pF and R D = Ω (Figure 6). R D Ω HIGH- VOLTAGE DC SOURCE CHARGE-CURRENT- LIMIT RESISTOR C S pf DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST HIGH- VOLTAGE DC SOURCE CHARGE-CURRENT- LIMIT RESISTOR C S 2pF DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 4. Human Body ESD Test Circuit Figure 6. Machine Model ESD Test Circuit. 5Ω TO Ω R D 2kΩ HIGH- VOLTAGE DC SOURCE CHARGE-CURRENT- LIMIT RESISTOR C S 33pF DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 5. ISO 65 Contact Discharge ESD Test Circuit PROCESS: CMOS Chip Information Package Information For the latest package outline information and land patterns, go to PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 48 LQPF C TQFN T

15 REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 3 2/8 Corrected typo (REF_IN should be REFCLK) in Figure 4 5/8 Corrected LQFP package, added Machine Model ESD, and corrected diagrams, 2, 6, 7,,, /9 Added automotive qualified part to Ordering Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.