SEFUW workshop. Feb 17 th 2016
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1 SEFUW workshop Feb 17 th 2016
2 NanoXplore overview French fabless company with two activities FPGA core IP High reliable FPGA devices Lead by FPGA industry experts with more than 25 years track records Has developed FPGA core from 1µm down to 28nm process Already developed 750k LUTs FPGA in 65nm and 500k LUTs FPGA core in 28nm Technology has been used in emulation systems for 20 years
3 BRAVE project overview ESA / CNES project to develop a new generation of rad hard FPGAs Well defined consortium ESA and CNES NanoXplore as project leader STM as foundry and IP provider Airbus DS and TAS as alpha users Based on NanoXplore ultra dense patented FPGA architecture and STM 65nm space process NXT 35 NG-MEDIUM is our first rad-hard FPGA Fully ITAR free
4 NG-MEDIUM Overview S based FPGA Four inputs LUT Embedded Embedded Multiple clock domains Programmable IO banks Radiation hardened by design Specifically designed for space applications No software level mitigation SEE immune for LEO/GEO environment Meet QML-V qualification flow for two packages CQFP-352 LGA-625
5 NG-MEDIUM Summary Device NG-MEDIUM Capacity Equivalent System Gates ASIC Gates Modules Register LUT Carry Embedded Core Blocks (48K-bits) 56 Core Bits (K = 1024) 2688 K Core Register File (64 x 16-bits) 168 Core Register File Bits 168 K Embedded 112 Clocks 32 Embedded Serial Link SpaceWire 400Mbps 1 I/Os I/O Banks 13 User I/Os LGA MQFP I/O PHY DDR 16 SpaceWire 16
6 NG-MEDIUM Architecture CKG I/O BANK COMPLEX - 30 I/O BANK COMPLEX - 30 I/O BANK COMPLEX - 30 I/O BANK COMPLEX - 30 CKG I/O BANK SIMPLE - 22 Bit Stream Interface 36 I/O BANK SIMPLE X ALU LUT LUT 408 LUT 384 DFF 32x16-bits Register File 32x16-bits Register File LUT LUT I/O BANK SIMPLE - 30 I/O BANK SIMPLE - 30 I/O BANK SIMPLE - 30 CKG I/O BANK COMPLEX - 30 I/O BANK COMPLEX - 30 I/O BANK COMPLEX - 30 I/O BANK COMPLEX - 30 CKG
7 NG-FPGA-MEDIUM Characteristics Power supply Core: 1,2V ±10% IOS: 1.5V ±10% or 1.8V ±10% or 2.5V ±10% or 3.3V ±10% Performance 250MHz Logic 333MHz 800Mbps I/O Temperature -55ºC to +125ºC ESD HBM > 2000V for all IOB, Control IO and power supplies
8 Embedded Implements arithmetic functions Multiply Multiply-add/subtract Multiply-accumulate Single / Dual mode 18 x 18 multiplication 24 x 24 multiplication Possibility to cascade multiple to implement high performance algorithms
9 Clock distribution Four clock generators PLL Post scaler Waveform generator PVT Oscillator Hierarchical clock distribution Core clocks Zone clocks I/O bank clocks
10 IO system Programmable I/O buffer Single ended Differential Resistive termination Standard Type Supply Drive Speed Special considerations Notes LVCMOS 3.3V SE 3.3 V 2 6 ma 200Mb/s LVCMOS 2.5V SE 2.5 V 2 5 ma 200Mb/s LVCMOS 1.8V SE 1.8 V 3.5 ma 600Mb/s LVCMOS 1.5V SE 1.5 V 3 ma 600Mb/s PCI/PCI-X SE 3.3 V 30 ma 200Mb/s SSTL 2.5V I/II SE 2.5 V 15/22 ma 600Mb/s SSTL 3.3V I/II SE 3.3 V 20/30 ma 600Mb/s HSTL 2.5V I/II SE 2.5 V 20/30 ma 600Mb/s HSTL 1.8V I/II SE 1.8 V 13/16 ma 800Mb/s Controlled Source Impedance DDR2 HSTL 1.5V I/II SE 1.5 V 11/16 ma 800Mb/s Controlled Source Impedance DDR3 GTL/GTL+ SE 3.3 V 24 ma 200Mb/s Sink only / External load LVPECL 2.5V DIF 2.5 V 18 ma 800Mb/s Source only / External load LVDS 2.5V DIF 2.5 V 18 ma 800Mb/s Multiple Banks One bank has same supply voltage 8 x 30 I/Os complex banks 3 x 30 I/Os simple banks 2 x 22 I/Os simple banks
11 Complex bank features DDR2 / DDR3 800Mb/s physical interface SpaceWire physical interface
12 Bit stream management Download interfaces: JTAG SpaceWire (up to 400Mbps). Slave // 8-bits Slave // 16-bits Master / Slave Dump (compatible AT69170E) Master SPI Advanced bit stream protection mechanisms Frame Integrity Check (FIC) Configuration Memory Integrity Check (CMIC) Seamless external SPI memory integration Auto powering by FPGA Built in SEL monitoring and mitigation
13 Hardening overview SEL immune ST 65nm technology with PDK space design rules provides immunity at 60MeV/mg cm2, 125ºC, 1.32V SEL TCAD simulations performed on IO buffers SEU / SET immune for LEO / GEO applications Cell level hardening by design: Implement a certain level redundancy Optimize layout to reduce charge collection on critical nodes Validate susceptibility with cross section simulation tools Functional level hardening: Use error detection and correction functions Implement filters on critical signals (i.e. clock, reset) System level: Check bit stream integrity with signatures (FIC) Check configuration integrity at run time (CMIC)
14 Programming software: NanoXmap overview NanoXplore rad-hard FPGA offering is supported by its own software NanoXmap Fully integrated flow from synthesis down to bit stream generation and reports (timing, LUTs utilization etc) NanoXmap is already released and meet the initial expectations Utilization rate >80% Best compilation time of the market Support Verilog IEEE /2001 and VHDL IEEE / 2008 Text RTL Project Setup Synthesis Physical Implementation Backend Verilog VHDL Timing Constraints (SDC) I/O Placement Reports & Models Bit Stream Simulation Formal proof Static timing analysis LUTs utilization
15 NG-MEDIUM roadmap NanoXmap: Q Evaluation kit: Q Samples: Q QML-V eq flow: Q QML-Q eq flow: Q4 2017
16 Conclusion NG-MEDIUM is the first rad-hard FPGA of a well identified roadmap NG-MEDIUM in 2016 NG-LARGE in 2017 NG-ULTRA in 2018 NG-MEDIUM has validated NanoXplore design methodology and software tools for all future high performance rad-hard FPGA For more information feel free to contact us! Edouard Lepape: elepape@nanoxplore.com
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