Video Input Daughter Card Reference Manual

Transcription

1 Video Input Daughter Card Reference Manual 101 Innovation Drive San Jose, CA (408) Document Version 1.0 Document Date November 2006

2 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Part Number MNL-VDC ii Altera Corporation

3 Contents About This Manual... v Chapter 1. Introduction Key Features Functional Overview Basic Operation Chapter 2. Board Description Board Outline I2C Addressing Decoder Output Mapping Altera Corporation iii

4 Contents Video Input Daughter Card iv Altera Corporation

5 About This Manual This reference manual describes the board-level operations of the Video Input Daughter Card for the Altera Santa Cruz interface. The DSP Development Kit, Cyclone II Editions (EP2C35 and EP2C70), base boards use this peripheral add-in daughter card to support the Santa Cruz interface connectors. The card enables engineers and developers to incorporate live video into their designs.it also enables evaluators of the designs to create software on the base boards for expanding their application and system in a variety of ways. References For further information about products named in this document, please refer to the following related documents: Texas Instruments TVP5146 Data Sheet Altera Cyclone II Data Sheet Altera Santa Cruz Interface Specification Altera Cyclone II Evaluation Board f The document revision history in Table 2 1 shows the current version of this document. To ensure that you have the most up-to-date information on this product, refer to the readme file on the provided CD_ROM for late-breaking information that is not available in this document. Table 2 1. Document Revision History Date November 2006 Description Initial publication of the Video Input Reference Manual, version 1.0. How to Find Information The following methods enable you to quickly find information in this Portable Document Format (PDF) type document: Search the contents by using the Adobe Acrobat or Reader Edit/Find command or click on the binoculars/search toolbar icon. The Bookmarks window serves as an additional table of contents. Click on a topic to jump to that section in the document. Thumbnail icons in the Pages window provide miniature previews of each page and provide a link to the pages. Altera Corporation November 2006 v Video Input Daughter Card

6 About This Manual Within the text, hypertext links, highlighted in green, enable you to jump to related information. How to Contact Altera To get help regarding this product, use the following contact information: Altera Corporation 101 Innovation Drive San Jose, California, USA For the most up-to-date information about Altera products, go to the Altera world-wide web site at For technical support on this product, go to For additional information about Altera products, consult the sources shown below. Information Type USA & Canada All Other Locations Technical support (800) 800-EPLD (3753) (7:00 a.m. to 5:00 p.m. Pacific Time) :00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time Product literature Altera literature services Non-technical customer service (800) :00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time FTP site ftp.altera.com ftp.altera.com Typographic Conventions This document uses the typographic conventions shown below. Visual Cue Bold Type with Initial Capital Letters bold type Italic Type with Initial Capital Letters Meaning Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: f MAX, \qdesigns directory, d: drive, chiptrip.gdf file. Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design. vi Reference Manual Altera Corporation Video Input Daughter Card November 2006

7 About This Manual Visual Cue Italic type Initial Capital Letters Subheading Title Courier type Meaning Internal timing parameters and variables are shown in italic type. Examples: t PIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file. Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: Typographic Conventions. Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. 1., 2., 3., and a., b., c., etc. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention. c w r f The caution indicates required information that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process. The warning indicates information that should be read prior to starting or continuing the procedure or processes The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. Altera Corporation Reference Manual vii November 2006 Video Input Daughter Card

8 About This Manual viii Reference Manual Altera Corporation Video Input Daughter Card November 2006

9 1. Introduction The Altera Video Input Daughter Card (Figure 1 1) is an add-on peripheral development platform for Altera Development Kit boards. The daughter card enables users to incorporate live video into the applications developed on the Cyclone II family of FPGAs. Figure 1 1. Video Input Daughter Card The following topics introduce the card, present its key features, including a block diagram of the circuit board, and describe basic operations of the card: Key Features Functional Overview Basic Operation Key Features The video input daughter card, which incorporates two Texas Instruments TVP5146 video decoders suitable for a wide variety of video applications, includes the following key features: Two independent 10-bit Texas Instruments TVP5146 video decoders (Table 1 1) NTSC/PAL/SECAM video input support I2C-configurable control registers Two RCA input connectors Direct connection to Santa Cruz interface headers On-board power regulators for direct connection to the Santa Cruz interface Altera Corporation 1 1 November 2006

10 Introduction Table 1 1. Daughter Card Component References Board Reference Device Description U1, U41 10-Bit high-quality, single-chip, digital video decoder - NTSC/PAL/SECAM Manufacturer Name Part Number Website Texas Instruments TVP Functional Overview Figure 1 2 shows the block diagram of the TVP5416 Dual Decoder Daughter Card. The daughter card accepts NTSC, PAL, or SECAM video on two independent inputs, J1 and J41, and produces digital-encoded video outputs to the Santa Cruz interface connectors J3, J4,and J5. Figure 1 2. Block Diagram J1 J41 1.8V Supply Video In CLK1 TVP5416 U1 Video In Y0:Y9 HSYNC VSYNC J4 CLK2 J5 Y0:Y9 HSYNC VSYNC TVP5416 U41 I 2 C Bus J3 TP43 TP41 TP42 The daughter card provides two entirely independent channels. Each of the two decoders uses a separate MHz crystal oscillator and initializes from a separate I2C address via an I2C interface (J5). By incorporating two totally independent channels, the daughter card significantly increases the flexibility of applications. For example, the two independent channels enable the use of picture-in-picture and surveillance functions or automotive front-and-rear camera applications. The card imposes no additional power requirements on the designer. The Santa Cruz interface connectors supply power to the card directly and on-board voltage regulators provide the 1.8 -volt core voltage required by the TVP5146 devices. 1 2 Reference Manual Altera Corporation Video Input Daughter Card November 2006

11 Introduction Basic Operation The video input daughter card is a peripheral device used by the Altera Cyclone II DSP series of FPGA development platforms. After installation of the daughter card on the development platform and downloading one of the hardware reference designs provided, the FPGA initializes the decoders via the I2C interface. When live video from a DVD or camera connected to the J1 or J41 RCA-type connector appears at the daughter card input, the daughter card produces encoded video output in digital format on the Santa Cruz interface connector. 1 It is important to understand that this daughter card is a peripheral device to the FPGA development platform and that it is the Cyclone II FPGA that implements the I2C controller and video processing functions. The Video Input Daughter Card Development Kit includes an installation CD with reference designs for the DSP Development Kit, Cyclone II Edition (either EP2C35 or EP2C70). Altera Corporation Reference Manual 1 3 November 2006 Video Input Daughter Card

12 Introduction 1 4 Reference Manual Altera Corporation Video Input Daughter Card November 2006

13 2. Board Description This chapter provides a description of the Video Input Daughter Card within the following topics: Board Outline I2C Addressing Decoder Output to Santa Cruz Mapping Board Outline Figure 2 1 shows the top and bottom board outlines for the daughter card. Figure 2 1. Top and Bottom Board Outlines TOP BOTTOM Altera Corporation 2 1 November 2006

14 Board Description I2C Addressing When a reference design is loaded, an I2C controller in the FPGA initializes the TVP5146 decoders. In typical dual-channel applications, both channels would load the same configuration to enable the video interface connectors to accept input from two video sources of the same type. However, because the decoders are totally independent, this is not a requirement with the video input daughter card. Each decoder, marked U1 and U41 on the board and schematics, includes the base address (Table 2 1) hardwired, except for the least significant address bit (LSB). The LSB is strapped HIGH for U1 via R5 and strapped LOW for U41 via R44. The decoder captures the LSB via the I2CA pin (pin 37) at reset. Table 2 1. Decoder Base Addresses Designator Video Input Channel Base I2C Address U1 J1 0xBA U41 J41 0xB8 The TVP5146 decoder has up to 256 addressable control registers, many of them unreserved. Most of these do not require initialization in normal applications. 1 For more information on programming the decoder, please refer to the TVP5146 data sheet from Texas Instruments. Decoder Output Mapping The Santa Cruz interface specifies three connectors, J1, J2, and J3 for daughter card interfacing. The Dual Decoder Daughter Card uses the Santa Cruz interface to output 10-bit digital video. The Santa Cruz interface specifies three connectors, J1, J2, and J3 to connect a daughter card to the connections. The tables below show the mapping of pins from the two TVP5146 decoders to the Santa Cruz connectors. The Santa Cruz connector specification can be downloaded from: ftp://ftp.altera.com/outgoing/download/support/ip/processors/nios 2/nios_cyclone_1c20/nios_santa_cruz_connector_spec.pdf 2 2 Reference Manual Altera Corporation Video Input Decoder Daughter Card November 2006

15 Board Description Table 2 2 shows how the J3 connector pins map to the interface and the daughter card. Table 2 2. J3 Connector Pins Pin Number Daughter Card Mapping Santa Cruz Mapping 1 Ground Ground 2 Not used VCC_5 3 U41-Pin 72, HS/CS.GPIO Proto IO 40 4 U41-Pin 73, VS/VBLK/GPIO Proto IO 29 5 U41-Pin 43, Y9 Proto IO 30 6 U41-Pin 44, Y8 Proto IO 31 7 U41-Pin 45, Y7 Proto IO 32 8 U41-Pin 46, Y6 Proto IO 33 9 U41-Pin 47, Y5 Proto IO U41-Pin 50, Y4 Proto IO U41-Pin 51, Y3 Proto IO U41-Pin 52, Y2 Proto IO U41-Pin 53, Y1 Proto IO U41-Pin 54, Y0 Proto IO 39 Table 2 3 shows how the J4 connector pins map to the interface and the daughter card. Table 2 3. J4 Connector Pins (Part 1 of 2) Pin Number Daughter Card Mapping Santa Cruz Mapping 1 Not used 2 Ground Ground 3 Not used 4 Ground Ground Volts 3.3 Volts 6 Ground Ground Volts 3.3 Volts 8 Ground Ground 9 Not used 10 Ground Ground 11 U1-Pin 40, Data clock Clock In1 Altera Corporation Reference Manual 2 3 November 2006 Video Input Decoder Daughter Card

16 Board Description Table 2 3. J4 Connector Pins (Part 2 of 2) Pin Number Daughter Card Mapping Santa Cruz Mapping 12 Ground Ground 13 U41-Pin 40, Data clock Clock In 2 14 Ground Ground Volts 3.3 Volts 16 Ground Ground Volts 3.3 Volts 18 Ground Ground Volts 3.3 Volts 20 Ground Ground Table 2 4 shows how the J5 connector pins map to the interface and the daughter card. Table 2 4. J5 Connector Pins (Part 1 of 2) Pin Number Daughter Card Mapping Santa Cruz Mapping 1 Resetz Resetz 2 Ground Ground 3 U1-Pin 70, C0 Proto IO 0 4 U1-Pin 69, C1 Proto IO 1 5 U1-Pin 66, C2 Proto IO 2 6 U1-Pin 65, C3 Proto IO 3 7 U1-Pin 64, C4 Proto IO 4 8 U1-Pin 63, C5 Proto IO 5 9 U1-Pin 60, C6 Proto IO 6 10 U1-Pin 59, C7 Proto IO 7 11 U1-Pin 58, C8 Proto IO 8 12 U1-Pin 57, C9 Proto IO 9 13 U1-Pin 71, FID/GPIO Proto IO U1-Pin 36, AVID/GPIO Proto IO U1-Pin 37, GLCO/I2CA Proto IO U1-Pin 30, INTREQ Proto IO U1-Pin 72, HS/CS/GPIO Proto IO U1-Pin 73, VS/VBLK/GPIO Proto IO Ground Ground 2 4 Reference Manual Altera Corporation Video Input Decoder Daughter Card November 2006

17 Board Description Table 2 4. J5 Connector Pins (Part 2 of 2) Pin Number Daughter Card Mapping Santa Cruz Mapping 20 Not Used Not Used 21 U1-Pin 54, Y0 Proto IO Ground Ground 23 U1-Pin 53, Y1 Proto IO Ground Ground 25 U1-Pin 52, Y2 Proto IO Ground Ground 27 U1-Pin 51, Y3 Proto IO U1-Pin 50, Y4 Proto IO U1-Pin 47, Y5 Proto IO Ground Ground 31 U1-Pin 46, Y6 Proto IO U1-Pin 45, Y7 Proto IO U1-Pin 44, Y8 Proto IO Ground Ground 35 U1-Pin 54, Y0 Proto IO I2C Data U1 & U41 SDA Proto IO NOT USED Proto IO Pulled down Card SELz 39 I2C Clock U1 & U41 SCL Proto IO Ground Ground Altera Corporation Reference Manual 2 5 November 2006 Video Input Decoder Daughter Card

18 Board Description 2 6 Reference Manual Altera Corporation Video Input Decoder Daughter Card November 2006