EVAL6470PD. Fully integrated stepper motor driver mounting the L6470 in a high power PowerSo package. Description. Features

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1 Fully integrated stepper motor driver mounting the L6470 in a high power PowerSo package Description Data brief AM39v The EVAL6470PD demonstration board is a fully integrated microstepping motor driver. In combination with the STEVAL-PCC009V communication board and SPIN evaluation software, the board allows the engineer to investigate all the features of the L6470 device. In particular, the board can be used to check the voltage mode driving and to regulate the L6470 parameters in order to fit the application requirements. The 4-layer layout and the PowerSO package allow the top thermal performance to be obtained. The EVAL6470PD supports the daisy chain configuration making it suitable for the evaluation of the L6470 in multi motor applications. Features Voltage range from 8 V to 45 V Phase current up to 3 A r.m.s. Dual SPI connector (daisy chain configuration suitable) SW input FLAG and BUSY LED indicators Adjustable supply voltage compensation High thermal performance (R thj-a C/W typical) Suitable for use in combination with the STEVAL-PCC009V March 05 DocID0606 Rev 3 / For further information contact your local STMicroelectronics sales office.

2 EVAL6470PD Table. EVAL6470PD specifications Parameter Value Supply voltage () 8 to 45 V Maximum output current (each phase) 3 Ar.m.s. Logic supply voltage (VREG) Externally supplied: 3.3 V internally supplied: 3 V typical Logic interface voltage (VDD) Externally supplied: 3.3 V or 5 V internally supplied: VREG Low level logic input voltage 0V High level logic input voltage VDD() Operating temperature -5 to +5 C L6470PD thermal resistance junction to ambient C/W typical. All logic inputs are 5 V tolerant. Figure. Jumper and connector location AM330v / DocID0606 Rev 3

3 Table. Jumper and connector description Name Type Function M Power supply Motor supply voltage M Power output Bridge A outputs M3 Power output Bridge B outputs CN SPI connector Master SPI CN SPI connector Slave SPI CN3 NM connector OSCIN and OSCOUT pins CN4 NM connector External switch input TP () Test point Motor supply voltage test point TP (VDD) Test point Logic interface supply voltage test point TP3 (VREG) Test point Logic supply voltage/l6470 internal regulator test point TP5 (GND) Test point Ground test point TP6 (GND) Test point Ground test point TP8 (STCK) Test point Step clock input test point TP9 (STBY/RES) Test point Standby/reset input test point TP0 (FLAG) Test point FLAG output test point TP (BUSY/SYNC) Test point BUSY/SYNC output test point Table 3. Master SPI connector pinout (J0) Pin number Type Description Open drain output L6470 BUSY/SYNC output Open drain output L6470 FLAG output 3 Ground Ground 4 Supply EXT_VDD (can be used as external logic power supply) 5 Digital output SPI Master In Slave Out signal (connected to the L6470 SDO output through the daisy chain termination jumper JP) 6 Digital input SPI serial clock signal (connected to L6470 CK input) 7 Digital input SPI Master Out Slave In signal (connected to L6470 SDI input) 8 Digital input SPI slave select signal (connected to L6470 CS input) 9 Digital input L6470 step-clock input 0 Digital input L6470 STBY/RST input DocID0606 Rev 3 3/

4 EVAL6470PD Table 4. Slave SPI connector pinout (J) Pin number Type Description Open drain output L6470 BUSY/SYNC output Open drain output L6470 FLAG output 3 Ground Ground 4 Supply EXT_VDD (can be used as external logic power supply) 5 Digital output SPI Master In Slave Out signal (connected to pin 5 of J0) 6 Digital input SPI serial clock signal (connected to L6470 CK input) 7 Digital input SPI Master Out Slave In signal (connected to L6470 SDO output) 8 Digital input SPI slave select signal (connected to L6470 CS input) 9 Digital input L6470 step-clock input 0 Digital input L6470 STBY/RST input 4/ DocID0606 Rev 3

5 Figure. EVAL6470PD - schematic VDD EXT_VDD SDO M A A CN BUSY FLAG EXT_VDD 3 4 EXT_VDD MISO 5 6 CK SDO 7 8 ncs STCK 9 0 STBY_RESET CN BUSY FLAG 3 4 MISO 5 6 CK SDI 7 8 ncs STCK 9 0 STBY_RESET B B VREG TP JP3 GND MISO SPI_IN SPI_OUT STBY STCK Application reference VREG VDD M3 M TP9 TP8 VREG TP3 VDD TP C8 0nF/6V OPTION R 3K6 JP JP C7 0uF/6.3V C6 00nF/6.3V C5 47uF/6.3V C4 00nF/6.3V D + CA 00uF/63V 3 BAV99 3 TR 00k VDD 00nF/50V 00nF/50V C3 0nF/50V VREG CN3 N.M. C6 C5 C4 C + C 00uF/63V U OSCIN OSCOUT 00nF/50V 00nF/50V VDD OUTA OUTA 3 OSCIN 0 OSCOUT OUTA 35 OUTA 36 R4 39K ADCIN SW STCK STBY_RESET FLAG BUSY ncs CK SDI SDO GND GND TP5 B 3 B B PGND 6 B PGND 9 5 A AGND 34 A 33 A 5 A 4 CP 3 DGND 8 VBOOT 4 E_PAD VREG 9 VDD 4 37 R 8K R5 39K R3 39K L6470 ADCIN SW 8 7 OUTB 7 OUTB 8 STCK STBY_RES FLAG BUSY_SYNC OUTB 0 OUTB CS CK SDI SDO C nf/6.3v C0 00pF/6.3V C9 00pF/6.3V TP6 C 3.3nF/6.3V D BZX585-B3V6 SW R8 0K CN4 SW C3 0nF/6.3V TP0 TP FLAG BUSY VDD VDD DL DL R6 R7 FLAG BUSY N.M AM9v DocID0606 Rev 3 5/

6 EVAL6470PD Table 5. EVAL6470PD - bill of material Index Quantity Reference Value Package CN Pol. IDC male header vertical 0 poles (black) CON-FLAT- 5 x - 80 M CN Pol. IDC male header vertical 0 poles (gray) CON-FLAT- 5 x - 80 M 3 CN3, CN4 N.M. STRIP54P-M- 4 CA 00 µf/63 V (option) CAPE-R0HXX-P5 5 C 00 µf/63 V CAPES-R0HXX 6 4 C, C4, C5, C 00 nf/50 V CAPC C3 0 nf/50 V CAPC C4,C6 00 nf/6.3 V CAPC C5 47 µf/6.3 V CAPC-06 0 C7 0 µf/6.3 V CAPC-0805 C8 0 nf/6 V CAPC-0603 C9, C0 00 pf/6.3 V CAPC C nf/6.3 V CAPC C 3.3 nf/6.3 V CAPC C3 0 nf/6.3 V CAPC DL LED red LEDC DL LED amber LEDC D BAV99 SOT3 9 D BZX585-B3V6 SOD53 0 JP Jumper OPEN JPSO JP, JP3 Jumper CLOSED JPSO 3 M, M, M3 Screw connector poles MORSV-508-P 3 R 3.6 k RESC R 8. k RESC R3, R4, R5 39 k RESC R6, R7 470 k RESC R8 0 k RESC TP, TP, TP3, TP5, TP6, TP8, TP9, TP0, TP TPTH-RING-MM TPTH-RING-MM 9 TR 00 k TRIMM -00 x 50 x 0-64 W 30 U L6470 PowerSO36 6/ DocID0606 Rev 3

7 Figure 3. EVAL6470PD - layout (top layer) AM93v Figure 4. EVAL6470PD - layout (inner layer ) AM94v DocID0606 Rev 3 7/

8 EVAL6470PD Figure 5. EVAL6470PD - layout (inner layer 3) AM95v Figure 6. EVAL6470PD - layout (bottom layer AM96v 8/ DocID0606 Rev 3

9 Thermal data Figure 7. Thermal impedance graph Zth 0 8 Zth ( C/W) Time (seconds) AM337v DocID0606 Rev 3 9/

10 Revision history EVAL6470PD Revision history Table 6. Document revision history Date Revision Changes 3-Dec-0 Initial release. 3-May-0 6-Mar-05 3 Updated: Figure, Figure, Figure 3, Figure 4, Figure 5, Figure 6. Updated TP9 (STBY/RES) function in Table ; Updated pin and pin 0 description both in Table 3 and in Table 4. Updated Table 5: EVAL6470PD - bill of material. Replaced dspin by SPIN in Section : Description on page. Removed Figure 3. EVAL6470PD - Layout (silk screen) from page 7. Minor modifications throughout document. 0/ DocID0606 Rev 3

11 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 05 STMicroelectronics All rights reserved DocID0606 Rev 3 /

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