(Function Explanation, Program Fundamentals) Mitsubishi Programmable Logic Controller

Transcription

1 Basic Model QCPU(Q Mode) User's Manual (Function Explanation, Program Fundamentals) Mitsubishi Programmable Logic Controller

2 SAFETY INSTRUCTIONS (Always read these instructions before using this equipment.) When using Mitsubishi equipment, thoroughly read this manual and the associated manuals introduced in this manual. Also pay careful attention to safety and handle the module properly. These SAFETY PRECAUTIONS classify the safety precautions into two categories: "DANGER" and "CAUTION".! DANGER Indicates that incorrect handling may cause hazardous conditions, resulting in death or severe injury.! CAUTION Indicates that incorrect handling may cause hazardous conditions, resulting in medium or slight personal injury or physical damage. Note that the! CAUTION level may lead to a serious consequence according to the circumstances. Always follow the instructions of both levels because they are important to personal safety. Please save this manual to make it accessible when required and always forward it to the end user. [Design Precautions]! DANGER Install a safety circuit external to the PLC that keeps the entire system safe even when there are problems with the external power supply or the PLC module. Otherwise, trouble could result from erroneous output or erroneous operation. (1) Outside the PLC, construct mechanical damage preventing interlock circuits such as emergency stop, protective circuits, positioning upper and lower limits switches and interlocking forward/reverse operations. (2) When the PLC detects the following problems, it will stop calculation and turn off all output in the case of (a). In the case of (b), it will stop calculation and hold or turn off all output according to the parameter setting. (a) The power supply module has over current protection equipment and over voltage protection equipment. (b) The PLC CPUs self-diagnostic functions, such as the watchdog timer error, detect problems. In addition, all output will be turned on when there are problems that the PLC CPU cannot detect, such as in the I/O controller. Build a fail safe circuit exterior to the PLC that will make sure the equipment operates safely at such times. Refer to " LOADING AND INSTALLATION" in Basic Model QCPU (Q Mode) User s Manual (Hardware Design, Maintenance and Inspection) for example fail safe circuits. (3) Output could be left on or off when there is trouble in the outputs module relay or transistor. So build an external monitoring circuit that will monitor any single outputs that could cause serious trouble. A - 1 A - 1

3 [Design Precautions]! DANGER When overcurrent which exceeds the rating or caused by short-circuited load flows in the output module for a long time, it may cause smoke or fire. To prevent this, configure an external safety circuit, such as fuse. Build a circuit that turns on the external power supply when the PLC main module power is turned on. If the external power supply is turned on first, it could result in erroneous output or erroneous operation. When there are communication problems with the data link, refer to the corresponding data link manual for the operating status of each station. Not doing so could result in erroneous output or erroneous operation. When connecting a peripheral device to the CPU module or connecting a personal computer or the like to the intelligent function module to exercise control (data change) on the running PLC, configure up an interlock circuit in the sequence program to ensure that the whole system will always operate safely. Also before exercising other control (program change, operating status change (status control)) on the running PLC, read the manual carefully and fully confirm safety. Especially for the above control on the remote PLC from an external device, an immediate action may not be taken for PLC trouble due to a data communication fault. In addition to configuring up the interlock circuit in the sequence program, corrective and other actions to be taken as a system for the occurrence of a data communication fault should be predetermined between the external device and PLC CPU.! CAUTION Do not bunch the control wires or communication cables with the main circuit or power wires, or install them close to each other. They should be installed 1 mm (3.94 inch) or more from each other. Not doing so could result in noise that would cause erroneous operation. When controlling items like lamp load, heater or solenoid valve using an output module, large current (approximately ten times greater than that present in normal circumstances) may flow when the output is turned OFF to ON. Take measures such as replacing the module with one having sufficient rated current. A - 2 A - 2

4 [Installation Precautions]! CAUTION Use the PLC in an environment that meets the general specifications contained in Basic Model QCPU (Q Mode) User s Manual (Hardware Design, Maintenance and Inspection). Using this PLC in an environment outside the range of the general specifications could result in electric shock, fire, erroneous operation, and damage to or deterioration of the product. Hold down the module loading lever at the module bottom, and securely insert the module fixing hook into the fixing hole in the base module. Incorrect loading of the module can cause a malfunction, failure or drop. When using the PLC in the environment of much vibration, tighten the module with a screw. Tighten the screw in the specified torque range. Undertightening can cause a drop, short circuit or malfunction. Overtightening can cause a drop, short circuit or malfunction due to damage to the screw or module. When installing more cables, be sure that the base module and the module connectors are installed correctly. After installation, check them for looseness. Poor connections could cause an input or output failure. Completely turn off the external power supply before loading or unloading the module. Not doing so could result in electric shock or damage to the product. Do not directly touch the module's conductive parts or electronic components. Touching the conductive parts could cause an operation failure or give damage to the module. [Wiring Precautions]! DANGER Completely turn off the external power supply when installing or placing wiring. Not completely turning off all power could result in electric shock or damage to the product. When turning on the power supply or operating the module after installation or wiring work, be sure that the module's terminal covers are correctly attached. Not attaching the terminal cover could result in electric shock. A - 3 A - 3

5 [Wiring Precautions]! CAUTION Be sure to ground the FG terminals and LG terminals to the protective ground conductor. Not doing so could result in electric shock or erroneous operation. When wiring in the PLC, be sure that it is done correctly by checking the product's rated voltage and the terminal layout. Connecting a power supply that is different from the rating or incorrectly wiring the product could result in fire or damage. External connections shall be crimped or pressure welded with the specified tools, or correctly soldered. Imperfect connections could result in short circuit, fires, or erroneous operation. Tighten the terminal screws with the specified torque. If the terminal screws are loose, it could result in short circuits, fire, or erroneous operation. Tightening the terminal screws too far may cause damages to the screws and/or the module, resulting in fallout, short circuits, or malfunction. Be sure there are no foreign substances such as sawdust or wiring debris inside the module. Such debris could cause fires, damage, or erroneous operation. The module has an ingress prevention label on its top to prevent foreign matter, such as wire offcuts, from entering the module during wiring. Do not peel this label during wiring. Before starting system operation, be sure to peel this label because of heat dissipation. [Startup and Maintenance precautions]! DANGER Do not touch the terminals while power is on. Doing so could cause shock or erroneous operation. Correctly connect the battery. Also, do not charge, disassemble, heat, place in fire, short circuit, or solder the battery. Mishandling of battery can cause overheating or cracks which could result in injury and fires. Switch all phases of the external power supply off when cleaning the module or retightening the terminal or module mounting screws. Not doing so could result in electric shock. Undertightening of terminal screws can cause a short circuit or malfunction. Overtightening of screws can cause damages to the screws and/or the module, resulting in fallout, short circuits, or malfunction. A - 4 A - 4

6 [Startup and Maintenance precautions]! CAUTION The online operations conducted for the CPU module being operated, connecting the peripheral device (especially, when changing data or operation status), shall be conducted after the manual has been carefully read and a sufficient check of safety has been conducted. Operation mistakes could cause damage or problems with of the module. Do not disassemble or modify the modules. Doing so could cause trouble, erroneous operation, injury, or fire. Use a cellular phone or PHS more than 25cm (9.85 inch) away from the PLC. Not doing so can cause a malfunction. Switch all phases of the external power supply off before mounting or removing the module. If you do not switch off the external power supply, it will cause failure or malfunction of the module. Do not drop or give an impact to the battery mounted to the module. Doing so may damage the battery, causing the battery fluid to leak inside the battery. If the battery is dropped or given an impact, dispose of it without using. Before touching the module, always touch grounded metal, etc. to discharge static electricity from human body, etc. Not doing so can cause the module to fail or malfunction. [Disposal Precautions]! CAUTION When disposing of this product, treat it as industrial waste. A - 5 A - 5

7 REVISIONS The manual number is given on the bottom left of the back cover. Print Date * Manual Number Revision Aug., 21 SH (NA) 8188-A Equivalent to Japanese SH-8185-B First edition Jan., 23 SH (NA) 8188-B Equivalent to Japanese version "D" Overall reexamination Japanese Manual Version SH-8185-D This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the contents noted in this manual. 21 MITSUBISHI ELECTRIC CORPORATION A - 6 A - 6

8 INTRODUCTION Thank you for choosing the Mitsubishi Series of General Purpose Programmable Controllers. Please read this manual carefully so that equipment is used to its optimum. CONTENTS SAFETY INSTRUCTIONS...A- 1 REVISIONS...A- 6 CONTENTS...A- 7 About Manuals...A-16 How to Use This Manual...A-17 About the Generic Terms and Abbreviations...A-18 1 OVERVIEW 1-1 to Features Program Storage and Calculation Convenient Programming Devices and Instructions SYSTEM CONFIGURATION 2-1 to System Configuration QJCPU QCPU,Q1CPU Configuration of GX Developer Precaution on System Configuration Confirming the function version PERFORMANCE SPECIFICATION 3-1 to SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS 4-1 to Sequence Program Main routine program Sub-routine programs Interrupt programs Concept of Scan Time Operation Processing Initial processing I/O refresh (I/O module refresh processing) Automatic refresh of the intelligent function module END processing RUN, STOP, PAUSE Operation Processing A - 7 A - 7

9 4.5 Operation Processing during Momentary Power Failure Data Clear Processing Input/Output Processing and Response Lag Refresh mode Direct mode Numeric Values which Can Be Used in Sequence Program BIN (Binary Code) HEX (Hexadecimal) BCD (Binary Coded Decimal) Real number (floating-point data) Character String Data ASSIGNMENT OF I/O NUMBERS 5-1 to Relationship Between the Number of Stages and Slots of the Expansion Base Unit QJCPU QCPU,QO1CPU Installing Extension Base Units and Setting the Number of Stages Base Unit Assignment (Base Mode) What are I/O Numbers? Concept of I/O Number Assignment I/O numbers of main base unit,slim type main base unit and extension base unit Remote station I/O number I/O Assignment by GX Developer Purpose of I/O assignment by GX Developer Concept of I/O assignment using GX Developer Examples of I/O Number Assignment Checking the I/O Numbers ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU 6-1 to About Basic model QCPU's Memory About Program Memory About Standard ROM Executing Standard ROM Program (Boot Run) and Writing Program Memory to ROM Executing Standard ROM Program Write program memory to ROM About Standard RAM Program File Configuration GX Developer File Operation and File Handling Precautions File operation File handling precautions File capacity A - 8 A - 8

10 7 FUNCTION 7-1 to Function List Constant Scan Latch Functions Setting the Output (Y) Status when Changing from STOP Status to RUN Status Clock Function Remote Operation Remote RUN/STOP Remote PAUSE Remote RESET Remote Latch Clear Relationship of the remote operation and Basic model QCPU RUN/STOP switch Selection of Module Input Response Time (I/O Response Time) Selection of input response time of the input module/composite I/O module Selection of input response time of the high-speed input module Selection of input response time of the interrupt module Error-time Output Mode Hardware Error-time CPU Operation Mode Setting Setting the Switches of the Intelligent-Function Module Program Write during RUN of Basic Model QCPU Writing Data in the Ladder Mode during the RUN Status Multiple-User Debugging Function Multiple-user monitoring function Multiple-user simultaneous write during RUN Watchdog Timer (WDT) Self-Diagnosis Function LED display when error occurs Cancel error Failure History System Protect Password registration Remote password GX Developer system monitor LED Display Serial Communication Function (Usable with the QCPU or Q1CPU) COMMUNICATION WITH INTELLIGENT FUNCTION MODULE 8-1 to Communication Between Basic model QCPU and Q-series Intelligent Function Modules Initial setting and automatic refresh setting using GX Configurator Communication using device initial values Communication using FROM/TO instructions Communication Using The Intelligent Function Module Device Communication Using The Instructions Dedicated for Intelligent Function Modules Request of Intelligent Function Module to Basic Model QCPU Interrupt from intelligent function module A - 9 A - 9

11 9. PARAMETER LIST 9-1 to DEVICES 1-1 to Device List Internal User Devices Inputs (X) Outputs (Y) Internal relays (M) Latch relays (L) Anunciators (F) Edge relay (V) Link relays (B) Special link relays (SB) Step relays (S) Timers (T) Counters (C) Data registers (D) Link registers (W) Special link registers (SW) Internal System Devices Function devices (FX, FY, FD) Special relays (SM) Special registers (SD) Link Direct Devices (J \ ) Intelligent Function Module Devices (U \G ) Index Registers (Z) Switching between main routine/sub-routine program and interrupt program File Registers (R) Nesting (N) Pointers Interrupt Pointers (I) Other Devices SFC block device (BL) Network No. designation device (J) I/O No. designation device (U) Macro instruction argument device (VD) Constants Decimal constants (K) Hexadecimal constants (H) Real number (E) Character string ( " " ) Useful Method of Using the Devices Device initial value A - 1 A - 1

12 11 PROCESSING TIMES OF THE BASIC MODEL QCPU 11-1 to Scan Time Structure Concept of Scan Time Other Processing Times PROCEDURE FOR WRITING PROGRAMS TO BASIC MODEL QCPU 12-1 to Items to Consider when Creating Program Procedure for writing program to the Basic model QCPU OUTLINE OF MULTIPLE CPU SYSTEMS 13-1 to Features Outline of Multiple CPU Systems Differences with Single CPU Systems SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM 14-1 to System Configuration Precautions For Multiple CPU System Configuration Function versions of Basic model QCPU, Motion CPU and PC CPU module that can be used, and their mounting positions Precautions when using Q Series I/O modules and intelligent function modules Modules that have mounting restrictions Compatible GX Developers and GX Configurators Parameters that enable the use of Multiple CPU System Resetting the Multiple CPU System Processing when stop errors occur Reducing the time required for Multiple CPU System processing ALLOCATING MULTIPLE CPU SYSTEM I/O NUMBERS 15-1 to Concept behind Allocating I/O Numbers I/O modules and Intelligent function module I/O numbers I /O number of Basic model QCPU, Motion CPU and PC CPU module Setting of Control CPUs with GX Developer COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM 16-1 to Automatic Refresh of CPU Shared Memory Communication with Multiple CPU Instructions and Intelligent Function Module Devices Interactive Communications between The Basic model QCPU and Motion CPU Control commands from the Basic model QCPU to the Motion CPU (Motion dedicated instructions) Reading and writing device data(between Multiple CPU communication dedicated instructions) CPU Shared Memory A - 11 A - 11

13 17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES 17-1 to Range of Control CPU Communications Range of Non-control CPU Communications PROCESSING TIME FOR MULTIPLE CPU SYSTEM BASIC MODEL QCPUs 18-1 to Concept behind Scan Time Factor to Prolong the Scan Time STARTING UP THE MULTIPLE CPU SYSTEM 19-1 to Flow-chart for Starting Up the Multiple CPU System Setting Up the Multiple CPU System Parameters (Multiple CPU Settings, Control CPU Settings) System configuration Creating new systems Using existing preset Multiple CPU settings and I/O allocations APPENDICES App - 1 to App - 2 APPENDIX 1 Special Relay List... App - 1 APPENDIX 2 Special Register List... App - 5 APPENDIX 3 List of Interrupt Pointer Nos. and Interrupt Factors... App -18 APPENDIX 4 Enhancement of the Basic Model QCPU Functions... App 19 APPENDIX 4.1 Specification Comparison... App 19 APPENDIX 4.2 Added Functions... App 19 INDEX Index- 1 to Index- 2 A - 12 A - 12

14 (Related manual)... QCPU (Q Mode) User's Manual (Hardware Design,Maintenance and Inspection) 1 OVERVIEW 1.1 Features 2 SYSTEM CONFIGURATION 2.1 System Configuration of Single CPU System QJCPU QCPU, Q1CPU Configuration for Use of GX Developer 2.2 Precautions for Use of Single CPU System 2.3 System Configuration of Multiple CPU System QCPU or Q1CPU Configuration for Use of GX Developer 2.4 Precautions for Use of Multiple CPU System 2.5 Confirming the Function Version. 3 GENERAL SPECIFICATIONS CONTENTS 4 HARDWARE SPECIFICATION OF THE CPU MODULE 4.1 Performance Specification 4.2 Part Names QJCPU QCPU, Q1CPU 4.3 Switch Operation After Program Write 4.4 Reset Operation 4.5 Latch Clear Operation 5 POWER SUPPLY MODULE 5.1 Specification Power supply module specifications Selecting the power supply module Precaution when connecting the uninterruptive power supply A - 13 A - 13

15 5.2 Part Names and Settings 6 BASE UNIT AND EXTENSION CABLE 6.1 Base Unit Specification Table 6.2 Extension Cable Specification Table 6.3 Parts Names of Base Unit 6.4 Setting the Extension Base Unit 6.5 Guideline for Use of Extension Base Units (Q5!B) 7 BATTERY 7.1 Battery Specifications 7.2 Installation of Battery 8 EMC AND LOW-VOLTAGE DIRECTIVES 8.1 Requirements for conformance to the EMC Directive Standards applicable to the EMC Directive Installation instructions for the EMC Directive Cables Power supply module, QJCPU power supply section Others 8.2 Requirement to Conform to the Low-Voltage Directive Standard applied for series PLC series PLC selection Power supply Control box Grounding External wiring 9 LOADING AND INSTALLATION 9.1 General Safety Requirements 9.2 Calculating Heat Generation by PLC 9.3 Module Installation Precaution on installation Instructions for mounting the base unit Installation and removal of the module 9.4 Setting the Stage Number of the Extension Base Unit 9.5 Connection and Disconnection of the Extension Cable 9.6 Wiring The precautions on the wiring Connecting to the power supply module 1 MAINTENANCE AND INSPECTION 1.1 Daily Inspection 1.2 Periodic Inspection 1.3 Battery Replacement A - 14 A - 14

16 1.3.1 Battery service life Battery replacement procedure 1.4 When Resuming Operation after Storage of PLC without Battery 1.5 When Resuming PLC Operation after Storage of PLC with Battery Gone Flat 11 TROUBLESHOOTING 11.1 Troubleshooting Basics 11.2 Troubleshooting Troubleshooting flowchart Flowchart for when the "POWER" LED is turned off Flowchart for when the "RUN" LED is turned off When the "RUN" LED is flashing Flowchart for when the "ERR." LED is on/flashing Flowchart for when output module LED is not turned on Flowchart for when output load of output module does not turn on Flowchart for when unable to read a program Flowchart for when unable to write a program Flowchart for when program is rewritten Flowchart for when UNIT VERIFY ERR. occurs Flowchart for when CONTROL BUS ERR. occurs 11.3 Error Code List Procedure for reading error codes Error code list 11.4 Canceling of Errors 11.5 Input/Output Module Troubleshooting Input circuit troubleshooting Output circuit troubleshooting 11.6 Special Relay List 11.7 Special Register List APPENDICES APPENDIX 1 Error Code Return to Origin During General Data Processing APPENDIX 1.1 Error code overall explanation APPENDIX 1.2 Description of the errors of the error codes (4H to 4FFFH) APPENDIX 2 External Dimensions APPENDIX 2.1 CPU module APPENDIX 2.2 Power supply module APPENDIX 2.3 Main base unit APPENDIX 2.4 Slim type main base unit APPENDIX 2.5 Extension base unit APPENDIX 3 Functions Improvement of Basic Model QCPU APPENDIX 3.1 Specification comparison APPENDIX 3.2 Additional functions APPENDIX 3.3 Usability of additional functions by GX Developer version INDEX A - 15 A - 15

17 About Manuals The following manuals are also related to this product. In necessary, order them by quoting the details in the tables below. Related Manuals Manual Name Basic Model QCPU (Q Mode) User's Manual (Hardware Design, Maintenance and Inspection) This manual provides the specifications of the CPU modules, power supply modules, base units, extension cables and others. (Sold separately) QCPU (Q Mode)/QnACPU Programming Manual (Common Instructions) Describes how to use the sequence instructions, basic instructions, advanced instructions, and microcomputer programs. (Sold separately) Manual Number (Model Code) SH-8187 (13JL97) SH-839 (13JF58) QCPU (Q Mode)/QnACPU Programming Manual (PID Control Instructions) This manual describes the dedicated instructions used to exercise PID control. (Sold separately) SH-84 (13JF59) QCPU (Q Mode)/QnACPU Programming Manual (SFC) This manual explains the system configuration, performance specifications, functions, programming, debugging, error codes and others of MELSAP3. (Sold separately) QCPU (Q Mode)/QnACPU Programming Manual (MELSAP-L) This manual describes the programming methods, specifications functions, and so on that are necessary to create the MELSAP-L type SFC program. (Sold separately) Q Corresponding MELSEC Communication Protocol Reference Manual This manual explains the communication methods and control procedures through the MC protocol for the external devices to read and write data from/to the PLC CPU using the serial communication module/ethernet module. (Sold separately) SH-841 (13JF6) SH-876 (13JF61) SH-88 (13JF89) QCPU (Q mode) Programming Manual (Structured Text) Explains the programming methods in structured text language. (Sold separately) SH-8366E (13JF68) A - 16 A - 16

18 How to Use This Manual This manual is prepared for users to understand memory map, functions, programs and devices of the CPU module when you use Basic model QCPU (QJ/Q/ Q1CPU). The manual is classified roughly into three sections as shown below. (1) Chapters 1 and 2 Describe the outline of the CPU module and the system configuration. The feature of CPU module and the basics of the system configuration of CPU are described. (2) Chapters 3 to 6 Describe the performance specifications, executable program, I/O No. and memory of the CPU module. (3) Chapter 7 Describes the functions of the CPU modules. (4) Chapter 8 Describes communication with intelligent function modules. (5) Chapters 9 and 1 Describe parameter and devices used in the CPU modules. (6) Chapter 11 Describes the CPU module processing time. (7) Chapter 12 Describes the procedure for writing parameter and program created at the GX Developer to the CPU module. (8) Chapters 13 to 19 Describes the overview of a Multiple CPU System, system configuration, I/O numbers, communication between CPU modules, and communication with I/O modules/intelligent function modules. REMARK This manual does not explain the functions of power supply modules, base units, extension cables and batteries. For these functions, refer to the manual shown below. Basic Model QCPU (Q Mode) User's Manual (Hardware Design, Maintenance and Inspection) A - 17 A - 17

19 About the Generic Terms and Abbreviations The following abbreviations and general names for Basic model QCPU are used in the manual. Generic Term/Abbreviation Description Basic model QCPU General name for QJCPU, QCPU and Q1CPU modules. Q Series Abbreviation for Mitsubishi general-purpose PLC series. Product name for Q series compatible SW D5C-GPPW(-V) type GPP function GX Developer software package. indicates Version "7" or later. When using the functions of the function version B, use Version "8". Q3 B General name for Q33B, Q35B, Q38B and Q312B type main base units that accept QCPU/Q1CPU, Q series power supply module, input/output module and intelligent function module. Q3 SB General name for Q32SB, Q33SB and Q35SB type slim type main base units that accept QCPU, Q1CPU, slim type power supply module, I/O modules and intelligent function modules. Q5 B General name for Q52B and Q55B type extension base unit with Q Series input/output module, intelligent function module attachable. Q6 B General name for Q63B, Q65B, Q68B and Q612B type extension base unit with Q Series power module, input/output module, intelligent function module attachable. General name for Q33B, Q35B, Q38B, and Q312B type main base unit QJCPU Main base unit (base unit) with Q Series power module, input/output module, intelligent function module attachable. 1 General name for Q32SB, Q33SB and Q35SB type slim type main base units that Slim type main base unit accept QCPU, Q1CPU, slim type power supply module, I/O modules and intelligent function modules. Extension base unit General name for Q5 B and Q6 B. Base unit General name for main base units, slim type main base unit and extension base units. Extension cable General name for QC5B, QC6B, QC12B, QC3B, QC5B, QC1B type extension cable. Power supply module General name for Q61P-A1, Q61P-A2, Q63P, Q64P type power supply module, QJCPU (power supply section). Slim type power supply module General name for Q61SP slim type power supply module. Battery General name for Q6BAT type CPU module battery. CPU slot Slot on right-hand side of power supply module on main base unit. Basic model QCPU, motion CPU or PC CPU module that controls I/O module or Control CPU intelligent function module mounted on main base unit or extension base unit. For example, when the module mounted on Slot 3 is to be controlled by CPU No. 2, CPU No. 2 is the control CPU of the module on Slot 3. Basic model QCPU, motion CPU or PC CPU module other than control CPU. For Non-control CPU example, when the module mounted on Slot 3 is to be controlled by CPU No. 2, CPU No. 1 and CPU No. 3 are the non-control CPUs of the module on Slot 3. I/O module or intelligent function module other than controlled modules. For example, Non-controlled module when the module mounted on Slot 3 is to be controlled by CPU No. 2, the module on (Non-group module) Slot 3 is the non-controlled module of CPU No. 1 and CPU No. 3. I/O module or intelligent function module to be controlled by control CPU. For Controlled module example, when the module mounted on Slot 3 is to be controlled by CPU No. 2, the module on Slot 3 is the controlled module of CPU No. 2. Number assigned to differentiate between Basic model QCPU, Motion CPU and PC CPU No. CPU module mounted in a Multiple CPU System. The CPU on the CPU slot is No. 1, the one on Slot is No. 2, and the one on Slot 1 is No. 3. Single CPU System System in which Basic model QCPU is mounted on CPU slot for control. PC CPU module series compatible PC CPU module of Contec makes. Multiple CPU System System in which up to of three Basic model QCPU/Motion CPU/PC CPU modules are mounted on main base unit for control. 1: In a Multiple CPU System configuration, the Motion CPU and PC CPU module can also be mounted. A - 18 A - 18

20 1 OVERVIEW 1 OVERVIEW This manual describes the functions, programs and devices of the Basic model QCPU. 1 Refer to the following functions for details on power supply modules, base units, extension cables, battery specifications and other information. Basic Model QCPU (Q mode) User's Manual (Hardware Design, Maintenance and Inspections) (1) QJCPU The QJCPU is a CPU module consisting of a CPU module, a power supply module and a main base unit (five slots). This CPU allows connection of up to two extension base units to accept up to 16 input/output and intelligent function modules. The number of input/output points controllable by the main and extension base units is 256. When a CC-Link/LT module is used, 124 points can be controlled by a single module. (2) QCPU, Q1CPU The QCPU and Q1CPU are stand-alone CPU modules loaded on a main base unit or slim type main base unit. Either of these CPUs allows connection of up to four extension base units to accept up to 24 input/output and intelligent function modules. However, an extension base unit cannot be connected to the slim type main base unit. The number of input/output points controllable by the main and extension base units is 124. When a CC-Link/LT module is used, 124 points can be controlled by a single module. The Basic model QCPU can be used with the Motion CPU and PC CPU module to configure a Multiple CPU System. For detailed explanation of the multiple PLC system, refer to Chapter 13 to Chapter

21 1 OVERVIEW 1 The Basic model QCPU is updated to add functions. The added functions can be judged by the function version/serial No. of the CPU module. Table 1.1 indicates the added functions and the GX Developer version compatible with the additional functions. When using any of the added functions, confirm the function version/serial No. and GX Developer version. Table 1.1 List of Functions Added to Basic Model QCPU and Function Version/Serial No. Updates of Basic Model QCPU Compatible Function version Serial No. Additional functions GX Developer B 4122 or later Multiple PLC system (QCPU, Q1CPU) SFC Function block Structured text (ST) Real number operation function PID operation function 1 Remote password setting Increased standard RAM capacity (QCPU, Version 8 or later Q1CPU) 1 Device initial value automatic setting Interrupt function from intelligent function module Write during RUN function using pointer *1 Functions irrelevant to GX Developer POINT Refer to Section 2.3 for the confirmation of the function version and serial No. of the Basic model QCPU

22 1 OVERVIEW The following table indicates the differences between the Basic model QCPUs. Item QJCPU QCPU Q1CPU CPU module, Power supply CPU module module, Main base unit Stand-alone CPU module (5 slots) Integrated type Main base unit/slim type main base unit Unnecessary Necessary (Q33B, Q35B, Q38B, Q312B) Connectable Extension base unit However, an extension base unit cannot be connected when the slim type main base unit is used. Number of extension stages Up to 2 stages Up to 4 stages 24 modules Number of input/output modules to be 16 modules (Cannot be connected when the slim type main installed base unit is used) Power supply module Main base unit Unnecessary Necessary Slim type main base unit Unnecessary Necessary Extension Q52B, Q55B Unnecessary base unit Q63B, Q65B, Q68B, Q612B Necessary Extension cable QC5B, QC6B, QC12B, QC3B, QC5B, QC1B Memory card interface No External interface RS-232 Yes (transmission rate: 9.6kbps, 19.2kbps, 38.4kbps, 57.6kbps, kbps) USB No Processing speed LD X.2µs.16µs.1µs (Sequence instruction) MOV D D1.7µs.56µs.35µs Program capacity 1 8k steps (32 kbyte) 8k steps (32 kbyte) 14k steps (56 kbyte) Memory capacity Program memory 58 kbyte 94 kbyte Standard RAM 128 kbyte 2 Standard ROM 58 kbyte 94 kbyte CPU shared memory 3 None 1k bytes (user free area 32 words) Number of times for write to standard ROM Maximum 1, times Device memory capacity The number of device points can be changed within the range of 16.4k words. Number of input/output devices points (Remote I/O is contained.) 248 points Number of input/output points 256 points 124 points File register No Yes (64k points fixed) Serial communication function No Yes (using the RS-232 interface of the CPU module) 1: 1 step of the program capacity is 4 Bytes. 2: 64k bytes for the function version A. 3: Memory added to the function version B. The CPU shared memory is not latched. The CPU shared memory is cleared when the PLC is powered on or the CPU module is reset

23 1 OVERVIEW 1.1 Features (1) Many controllable input/output points As the number of input/output points accessible to the input/output modules loaded on the base units, the following numbers of input/output points are supported. QJCPU: 256 points (X/Y to FF) QCPU, Q1CPU: 124 points (X/Y to 3FF) (2) Lineup according to program capacity The optimum CPU module for the program capacity to be used can be selected. QJCPU, QCPU : 8k steps Q1CPU : 14k steps (3) Fast processing series. Comparison of installation space The LD instruction processing speeds are as follows. QJCPU :.2µs QCPU :.16µs Q1CPU :.1µs The high-speed system bus of the series base unit can speed up access to an intelligent function module and link refresh with a network module. MELSECNET/H link refresh processing : 2.2ms/2k words 1 *1 This speed only applies when the SB/SW is not used with the Q1CPU and the MELSECNET/H network module is used as the main base unit. (4) Increase in debugging efficiency through high-speed communication with GX Developer The RS-232 interface of the Basic model QCPU enables program write/read or monitor at a maximum of 115.2kbps. (5) Saved space by a reduction in size The installation area of the Basic model QCPU is about 6% of that of the AnS 1SX1 1SY5 1SX41 1SY41 1SX81 1SY81 1SX42 1SY42 98mm (3.86 inch) 5 Slot Main Base Unit 245mm(9.65inch) 8 Slot Main Base Unit 328mm(12.92inch) 12 Slot Main Base Unit 439mm(17.3inch) (depth:98mm(3.86inch))

24 1 OVERVIEW (6) Connection of up to four/two extension base units (a) The QJCPU can connect up to two extension base units (three base units including the main) and accepts up to 16 modules. (b) The Q/Q1CPU can connect up to four extension base units (five base units including the main) and accepts up to 24 modules. (c) The overall distance of the extension cables is up to 13.2m to ensure high degree of extension base unit arrangement. POINT (1) When connected with a bus, the GOT uses one of the above extension base units. Therefore, the number of available extension base units decreases by one. (2) When the slim type main base unit (Q3 SB) is used, an extension base unit cannot be connected. (7) Serial communication function for communication with personal computer or display device With the RS-232 interface of the QCPU or Q1CPU connected with a personal computer, display device or the like, the MELSEC communication protocol (hereafter refered to as the MC protocol) can be used to make communication. RS-232 cable Personal computer, display device Communication in MC protocol The serial communication function only allows communication in the MC protocol (QnA-compatible 3C frame (format 4), QnA-compatible 4C frame (format 4, 5)). The serial communication function does not allow communication in the nonprocedure protocol or bidirectional protocol. Refer to the following manual for the MC protocol. Q Corresponding MELSEC Communication Protocol Reference Manual (8) Built-in standard ROM The flash ROM for storing parameters and sequential program is installed as a standard feature for easier protection of important program. (9) Blocking an invalid access using the file password The file password can be used to set the access level (read disable, write disable) of a program to prevent program changes due to illegal access

25 1 OVERVIEW (1) 64k points of file registers available (QCPU, Q1CPU) The standard RAM capacity has been increased from 64k bytes to 128k bytes to double the file register capacity (64k points). The increase of battery-backed data provides sufficient space for control programs. (11) Remote password setting When external access is made to an Ethernet module, serial communication module or modem interface module, whether access to the Basic model QCPU may be made or not can be selected using a remote password. (12) Multiple CPU System compatibility A Multiple CPU System can be configured by the Basic model QCPU (QCPU, Q1CPU only), Motion CPU and PC CPU module. REMARK The features in (1) to (12) are functions added to the Basic model CPU of function version B. The remote password function can be executed when the Ethernet module or serial communication module of function version B is used with GX Developer 8 or later

26 1 OVERVIEW 1.2 Program Storage and Calculation (1) Program storage Program created at GX Developer can be stored in Basic model QCPU's program memory or standard ROM. QJCPU QCPU,Q1CPU Program memory Parameters 3 Program Comment Standard ROM 1 Parameters 3 Program Comment Program memory Parameters 3 Program Comment Standard ROM 1 Parameters 3 Program Comment Standard RAM 2 File registers 1: The standard ROM is used when parameters, program and comment are written to ROM. 2: The standard RAM is used for file registers. 3: Including the intelligent parameters of the intelligent function module set on GX Configurator. (2) Program execution The Basic model QCPU processes program which are stored in the program memory. QJ/Q/Q1CPU Program memory Parameters Program Comment Execution of program in program memory For displaying comment of program made by GX Developer

27 1 OVERVIEW (3) Boot operation of program The program stored on the standard ROM is booted (read) to the program memory of the Basic model QCPU and executed. Booting a program from the standard ROM to the program memory requires boot file setting in the PLC parameter. Basic model QCPU Program memory Parameter Program Comment Boot Standard ROM Parameter Program Comment Execution of program booted from the standard ROM to the program memory

28 1 OVERVIEW 1.3 Convenient Programming Devices and Instructions The QJ/Q/1CPU features devices and instructions which facilitate program creation. A few of these are described below. (1) Flexible device designation (a) Word device bits can be designated to serve as contacts or coils. [For the case of Basic model QCPU] [For the case of AnS] Bit designation of X D.5 word device X D.A MOV D K4M The 1/ status of b5 of D is used as ON/OFF data. Switches b1 of D ON and OFF (1/). M5 MOV K4M M1 D D b15b14 b13 b12 b11b1 1/ b9 b8 b7 b6 b5 1/ b4 b3 b2 b1 b : D.5 Bit designation Word device designation (b) Direct processing in 1-point units is possible within a program simply by using direct access inputs (DX ) and direct access outputs (DY ). [For the case of Basic model QCPU] Direct access input [For the case of AnS] M DX1 M936 DY1 SET M952 (Always ON) Output to output M936 module at SEG K1X1 K1B instruction execution (X1 to X13 refresh) Read from input module at instruction execution M M936 X1 Y1 SEG K1Y1 K1B (Y1 to Y13 refresh) (c) Differential contacts ( / ) eliminate the need for converting inputs to pulses. [For the case of Basic model QCPU] [For the case of AnS] Differential contact X X1 X Y1 PLS M Y1 M X1 Y1 ON at leading edge of X Y

29 1 OVERVIEW (d) The buffer memory of intelligent function module (e.g. Q64AD, Q62DA) can be used in the same way as devices when programming. [For the case of Basic model QCPU] [For the case of AnS] X +P U4\G12 D X FROMP H4 K12 D1 K1 Readout of Q64AD buffer memory's address 12 data +P D1 D Power supply module QCPU Input (16 points) Input (16 points) Input (16 points) Q64AD (16 points) Q64AD (16 points) Q62AD (16 points) Output (16 points) Output (16 points) :U4\G12 Buffer memory address designation Intelligent function module designation Input/output Nos.:X/Y4 to X/Y4f (e) Direct access to link devices (LX, LY, LB, LW, LSB, LSW) of MELSECNET/H network modules (e.g. QJ71LP21-25) is possible without refresh settings. X +P J5\W12 D Direct readout of the No.5 network module's "LW12" link register Power supply module QCPU QJ71LP21-25 Input (16 points) Input (16 points) Q68AD (16 points) Q68AD (16 points) Q62AD (16 points) Output (16 points) Output (16 points) :J5\W12 Link register designation Network No. designation Network No

30 1 OVERVIEW (2) Edge relays simplify pulse conversion processing (a) The use of a relay (V) that comes ON at the leading edge of the input condition simplifies pulse processing when a contact index qualification has been made. [Circuit example] M1 RST Z1 Reset index register (Z1) FOR K1 Repetition (1 times) designation XZ1 VZ1 MZ1 Pulsing M to M999 M1 INC Z1 Increment Index Register (Z1) (+1) NEXT Return to FOR instruction [Timing chart] X OFF When Z1= V OFF M OFF ON ON ON 1 Scan When Z1=1 X1 OFF V1 OFF M1 OFF ON ON ON 1 Scan (3) Structured program The index registers and edge relay make it easy to structure the program that includes pulse processing. [Basic model QCPU] FOR n X M X1 [Ans] PLS M Y8 XZ X1Z VZ1 Y8Z2 NEXT n pieces of similar programs can be described at one time! X1 X11 PLS M1 M1 Y18 X17X171 PLS M17 M17 Y

31 1 OVERVIEW (4) Ease of data processing The reinforced data processing instructions, such as table processing instructions, enable high-speed processing of large amounts of data. X FINSP D Insertion source R K2 Insertion Insertion position designation Instruction for data insertion at table D 15 R R1 R2 R3 R4 FIF table R R1 R2 R3 R4 FIF table (5) Easy shared use of sub-routine programs Subroutine call instructions with arguments will make it easier to create a subroutine programs that makes several calls. Main routine program Argument designation M CALLP P W K4X R Subroutine program designation Argument from FD2 Argument to FD1 Argument to FD 1 M1 CALLP P Argument designation W1 K4X1 R1 Argument from FD2 Argument to FD1 Argument to FD FEND Sub-routine program Destination data source data SM4 M P MOV FD FD2 Always ON M MOV FD1 FD2 RET END REMARK For details regarding the argument input/output condition, refer to Section

32 2 SYSTEM CONFIGURATION 2 SYSTEM CONFIGURATION 2.1 System Configuration QJCPU This section describes the system configuration of the Basic model QCPU, cautions on use of the system, and configured equipment. 2 This section explains the equipment configuration of a QJCPU system and the outline of the system configuration. (1) Equipment configuration MITSUBISHI LITHIUM BATTERY Battery (Q6BAT) Basic model QCPU (QJCPU) Input/output module/ Intelligent function module Q5 B extension base unit (Q52B, Q55B) Extension cable (QC5B, QC6B, QC12B, QC3B, QC5B, QC1B) Q6 B extension base unit (Q63B, Q65B, Q68B, Q612B) Input/output module/ Intelligent function module Power supply module/ Input/output module/ Intelligent function module

33 2 SYSTEM CONFIGURATION 2 System configuration (2) Outline of system configuration (a) System including extension base units Extension cable Extension 2 O UT C P U F 1F 2F 3F 4F Extension base unit (Q68B) Extension 1 Extension A B C O I UT N O UT I N Power supply module 5F Extension base unit (Q65B) Power supply module 13 D 6F 7F E F DF EF FF 8F 9F Inhibited Inhibited AF BF CF Loading will cause error Extension cable connector Slot number (b) System including extension base unit and GOT Extension cable O UT O UT I N C P U Extension base unit (Q68B) F F 1F 2F 3F 4F 6 6F 7 7F 8 8F 9 9F A B C AF BF CF Number of extension units: 2 Slot No. : Both of the above systems assume that each slot of the main and extension base units is loaded with a 16-point module. Maximum number of Extension Stages Two Extension Stages Maximum number of input/output modules to 16 modules be installed Maximum number of input/output points Main base unit Unnecessary Extension base unit Q52B, Q55B, Q63B, Q65B, Q68B, Q612B Extension cable QC5B, QC6B, QC12B, QC3B, QC5B, QC1B (1) Do not use an extension cable longer than an overall extension length of 13.2m(43.31ft.). (2) When using an extension cable, do not bind it together with the main circuit (high voltage and heavy current) line or do not lay down them closely to each other. (3) When setting the No. of the expansion stages, set it in the ascending order so that the same No. is not set simultaneously by two extension base units. (4) The QA1S6 B/QA65B cannot be connected as an extension base unit. Notes (5) Connect the extension cable from OUT of the extension cable connector of the base unit to IN of the extension base unit on the next stage. (6) If 17 or more modules are installed, an error will occur. (7) When bus-connected, the GOT occupies one extension stage and one slot. (8) The QJCPU processes the GOT as a 16-point intelligent function module. Hence, connection of one GOT decreases the number of controllable points on base units by 16 points. (9) The bus extension connector box (A9GT-QCNB) cannot be connected to the QJCPU. It should be connected to the extension base unit. 1: Indicates the maximum number of I/O points of the CPU module and does not indicate the maximum number of I/O points of the system. When a CC-Link/LT module is used, 124 points can be controlled per module. Power supply module

34 2 SYSTEM CONFIGURATION Q, Q1CPU This section explains the equipment configuration of a Q/Q1CPU system and the outline of the system configuration. (1) Equipment configuration (a) When main base unit (Q3 B) is used MITSUBISHI LITHIUM BATTERY Basic model QCPU (QCPU, Q1CPU) Battery (Q6BAT) Main base unit (Q33B, Q35B, Q38B, Q312B) Power supply module/ Input/output module/ Intelligent function module Q5 B extension base unit (Q52B, Q55B) Extension cable (QC5B, QC6B, QC12B, QC3B, QC5B, QC1B) Q6 B extension base unit (Q63B, Q65B, Q68B, Q612B) Input/output module/ Intelligent function module Power supply module/ Input/output module/ Intelligent function module POINT As a power supply module, use the Q61P-A1, Q61P-A2, Q62P or Q64P. The slim type power supply module (Q61SP) cannot be used

35 2 SYSTEM CONFIGURATION (b) When slim type main base unit (Q3 SB) is used MITSUBISHI LITHIUM BATTERY Basic model QCPU (QCPUC Q1CPU) Battery (Q6BAT) Slim type main base unit (Q32SB,Q33SB,Q35SB) Slim type power supply, I/O, intelligent function modules POINT (1) As a power supply module, use the slim type power supply module (Q61SP). The Q61P-A1, Q61P-A2, Q62P or Q64P cannot be used. (2) The slim type main base unit does not have an extension cable connector. An extension base unit or GOT cannot be connected

36 2 SYSTEM CONFIGURATION (2) Outline of system configuration (a) When main base unit (Q3 B) is used (a) System including extension base units Extension cable O UT Power supply module Main base unit (Q312B) A C E CPU module 1F 3F 5F 7F 9F BF DF FF 11F 13F15F 17F Slot No. (b) System including extension base unit and GOT Extension cable O UT Power supply module Main base unit (Q312B) A C E CPU module 1F 3F 5F 7F 9F BF DF FF 11F 13F15F 17F Slot No. System configuration Extension 1 Extension 2 O I UT N O UT I N Power supply module Power supply module Extension base unit (Q68B) A 1C 1E F 1BF 1DF 1FF 21F 23F 25F 27F Extension base unit (Q65B) A 2C 2E 29F 2BF 2CF 2FF Inhibited Loading will cause error Assumes that each slot is loaded with a 32-point module. Extension 1 O I UT N Power supply module Extension base unit (Q68B) A 1C 1E F 1BF 1DF 1FF 21F 23F 25F 27F GOT Number of extension units: 2 Slot No. : Maximum number of Extension Stages Four Extension Stages Maximum number of input/output modules to 24 modules be installed Maximum number of input/output points Main base unit Q33B, Q35B, Q38B, Q312B Extension base unit Q52B, Q55B, Q63B, Q65B, Q68B, Q612B Extension cable QC5B, QC6B, QC12B, QC3B, QC5B, QC1B (1) Do not use an extension cable longer than an overall extension length of 13.2m(43.31ft.). (2) When using an extension cable, do not bind it together with the main circuit (high voltage and heavy current) line or do not lay down them closely to each other. (3) When setting the No. of the expansion stages, set it in the ascending order so that the same No. is not set simultaneously by two extension base units. (4) The QA1S6 B/QA65B cannot be connected as an extension base unit. Notes (5) Connect the extension cable from OUT of the extension cable connector of the base unit to IN of the extension base unit on the next stage. (6) If 25 or more modules are installed, an error will occur. (7) When bus-connected, the GOT occupies one extension stage and one slot. (8) The Q/Q1CPU processes the GOT as a 16-point intelligent function module. Hence, connection of one GOT decreases the number of controllable points on base units by 16 points. (9) The Q61SP cannot be used as a power supply module. As a power supply module, use the Q61P-A1, Q61P-A2, Q62P or Q64P. 1: Indicates the maximum number of I/O points of the CPU module and does not indicate the maximum number of I/O points of the system. When a CC-Link/LT module is used, 124 points can be controlled per module

37 2 SYSTEM CONFIGURATION (b) When slim type main base unit (Q3 SB) is used System configuration Maximum number of extension stages Maximum number of input/output modules to be installed Maximum number of input/output points Slim type main base unit type Extension base unit type Extension cable type Power supply module Slim type main base unit (Q35SB) Slot number CPU module 1F F 5F 7F 9F * The above system assumes that each slot is loaded with a 32-point module. Extension not allowed 5 modules Q32SB,Q33SB,Q35SB Cannot be connected. Cannot be connected. (1) The Q61P-A1, Q61P-A2, Q62P or Q64P cannot be used as a power supply module. As a power supply module, use the Q61SP. Notes (2) The slim type main base unit does not have an extension cable connector. An extension base unit or GOT cannot be connected. 1: Indicates the maximum number of I/O points of the CPU module and does not indicate the maximum number of I/O points of the system. When a CC-Link/LT module is used, 124 points can be controlled per module

38 2 SYSTEM CONFIGURATION Configuration of GX Developer Basic model QCPU (QJCPU) Basic model QCPU (QCPU, Q1CPU) RS-232 cable (QC3R2) Personal Computer GX Developer (Version 8 or later)* REMARK : GX Developer Version 7 can be used when the functions added to the function version B of the Basic model QCPU are not used

39 2 SYSTEM CONFIGURATION 2.2 Precaution on System Configuration This section describes hardware and software packages compatible with Basic model QCPU. (1) Hardware (a) The number of modules to be installed and functions are limited depending on the type of the modules. Applicable Module Q Series MELSECNET/H network module Q series Ethernet interface module Q series CC-Link system master local module Type QJ71LP21, QJ71BR11, QJ71LP21-25, QJ71LP21G, QJ71LP21GE QJ71E71, QJ71E71-B2, QJ71E71-1 QJ61BT11 Limit of number of modules to be installed Up to one module Up to one module Up to 2 modules function version B or later Interrupt module QI6 One module only 1 1: Indicates the number of interrupt modules to which interrupt pointer setting has not been made. When interrupt pointer setting has been made, up to the following number of modules can be used. QJCPU : 16 modules QCPU, Q1CPU : 24 modules (b) A graphic operation terminal can be used only for the GOT9 series and F9 series (Basic OS matching Q-mode and communication driver must be installed). The GOT8 series, A77GOT and A64GOT cannot be used. (c) A DeviceNet Master-Slave module (QJ71DN91) whose function version is B or later can be used. (2) Software package GX Developer and GX Configurator of the versions or later in the following table are usable with the Basic model QCPU. Product Name Type Version GX Developer SW7D5C-GPPW-E Ver. 8 2 GX Simulator SW6D5C-LLT-E Ver. 6.13P GX Configurator-AD SWD5C-QADU-E Ver. 1.1L GX Configurator-DA SWD5C-QDAU-E Ver. 1.1L GX Configurator-SC SWD5C-QSCU-E Ver. 1.1L GX Configurator-CT SWD5C-QCTU-E Ver. 1.1L GX Configurator-TC SWD5C-QTCU-E Ver. 1.1L GX Configurator-FL SWD5C-QFLU-E Ver. 1.1L GX Configurator-DN SWD5C-QDNU-E Ver. 1.1L GX Configurator-TI SWD5C-QTIU-E Ver. 1.1L GX Configurator-PT SW1D5C-QPTU-E Ver. 1.1L GX Configurator-QP SW2D5C-QD75P-E Ver. 2.1L 2: Ver. 7 can be used when the functions added to the function version B of the Basic model QCPU are not used.

40 2 SYSTEM CONFIGURATION 2.3 Confirming the function version The Basic model QCPU function version can be confirmed on the rating nameplate and GX Developer's system monitor. (1) Confirming the function version on the rating nameplate The function version is indicated on the rating nameplate. MODEL SERIAL B LISTED 8M1 IND.CONT.EQ. Function version MADE IN JAPAN (2) Confirming the function version on the system monitor (product information List) The product information list in the system monitor of GX Developer allows you to confirm the function version of the Basic model QCPU. The product information list of the system monitor also allows you to confirm the function versions of the intelligent function modules. Serial No. Function version

41 3 PERFORMANCE SPECIFICATION 3 PERFORMANCE SPECIFICATION The table below shows the performance specifications of the Basic model QCPU. Performance Specifications 3 Control method I/O control method Item Programming language (Sequence control dedicated language) Model QJCPU QCPU Q1CPU Repetitive operation of stored program Refresh mode Relay symbol language, logic symbolic language MELSAP3 (SFC), MELSAP-L, function block, structured text (ST) Processing speed LD X.2µs.16µs.1µs (Sequence instruction) MOV D D1.7µs.56µs.35µs Total number of instructions (excluding intelligent function module dedicated instructions) Constant scan (Function to make the scan time constant) Program 1 2 capacity Program memory (Drive ) Memory capacity Standard RAM (Drive 3) Standard ROM (Drive 4) CPU shared memory to 2 ms (configurable in increments of 1 ms) 8k steps (32 kbyte) 8k steps (32 kbyte) 58 kbyte 94 kbyte 128 kbyte 3 58 kbyte 94 kbyte None 14k steps (56 kbyte) 1k byte (user free area 32 words) Remark Direct input/output is possible by direct input/output specification (DX, DY ) Set parameter values to specify Number of Program memory 2 4 stored programs Standard ROM 2 4 Number of stored file registers Standard RAM 1 Number of times for write to standard ROM Maximum 1, times Number of I/O devices points 248 points (X/Y to 7FF) Number of devices usable on program Number of I/O points 256 points (X/Y to FF) 124 points (X/Y to 3FF) Number of points accesible to input/output modules 1: "1 step" in program capacity equals 4 bytes. 2: The maximum number of executable steps can be obtained as follows: (Program capacity) - (File header size (Default: 34 steps)) 3: 64k bytes for function version A. 4: One sequence program and one SFC program can be stored (two programs in all). 5: Memory added for function version B. The CPU shared memory is not latched. (Refer to Section 16.4 for details.) The CPU shared memory is cleared when the PLC is powered on or the Basic model QCPU is reset

42 3 HARDWARE SPECIFICATION OF THE CPU MODULE Item Performance Specifications (continued) Model QJCPU QCPU Q1CPU Remark Number of device points Internal relay [M] Default 8192 points (M to 8191) Latch relay [L] Default 248 points (L to 247) Link relay [B] Default 248 points (B to 7FF) Default 512 points (T to 511) (for low / high speed timer) Select between low / high speed timer by instructions. The measurement unit of the low / high speed timer is set Timer [ T ] with parameters. (Low speed timer : 1 to 1ms, 1ms/unit, default 1ms) (High speed timer :.1 to 1ms,.1ms/unit, default 1ms) Default point (ST to 511) (for low / high speed retentive timer) Switchover between the low / high speed retentive timer is set by instructions. Retentive timer [ ST ] The measurement unit of the low speed retentive timer and high speed retentive timer is set with parameters. (Low speed retentive timer : 1 to 1ms, 1ms/unit, default 1ms) (High speed retentive timer :.1 to 1ms,.1ms/unit, default 1ms) Normal counter default 512 points (C to 511) Counter [C] Interrupt counter maximum 128 points (default point, set with parameters) Data register [D] Default points (D to 11135) Link register [W] Default 248 points (W to 7FF) Annunciator [F] Default 124 points (F to 123) Edge relay [V] Default 124 points (V to 123) File Register [R] None points (R to 32767) [ZR] None points (ZR to 65535) Number of use points is set with parameters

43 3 HARDWARE SPECIFICATION OF THE CPU MODULE Item Performance Specifications (continued) Model QJCPU QCPU Q1CPU Remark Number of device points Special link relay [SB] Special link register [SW] 124 points (SB to 3FF) 124 points (SW to 3FF) Step relay [S] points (S to 127/block) Index register [Z] 1 points (Z to 9) Pointer [P] 3 points (P to 299) 128 points (I to 127) Interrupt pointer [ I ] The specified intervals of the system interrupt pointers I28 to The number of device I31 can be set with parameters.(.5 to 1ms, Cunit in.5 ms) points is fixed. Default I28 : 1ms I29 : 4ms I3 : 2ms I31 : 1ms Special relay [SM] 124 points (SM to 123) Special register [SD] 124 points (SD to 123) Function input [FX] 16 points (FX to F) 7 Function output [FY] 16 points (FY to F) 7 Function register[fd] 5 points (FD to 4) Link direct device Intelligent function module device Latch (power failure conpensation) range Remote RUN/PAUSE contact Clock function Allowable momentary stop time Device for direct access to link device. MELSECNET/H use only. Specified form at : J \X, J \Y, J \W, J \B, J \SW, J \SB Device for direct access to the buffer memory of the intelligent function module. Specified form at : U \G L to 247 (default) (Latch range can be set for B, F, V, T, ST, C, D, and W.) RUN and PAUSE contacts can be set from among X to 7FF, respectively. Year, month, day, hour, minute, second, day of the week (leap year automatic distinction) Accuracy -3.2 to +5.27s (TYP s) /d at C Accuracy to +5.27s(TYP s)/d at 25 C Accuracy to +3.65s(TYP s)/d at 55 C Max. 2ms (Min. 1VAC) Varies according to the type of power supply module. 5VDC internal current consumption.22a 8.25A.27A H 98mm (3.86in.) 98mm (3.86in.) External dimensions W 245mm (9.65in.) mm (1.8in.) D 97.5mm (3.84in.) 89.3mm (3.52in.) Weight.66kg 9.13kg 6: Step relay is a device for SFC function. 7: Only FX to FX4 and FY to FY4 can be used in a program. 8: This value includes those for the CPU module and base unit. 9: This value includes those for the CPU module, base unit, and power supply module. Set parameter values to specify

44 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS Programs that can be executed by the Basic model QCPU are sequence programs (MAIN) and SFC programs (MAIN-SFC). This chapter describes the sequence program configuration and execution conditions. For SFC programs, refer to the QCPU (Q mode)/qnacpu Programming Manual (SFC). The Basic model QCPU executes a sequence program and SFC program in the following order. Initial processing Refresh processing of I/O modules 4 Operation processing of sequence program Operation processing of SFC program END processing Fig. 4.1 Execution Sequence of Basic Model QCPU

45 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS 4.1 Sequence Program (1) Definition of sequence program (a) A sequence program is created using sequence instructions, basic instructions, and application instructions, etc. Sequence instruction X T X1 X41 M K1 T Y3 BIN K4X1 D FROM H5 K D1 K1 Basic instruction Application instruction 4 (b) There are 3 types of sequence program: main routine programs, sub-routine programs, and interrupt programs. For details regarding these programs, refer to the following sections of this manual: Main routine programs : Section Sub-routine programs : Section Interrupt programs : Section MAIN Main routine program FEND P I Sub-routine program RET Interrupt program IRET END REMARK For details regarding the sequence instructions, basic instructions, and application instructions, refer to the " QCPU (Q Mode)/QnACPU Programming Manual (Common Instructions)"

46 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS (2) Sequence program writing format Programming for sequence programs is possible using either ladder mode, or list mode. (a) Ladder mode The ladder mode is based on the relay control sequence ladder. Programming expressions are similar to the relay control sequence ladder. Relay symbolic language programming occurs in ladder block units. A ladder block is the smallest unit of sequence program processing, with the ladder beginning from the left bus and ending at the right bus. Left bus Step No. 2 a Contact b Contact Coil (output) X Y2 X1 X2 X3 Y21 Y22 Right bus Ladder blocks X4 8 Y24 X5 Y23 Y24 (b) X to X5 : Indicate inputs. Y2 to Y24 : Indicate outputs. Fig.4.2 Ladder Block List mode The list mode uses dedicated instructions instead of the contact symbols, coil symbols, etc., used in the ladder mode. Contact a, contact b and coil instructions are as follows: a contact...ld, AND, OR b contact...ldi, ANI, ORI coil...out (2) Program processing Sequence programs are processed in order, beginning from step and ending at the END/FEND instruction. Processing of ladder mode ladder blocks begins from the left bus, and proceeds from left to right. When one ladder block is completed, processing proceeds downward to the next ladder block. Top to bottom [Ladder mode] Left to right 1 1) X 3) X2 6) X4 2) X1 4) X3 7) X5 5) 8) X6 9) X7 1) Y1 11) END Executed in order, beginning from step to the ending at the END instruction. [List mode] LD 1 AND 2 LD 3 AND 4 ORB 5 OR 6 AND 7 AND 8 AND 9 OUT 1 END X X1 X2 X3 X4 X5 X6 X7 Y1 1) 2) 3) 4) 5) 6) 7) 8) 9) 1) 11) Numbers 1) to 11) indicate the processing order of the sequence program. Step No. Fig.4.3 Sequence Program Processing

47 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS Main routine program (1) Definition of main routine program (a) (b) A main routine program is a program which begins from step and ends at the END/FEND instruction. 1 The main routine program execution begins from step and ends at the END/FEND instruction. When the END/FEND instruction is executed in the main routine program, END processing is performed and operation is then restarted from step. Main routine program Step Program execution Returns to step END/FEND END/FEND END processing (2) Execution of main routine program The main routine program is executed every scan. REMARK 1: For details regarding the END/FEND instruction, refer to the "QCPU (Q mode)/qnacpu Programming Manual (Common Instructions)"

48 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS Sub-routine programs (1) Definition of sub-routine program (a) A sub-routine program is a program which begins from a pointer (P ) and (b) (c) ends at a RET instruction. A sub-routine program is executed only when called by a CALL instruction (e.g. CALL(P), FCALL(P)) from the main routine program. Sub-routine program application 1) The overall step count can be reduced by using a sub-routine program as a program which is executed several times in one scan. 2) The step count of a constantly executed program can be reduced by using a sub-routine program as a program which is executed only when a given condition is satisfied. (2) Sub-routine program management Sub-routine programs are created after the main routine program (after FEND instruction), and the combination of main and sub-routine programs is managed as one program. Create a sub-routine program as described below. A sub-routine program is created between the main routine program's FEND and END instructions. Because there are no restrictions regarding the order in which sub-routine programs are created, there is no need to set the pointers in ascending order when creating multiple sub-routine programs. MAIN Main routine program FEND Write Basic model QCPU Program memory /standard ROM MAIN file P Y1 Sub-routine program P8 RET Y11 RET P1 Y12 RET END

49 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS Interrupt programs (1) Definition of interrupt program (a) An interrupt program is a program which begins at the interrupt pointer (I ), and ends at the IRET instruction. 1 (b) Interrupt programs are executed only when an interrupt factor occurs. 1 (2) Interrupt program management Interrupt programs are created after the main routine program (after the FEND instruction), and the combination of main and sub-routine programs is managed as one program. Create an interrupt program as described below. An interrupt program is created between the main routine program's FEND and END instructions. Because there are no restrictions regarding the order in which interrupt programs are created, there is no need to set the interrupt pointers in ascending order when creating multiple interrupt programs. MAIN Main routine program Write Basic model QCPU Program memory /standard ROM MAIN file FEND I Y1 Interrupt program I5 IRET Y11 IRET I28 Y12 IRET END Interrupt pointer REMARK 1: See Section 1.1 for details regarding interrupt factors and interrupt pointers

50 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS (3) Executing interrupt programs (a) To run an interrupt program, interrupts must have been enabled by the EI instruction. 1 1) If interrupt factors occur before interrupts are enabled, the interrupt factors that occurred are stored, and the interrupt programs corresponding to the stored interrupt factors are executed as soon as interrupts are enabled. 2) If the same interrupt factor occurs more than once, the interrupt factors of I to I15 and I5 to I127 are stored and the interrupt factors of I28 to I31 are discarded. Interrupt program example EI Interrupt program execution Main routine program Program execution Interrupt program for "I" activated Interrupt program for "I29" activated I FEND End of main routine program I FEND Interrupt program I29 IRET "I" interrupt program I29 Interrupt program IRET "I29" interrupt program END END (b) Fig.4.4 Interrupt Program Execution When an interrupt factor occurs, the interrupt program with the interrupt pointer number corresponding to that factor is executed. However, interrupt program execution varies according to the condition at that time. 1) : When multiple interruptions occur simultaneously When multiple interrupt programs are activated simultaneously, the programs will be executed in order, beginning from the interrupt program with the highest priority interrupt pointer number. 3 The remaining interrupt programs remain on stand-by until processing of the higher priority interrupt program is completed. If the same interrupt factor as that being executed occurs before the processing of the interrupt program being executed is completed, the interrupt factors of I to I15 and I5 to I127 are stored and the interrupt factors of I28 to I31 are discarded. 2) When an instruction is being executed The interrupt program may be executed by interrupting the execution of an instruction in the main routine program. When the same device is used in both the main routine program and interrupt program, device data may be separated. To prevent the separation of the device data, the following measures must be taken. (a) Do not specify the device, to which data will be written in the interrupt program, directly in the main routine program, but use another device by shifting the data with a transfer instruction, etc

51 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS (b) If inconvenience is caused when the instruction is interrupted in the main routine program, execute it after disabling the interruption with the DI instruction. However, since the interrupt program will not interrupt during access to the device of each argument of the instruction, data separation will not occur on an argument basis. 3) Interruption during a network refresh: If an interrupt factor occurs during a network refresh operation, the network refresh operation is suspended, and the interrupt program is executed. This means that "assurance of blocks in cyclic data at each station" cannot be secured by using a device designated as a destination of link refresh operation on the MESSECNET/H Network System. 3 1ms 1ms 1ms 1ms Interrupt factor Interrupt program execution Network refresh execution (c) Network refresh operation is suspended, and the interrupt program is executed. Fig.4.5 Interruption during Network Refresh Operation 4) Interruption during END processing: If an interrupt factor occurs during an END processing waiting period during constant scanning, the interrupt program corresponding to that factor will be executed. When the interrupt program is executed in the default setting of the Basic model QCPU, the save and restoration of the index register value and the save and restoration of the file register block No. are performed at the time of switching between the main routine program and interrupt program. Refer to Section for details. (4) High-speed execution of an interrupt program and overhead time When "Execute at a High Speed" is selected for the interrupt program in the PLC system setting of the PLC parameter dialog box, the "save and restoration of the index register value" is not performed at the time of switching between the main routine program and interrupt program. This will make it possible to shorten the duration of overhead time required for execution of an interrupt program. Refer to Section 11.2 for the overhead time of an interrupt program

52 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS REMARK 2: For details regarding the IMASK and EI instructions, refer to the "QCPU (Q mode)/ QnACPU Programming Manual (Common Instructions). 3: See Section 1.1 for details regarding the priority ranking of interrupt programs. 4: For assurance of station unit blocks in cyclic data, see the "MELECNET/H Network System Reference Manual." (5) Program creation restrictions (a) A device which is switched ON by a PLS instruction in an interrupt program will remain ON until the PLS instruction for the same device is executed again. X PLS M X PLS M END IO IRET END END IO IRET END X OFF M OFF ON ON Switched OFF by PLS M instruction Switched ON by PLS M instruction at X leading edge (OFF to ON) (b) (c) During execution of the interrupt program, interrupts are disabled (DI) so that other interrupt processing is not performed. Do not execute EI/DI instructions in the interrupt program. Timers cannot be used in interrupt programs. As timers are used at OUT T instructions to update present values and switch contacts ON and OFF, the use of a timer in the interrupt program would make a normal time count impossible. (d) The following instructions cannot be used in interrupt programs. COM ZCOM EI DI S.TO (e) When the interrupt program is executed when measuring time such as the scan time or execution time, the measured time will become the value obtained by adding the interrupt program/constant cycle execution type program. Thus, if the interrupt program is executed, the values stored in the following special registers and GX Developer monitor values will become longer than when the interrupt program is not executed. 1) Special registers SD52, SD521: Current scan time SD524, SD525: Minimum scan time SD526, SD527: Maximum scan time SD54, SD541: END processing time SD542, SD543: Constant scan wait time 2) GX Developer monitor values Scan time measurement Constant scan

53 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS 4.2 Concept of Scan Time (1) Scan time (a) The "scan time" is a total of following the execution time of program and END processing. When an interrupt program is executed, the value including the execution time of the interrupt program will be the scan time. (b) The scan time present value, minimum value, and maximum value are measured at the Basic model QCPU, and the results are stored in special registers (SD52, SD521, and SD524 to SD527). 1 The scan time can therefore be checked by monitoring the SD52, SD521, and SD524 to SD527 special registers. Current value Minimum value Maximum value SD52 SD524 SD526 SD521 SD525 SD527 Stores less than 1 ms initial scan time (unit s) Stores the initial scan time in 1 ms units. If the SD52 value is 3, and the SD521 value is 4, the initial scan time is 3.4 ms. POINT 1: The accuracy of the scan time stored at the special registers is ±.1 ms. The scan time count will continue even if a watchdog time reset instruction (WDT) is executed at the sequence program. (2) Constant scan setting Constant scan is a function that repeats the execution of a main routing program at give intervals. When constant scanning is designated, the main routine program is executed at each designated constant scan period. Refer to Section 7.2 for details of constant scan. (3) WDT (Watchdog timer) This is the timer which monitors the scan time, and its default setting is 2 ms. This WDT setting can be designated in a 1 ms to 2 ms range in the PLC RAS settings of the PLC parameter. (Setting units: 1 ms) POINT The WDT measurement error is 1 ms. Therefore, a WDT setting (t) of 1 ms will result in a "WDT ERROR" if the scan time is in the following range: 1 ms < t < 2 ms

54 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS 4.3 Operation Processing Initial processing This is a preprocessing for sequence operation execution, and is performed only once as shown in the table below. When the initial processing is completed, the Basic model QCPU goes in the RUN/STOP/RESET switch setting status. (See Section 4.4.) Initial processing item The Input/Output module initialization Boot from the standard ROM PLC parameter check Multiple PLC system parameter matching check Device initialization of the range not latched (bit device: OFF, word device: ) Automatic allocation of the I/O number of installed modules Start of the MELSECNET/H network information setting and network communication Switch setting of intelligent function module Setting of CC-Link information Setting of Ethernet information Device initial value Setting of serial communication function : executed, : not executed When the power is turned on. Basic model QCPU status When reset is executed. When STOP 1 to RUN REMARK 1: Indicates that the parameter or program was changed in a STOP status and the CPU was placed in a RUN status without being reset. (The RUN/STOP/RESET switch has been moved from STOP to RUN (RUN LED flickers) to STOP to RUN.) Since the previous data may not be maintained in the pulse conversion instruction (PLS, P) by the above operation depending on the program change, fully note that normal operation may not be performed

55 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS I/O refresh (I/O module refresh processing) In I/O refresh, an input (X) is received from the input module/intelligent function module, and output (Y) of the Basic model QCPU is produced to the output module/intelligent function module. The I/O refresh is executed before the sequence program operation starts. During constant scan execution, the I/O refresh is executed after the constant scan delay time has elapsed. (The I/O refresh is executed at each constant scan cycle.) Automatic refresh of the intelligent function module END processing When automatic refresh of intelligent function modules is set, communication with the intelligent function modules of the designated data is performed. Refer to the manual for the intelligent function modules to use for details regarding of the automatic refresh setting of intelligent function modules. This is a post-processing to return the sequence program execution to step after completing the whole sequence program operation processing once. MELSECNET/H or CC-Link refresh processing Automatic refresh of intelligent function module Self-diagnostics Communication with external device such as GX Developer Processing of intelligent function module dedicated instruction (Completion processing only)

56 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS 4.4 RUN, STOP, PAUSE Operation Processing The Basic model QCPU has three types of operation states; RUN, STOP and PAUSE states. The Basic model QCPU operation processing is explained below: (1) RUN Status Operation Processing (a) (b) (c) RUN status is when the sequence program operation is performed from step to END (FEND) instruction to step repeatedly. When entering the RUN state, the output state saved at STOP by the parameter output-mode setting during STOP to RUN. The processing time of switching from STOP to RUN until the beginning of sequence program operation changes with system configurations, but usually is 1 to 3 seconds. However, this time may be longer depending on the conditions. (2) STOP Status Operation Processing (a) (b) STOP status is when the sequence program operations are stopped with the RUN/STOP/RESET switch or remote STOP is performed. (Refer to Section for details regarding of remote STOP function.) The STOP status is also caused by a stopping error. When entering the STOP state, save the output state and turn off all output. The device memory of other than the output (Y) is retained. (3) PAUSE Status Operation Processing (a) The PAUSE state is when the sequence program operations are paused by remote PAUSE function while maintaining the output and device memory status. (Refer to Section for details regarding of remote PAUSE function.) (4) Basic model QCPU Operation Processing with RUN/STOP state RUN/STOP state Operation processing RUN to STOP Sequence program operation processing Executes up to the END instruction and stops. STOP to RUN Starts at step. External output OS saves the status immediately before the STOP state and all points turn off. Determined by the output mode of the PLC parameter at STOP to RUN. Device memory M, L, S, T, C, D Y Maintains the status immediately before the STOP state. Starts executing the operation from the status immediately before the STOP state. When a device initial value is designated, however, the value is set. Local devices are cleared. Determined by the "STOP to RUN-time output mode" in the PLC parameter dialog box. OS saves the status immediately before the STOP state and all points turn off

57 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS POINT The Basic model QCPU performs the following in any of RUN, STOP, and Pause state: I/O module refresh processing Data communication with the GX Developer and serial communication module Refresh process of MELSECNET/H and CC-Link For this reason, I/O monitor and test operation using GX Developer, reading/writing from the serial communication, communication with another station using MELSECNET/H, and communication with a remote station over the CC-Link can be made even in the STOP or PAUSE status. 4.5 Operation Processing during Momentary Power Failure The Basic model QCPU detects a momentary power failure to the power module when the input power voltage is lower than the regulated ranges. When the Basic model QCPU detects a momentary power failure, the following operation processing is performed: (1) When momentary power failure occurs for less than permitted power failure time (a) (b) (c) The output is maintained when the momentary power failure occurs, and file name of the file accessed and error history are logged. Then the system interrupts the operation processing. (The timer clock continues.) When a momentary power failure ends, the operation processing is resumed. Even if the operation is interrupted due to momentary power failure, the watchdog timer (WDT) measurement continues. For example, if the GX Developer PLC parameter mode WDT setting is set at 2 ms, when a momentary failure of 15 ms occurs at scan time 19 ms, the watchdog timer error is set. Momentary power failure occurrence END Power recovery END END QCPU interrupts the operation. Fig.4.6 Operation Processing When Momentary Power Failure Occurs (2) When a power failure occurs for more than the permitted power failure time The Basic model QCPU starts initially. (PLC power is turned on.) The same operation processing as that after the following operation occurs. Power ON Resetting using RUN/STOP/RESET switch Remote setting using GX Developer

58 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS 4.6 Data Clear Processing (1) Data clear The Basic model QCPU clears all data except for the following, when a reset operation is performed with RESET/L.CLR switch, or power ON to OFF to ON. (a) Program memory data (b) (c) (d) (e) Device data with latch specification (latch clear valid) Device data with latch specification (latch clear invalid) File register data Failure history data (when special register SD storage) Data in (b) is cleared using the remote latch clear from the GX Developer function. Refer to Section for details regarding of the remote latch clear. (2) Device latch specification (a) Specify the device latch (latch range setting) for each device in the device setting of the PLC parameter. There are two types of latch range settings: 1) Valid latch clear key Sets the latch range that can be cleared with latch-clear operation using the remote latch clear. 2) Invalid latch clear key Sets the latch range that can not be cleared even with latch-clear operation using the remote latch clear. (b) POINT The devices that were set to invalid RESET/L.CLR switch can only be cleared by an instruction or GX Developer clear operation. 1) Instruction to clear method Reset with the RST instruction or send "" with the MOV/FMOV instruction. 2) GX Developer clear method Clear all device memory in the online PLC memory clear (including latch). For the GX Developer operation method, refer to the GX Developer Operating Manual. To clear file registers or local devices, use the RST instruction to perform a reset operation, or use the MOV/FMOV instruction to transmit "". REMARK See following manual for the MOV/FMOV instruction. QCPU (Q mode)/qnacpu Programming Manual (Common instructions)

59 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS 4.7 Input/Output Processing and Response Lag Refresh mode The Basic model QCPU features a refresh type input/output processing format in which a batch communication with the input/output module occurs at END processing. A direct communication format is also possible by using direct access inputs/outputs at the sequence program to enable direct communication with the input/output module when the sequence program instructions are executed. For details regarding direct inputs and direct outputs, refer to Sections and 1.2.2, respectively. (1) Definition of refresh mode In the refresh mode, batch communication with the input/output modules is made before start of the sequence program operation. (a) The ON/OFF data of the input module are batch-imported to the input device memory in the Basic model QCPU before start of the sequence program operation. (b) The operation result of the output (Y) sequence program is output to the output device memory in the Basic model QCPU every time the result ocurs, and the ON/OFF data of the output device memory are batch-output to the output module before start of the sequence program operation. Basic model QCPU CPU (operation processing area) Remote input refresh area 3 Input (X) 3) GX Developer device input area X memory 1 1) At input Area for refresh communication 4) 2 with input module Output (Y) Y22 device Y2 5) memory At input refresh 1) At output refresh 2) Network module Input module Output module Network module Input refresh: Before start of the sequence program operation, input data are batch-read from the input module (1) and ORed with the GX Developer input area or remote input refresh area data, and the results are stored into the input (X) device memory. Output refresh: Before start of the sequence program operation, the data (2) of the output (Y) device memory are batch-output to the output module. When an input contact instruction has been executed: Input information is read 3) from the input (X) device memory, and a sequence program is executed. When an output contact instruction has been executed: Output information is read 4) from the output (Y) device memory, and a sequence program is executed. When an output OUT instruction has been executed: The sequence program operation result 5) is stored in the output (Y) device memory. Fig.4.7 Input/Output Information Flow at Refresh Mode

60 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS REMARK 1: The GX Developer input area can be switched ON and OFF by the following: Test operation by the GX Developer Network refresh of MELSECNET/H network system Writhing from a serial communication module Automatic refresh of CC-Link 2: The output (Y) device memory can be switched ON and OFF by the following: Test operation by the GX Developer A network refresh by the MELSECNET/H network system Writhing from a serial communication module CC-Link automatic refresh 3: The remote input/output refresh area indicates the area used when automatic refresh setting is made to the input (X) with MELSECNET/H and CC-Link. Automatic refresh of the remote input refresh area is executed during END processing

61 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS (2) Response lag Output response lags of up to 2 scans can result from input module changes. (See Fig.4.7) Ladder examples X5 55 Y5E Ladder for switching the Y5E output ON in response to an X5 input ON. Fastest possible Y5E ON Input refresh Input refresh Output refresh END 56 END External contact QJ/Q/ Q1CPU devices X5 Y5E External load OFF OFF OFF OFF ON ON ON ON Lag time (Minimum 1 scan) The fastest possible Y5E ON occurs if the external contact is switched ON immediately prior to the refresh operation. X5 then switches ON at the input refresh, Y5E at step 56 switches ON, and the external load switches ON at the output refresh following execution of the END instruction. In this case, the time lag between the external contact ON and the external load ON is 1 scan. Slowest possible Y5E ON Input refresh Input refresh Output refresh END 56 END ON OFF External contact QJ/Q/ Q1CPU devices X5 Y5E External load OFF OFF OFF ON ON Lag time (Maximum 2 scan) ON The slowest possible Y5E ON occurs if the external contact is switched ON immediately prior to the refresh operation. X5 then switches ON at the input refresh, Y5E at step 56 switches ON, and the external load switches ON at the output refresh following execution of the END instruction. In this case, the time lag between the external contact ON and the external load ON is 2 scan. Fig.4.8 Output "Y" change in response to input "X" change

62 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS Direct mode (1) Definition of direct mode In the direct mode the communication with the input/output modules is performed when executing sequence program instructions. With Basic model QCPU, direct mode I/O processing can be executed by using direct access inputs (DX) and direct access outputs (DY). See for direct access inputs. See for direct access outputs. Basic model QCPU CPU (operation processing area) Remote input refresh area 3 Network module DX 3) Input (X) device memory 2) GX Developer input area 1 1) Input module Y2 DY25 4) 5) 2 Output (Y) device memory Output module When an input contact instruction has been executed: The input data (1) of the input module are ORed with the input data (2) of the GX Developer input area or the data of the remote input refresh area. The results are stored into the input (X) device memory and used as input data (3) to execute the sequence program. When an output contact instruction has been executed: Output information 4) is read from the output (Y) device memory, and a sequence program is executed. When an output OUT instruction has been executed: The sequence program's operation result 5) is output to the output module, and is stored in the output (Y) device memory. REMARK Fig.4.9 Input/Output Information Flow at Direct Mode 1: The GX Developer input area can be switched ON and OFF by the following: Test operation by the GX Developer A network refresh by the MELSECNET/H network system Writhing from a serial communication module CC-Link automatic refresh 2: The output (Y) device memory can be switched ON and OFF by the following: Test operation by the GX Developer A network refresh by the MELSECNET/H network system Writhing from a serial communication module CC-Link automatic refresh

63 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS (2) Response lag Output response lags of up to 1 scans can result from input module changes. (See Fig.4.1) Ladder examples DX5 55 Fastest possible DY5E ON DY5E Ladder for switching the DY5E output ON in response to an DX5 input ON LD DX5 OUT DY5E DX5 DY5E OFF OFF ON ON The fastest possible DY5E output ON occurs if the DX5 input is switched ON immediately prior to the step 55 operation. If DX5 is ON when step 55's LD DX5 is executed, DY5E will switch ON within that scan. This condition represents the minimum time lag between the DX5 input ON and the DY5E output ON. Slowest possible DY5E ON LD DX5 OUT DY5E END DX5 DY5E OFF OFF ON ON Lag time (Maximum of 1 scan) The slowest possible DY5E output ON occurs if the DX5 input is switched ON immediately after the step 55 operation. In this case, the DY5E output will switch ON during the next scan. This condition represents the maximum time lag (1 scan) between the DX5 input ON and the DY5E output ON. Fig.4.1 Output "Y" Change in Response to Input "X" Change

64 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS 4.8 Numeric Values which Can Be Used in Sequence Programs Numeric and alphabetic data are expressed by "" (OFF) and "1" (ON) numerals in the Basic model QCPU. This method of expression is called "binary code" (BIN). The hexadecimal (HEX) expression method in which BIN data are expressed in 4-bit units, and the BCD (binary coded decimal) expression method are also possible for the Basic model QCPU. Real numbers may also be used. (See Section 4.8.4) The numeric expressions for the BIN, HEX, BCD, and Decimal (DEC) notations are shown in Table 4.1 below. Table 4.1 BIN, HEX, BCD, and Decimal Numeric Expressions DEC (Decimal) HEX (Hexadecimal) BIN (Binary) BCD (Binary Coded Decimal) A B C D E F F FFE FFF FFFE FFFF

65 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS (1) External numeric inputs to Basic model QCPU When designating numeric settings for the Basic model QCPU from an external source (digital switch, etc.), a BCD (binary coded decimal) setting can be designated which is the same as a decimal setting. However, because the Basic model QCPU operation is based on BIN, if the Basic model QCPU uses values designated in the BCD method as they are, it handles the values as BIN. The Basic model QCPU operation based on such values will be different from the operation specified by the designated values. A BIN instruction is therefore provided for the Basic model QCPU to convert BCD input data to the BIN data which is used by the Basic model QCPU. A program which converts numeric data to BIN data can be created at the sequence program in order to allow numeric settings to be designated from an external source without regard to the corresponding BIN values. [Numeric data designation] Digital switch Basic model QCPU BINP K4X D XF X BCD input BIN data BCD D5 K4Y3 Fig.4.11 Digital Switch Data Input to Basic model QCPU (2) External numeric outputs from Basic model QCPU A digital display can be used to display numeric data which is output from the Basic model QCPU. However, because the Basic model QCPU uses BIN data, it cannot be displayed at the digital display as is. A BCD instruction is therefore provided for the Basic model QCPU to convert the BIN data to BCD data. A program which converts BIN data to BCD data can be created at the sequence program in order to display the output data in a manner identical to decimal data. Basic modle QCPU BINP K4X D [Numeric data designation] Digital display Y3F Y3 BCD D5 K4Y3 BCD output BIN data Fig.4.12 Digital Display of Data from Basic model QCPU

66 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS BIN (Binary Code) (1) Binary code In binary code, numeric values are expressed by numerals "" (OFF) and "1" (ON) numerals. When counting in the decimal system, a carry to the "tens" column occurs following 9 (8 to 9 to 1). In the binary system, this carry occurs following 1 ( to 1 to 1). The binary "1" therefore represents the decimal "2". Binary values and their respective decimal values are shown in Fig.4.2 below. Table 4.2 Binary and Decimal Numeric Value Comparison DEC (Decimal) BIN (Binary) Carry Carry Carry (2) Binary numeric expression (a) Basic model QCPU registers (data registers, link registers, etc.) consist of 16 bits, with a "2 n " value is allocated to each of the register bits. The most significant bit (initial bit) is used to discriminate between "positive" and "negative". 1) When most significant bit is ""...Positive 2) When most significant bit is "1"...Negative The numeric expressions for the Basic model QCPU registers are shown in Fig.4.12 below. Bit name Most significant bit (for positive/negative discrimination) b15 b14 b13 b12 b11 b1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b Decimal value "Negative value" when most significant bit is "1". Fig.4.12 Numeric Expressions for Basic model QCPU Registers (b) Usable numeric data for Basic model QCPU As shown in Fig.4.11, the numeric expression range is to Therefore, numeric data within this range can be stored in the Basic model QCPU registers

67 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS HEX (Hexadecimal) (1) Hexadecimal notation In the hexadecimal system, 4 bits of binary data are expressed by 1 digit. 4 bits of binary data can express 16 values ( to 15). In the hexadecimal system, values from to 15 are expressed by 1 digit. This is accomplished by using alphabetic characters following "9", with a carry occurring after "F", as follows: A comparison of binary, hexadecimal, and decimal numeric expressions is shown in Table 4.3 below. Table 4.3 Comparison of BIN, HEX, and DEC Numeric Expressions DEC (Decimal) HEX (Hexadecimal) BIN (Binary) A B C D E F F Carry (2) Hexadecimal numeric expression Basic model QCPU registers (data registers, link registers, etc.) consist of 16 bits. Therefore, as expressed in hexadecimal code, the numeric value range which can be stored is to FFFFH

68 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS BCD (Binary Coded Decimal) (1) BCD notation BCD numeric expressions are binary expressions with a carry format identical to that of the decimal system. As with the hexadecimal system, BCD expressions are the equivalent of 4 binary bits, although the BCD system does not use the A to F alphabetic characters. A comparison of binary, BCD, and decimal numeric expressions is shown in Table 4.4 below. Table 4.4 Comparison of BIN, BCD, and DEC Numeric Expressions DEC (Decimal) BIN (Binary) BCD (Binary Coded Decimal) Carry (2) BCD numeric expression Basic model QCPU registers (data registers, link registers, etc.) consist of 16 bits. Therefore, as expressed in BCD code, the range of numeric values to be stored is to

69 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS Real number (floating-point data) (1) Real number A real number is a single precision floating-point data. (2) Internal representation of real number data The internal representation of real number data handled by the Basic model QCPU will be described. Two word devices are used to represent real number data as shown below. [Sign] 1. [fixed-point part] [exponent part] 2 When real number data is represented internally, the bit locations and their meanings are as follows. b31 b3 b23 b22 b16 b15 b b31 b23 b3 b b22 Sign Exponent part (8 bits) Fixed-point part (23 bits) Sign: b31 indicates a sign. : Positive 1: Negative Exponent part: b23 to b3 represent n of 2 n. n changes as indicated below depending on the BIN value in b23 to b3. b23 b3 FFH FEH FDH 81H 8H 7FH 7EH 2H 1H H n Not used Not used Fixed-point part: 23 bits in b to b22 indicate the value XXXXXX... when 1.XXXXXX... is set in binary. (3) Calculation examples Calculation examples are given below. ((nnnnnn)x indicates that the data is in X representation.) (a) When 1 is stored 3 (1) 1 (11) 2 ( ) 2 Sign: Positive Exponent part: 3 82 H (11) 2 Fixed-point part: (1 ) 2 Hence, the data is 412 H as shown below. Sign Exponent part Fixed-point part

70 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS (b) When.75 is stored (.75) 1 (.11) 2 ( ) 2 Sign: Positive Exponent part: -1 7E H (111111) 2 Fixed-point part: (1 ) 2 Hence, the data is 3F4 H as shown below. Sign Exponent part Fixed-point part POINT 3 F 4 (1) With the monitor function of GX Developer, the real number data of the Basic model QCPU can be monitored. However, if an attempt is made to monitor data that cannot be represented in real number, e.g. "FFFFH", "-" is displayed. (2) When is represented, b to b31 all turn to. REMARK A binary value below a decimal point is calculated as described below Bit representing 2-1 Bit representing 2-2 Bit representing 2-3 Bit representing 2-4 (.111) 2 = = =(.875)

71 4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS 4.9 Character String Data (1) Character String Data The Basic model QCPU uses ASCII code data. (2) ASCII code character strings ASCII code character strings are shown in the Table below. "H" (NUL code) is used at the end of a character string. b8 b7 b6 b5 b4 b3 b2 b Low Column A B C A B C D E F NUL P ` p! 1 A Q a q " 2 B R b r # 3 C S c s $ 4 D T d t % 5 E U e u & 6 F V f v ' 7 G W g w ( 8 H X h x ) 9 I Y i y * : J Z j z + ; K [ k { (Comma), < L l D E F (Minus) - = M ] m } (Period). > N ^ n Under line /? O _ o POINT Character strings are available for the $MOV instruction only

72 5 ASSIGNMENT OF I/O NUMBERS 5 ASSIGNMENT OF I/O NUMBERS This section describes the necessary information on the I/O number assignment for the data exchange between Basic model QCPU and input/output modules or intelligent function modules. 5.1 Relationship Between the Number of Stages and Slots of the Extension Base Unit QJCPU The QJCPU can configure a system with a total of three base units: one main base unit and two extension base units. Note that the number of usable slots (modules) is 16 slots including vacant slots. For example, if you set slot 2 for "vacant, zero points" as shown below, it occupies one slot. Hence, the following system uses five slots, slot - slot 4. QJCPU QX4 QX4 Empty, points QY4 QY4 5 1 slot occupied Install modules to slots Installing any module to slot 16 or later will result in an error (SP. UNIT LAY ERR.) Slot No. Setting of extension stage (Refer to Section 5.2) QJCPU 1 Power supply CPU slot Q68B 2 Power supply Prohibit Prohibit Q65B Modules cannot be installed. (Installing modules will result in error.) When the GOT has been bus-connected, one slot of extension base 1 is used. Also one GOT occupies 16 I/O points. When using the GOT, consider the number of slots and the number of I/O points. Refer to the GOT Manual for details of busconnecting the GOT

73 5 ASSIGNMENT OF I/O NUMBERS QCPU, Q1CPU The QCPU or Q1CPU can configure a system with a total of five base units: one main base unit and four extension base units, or with one slim type main base unit. Note that the number of usable slots (modules) is 24 slots including vacant slots. Power supply QCPU QX4 QX4 Empty, points QY4 QY4 1 slot occupied Install modules to slots Installing any module to slot 24 or later will result in an error (SP. UNIT LAY ERR.). Hence, the following system uses five slots, slot - slot Slot No. 5 Setting of extension stage (Refer to Section 5.2) 1 Power supply Power supply QCPU Q35B CPU slot Q65B Power supply Q65B Power supply Q65B 4 Power supply Invalid Q65B Module cannot be installed. (Installing module will result in error.) When the GOT has been bus-connected, one slot of extension base 1 is used. Also one GOT occupies 16 I/O points. When using the GOT, consider the number of slots and the number of I/O points. Refer to the GOT Manual for details of busconnecting the GOT

74 5 ASSIGNMENT OF I/O NUMBERS 5.2 Installing Extension Base Units and Setting the Number of Stages As extension base units, you can use the Q5 B and Q6 B that are designed for installation of Q series-compatible modules. There are the following precautions for use of extension base units. When the slim type main base unit is used, an extension base unit cannot be connected. The QA1S6 B and QA65B extension base units are unusable. (1) Setting order of the extension stage numbers for extension base units Extension base units require the setting of the extension stage numbers using the stage setting connector. Assign the extension stage numbers starting from 1 to 2/4 to the extension base units counting from the one which is connected to the main base unit. (2) Cautions to assign extension stage numbers to extension base units (a) Assign consecutive numbers to extension stages. If you assign stage numbers to base units in "Auto" mode and assign some stage numbers to no modules, "" is assigned to the skipped stage as the number of slots. Consequently, the number of vacant slots does not increase. The I/O assignment also assigns "" to the skipped stage as the I/O points. (b) (c) Setting of extension stage Stage setting connector 1 It is impossible to set and use the same extension stage number with two or more extension base units. You cannot use the system if two or more connector pins are inserted to the stage setting connector. On the contrary, you cannot use the system if no connector pin is inserted to the stage setting connector. Power supply QCPU Power supply Q38B Q68B Main base unit 2 Power supply Q68B

75 5 ASSIGNMENT OF I/O NUMBERS 5.3 Base Unit Assignment (Base Mode) There are the "Auto mode" and "Detail mode" to assign the number of modules to the main base unit, slim type main base unit and extension base units. (1) Auto mode In Auto mode, base unit assignment is made according to the installable slots of the main, slim type main and extension base units. The I/O numbers are assigned according to the number of modules that can be installed to the used base unit. Since the AnS series main and extension base units were fixed to eight slots, a three/five-slot base unit occupied eight slots. The Basic model QCPU, which occupies only the installable slots of a base unit, occupies only three slots when a three-slot base unit is used. (a) For 3-slot base unit: 3 slots are occupied Q33B type main base unit 1 2 Power supply QCPU Q63B type extension base unit Five slots are not occupied. Power supply Q63B type extension base unit Five slots are not occupied. Power supply Five slots are not occupied

76 5 ASSIGNMENT OF I/O NUMBERS (b) For 5-slot base unit/qjcpu: 5 slots are occupied Q35B type main base unit Power supply QCPU Q65B type extension base unit Three slots are not occupied Power supply Q65B type extension base unit Three slots are not occupied Power supply Three slots are not occupied (c) For 8-slot base unit: 8 slots are occupied Q38B type main base unit Power supply QCPU Q68B type extension base unit Power supply (d) For 12-slot base unit: 12 slots are occupied Q312B type main base unit Power supply QCPU Q612B type extension base unit Power supply

77 5 ASSIGNMENT OF I/O NUMBERS (2) Detail mode (a) In Detail mode, the number of slots is assigned to the individual base units (main base unit, slim type main base unit and extension base units)by setting the I/O assignment of PLC Parameter. Use this mode to match the number of slots to the one for the AnS-series base units (8 fixation). Since one slot is occupied if an empty slot is set for zero points in I/O assignment, this mode is also used to make the slot without a module and later unrecognized. (b) Cautions on setting the number of slots The number of slots can be set regardless of the number of slots of the module being used. However, the number of slots must be set for all the base units in use. If the number of slot is not set for all the base units, I/O assignment may not work correctly. The followings result if the preset number of slots differs from that of the installed base units. 1) When the designated number of slots is larger than that of the installed base unit: Among the designated slots, those after the slots occupied by the installed base unit will be empty slots. For example, when 8 slots are designated for a 5-slot base unit, 3 slots will be empty slots. Q35B type main base unit Power supply QCPU Empty Empty Empty Three slots are occupied. The number of points for the empty slots is the one designated by PLC system of PLC Parameter or with I/O assignment. (Default value is 16 points.) 2) When the designated number of slots is smaller than that of the base unit being used: The slots other than those designated are disabled. For example, when 8 slots are designated for a 12-slot base unit, the 4 slots on the right of the base unit are disabled. (If a module is installed to the disabled slot, an error [SP. UNIT LAY ERR.] occurs.) Q312B type main base unit Power supply QCPU Invalid Invalid Invalid Invalid Module can be installed. (When eight slots are set) When module is installed, an error occurs

78 5 ASSIGNMENT OF I/O NUMBERS (3) Setting screen and setting items for Base mode of GX Developer (e) (a) (b) (c) (d) (a) (b) (c) (d) (e) Base model name Designate the model name of the installed base unit with 16 or less characters. Basic model QCPU does not use the designated model name. (It is used as a user's memo or parameter printing) Power model name Designate the model name of the installed power supply module with 16 or less characters. Basic model QCPU does not use the designated model name. (It is used as a user's memo or parameter printing) Increase cable name Designate the model name of the extension cable being used with 16 or less characters. Basic model QCPU does not use the designated model name. (It is used as a user's memo or parameter printing) Points (Used with Basic model QCPU) Select the number of points for the slot of the base unit being used from the followings: 2 (2 slots) 3 (3 slots) 5 (5 slots) 8 (8 slots) 1 (1 slots) 12 (12 slots) 8 fixation/12 fixation (Used with Basic model QCPU) Select either option to designate the number of slots for all base units to the same number

79 5 ASSIGNMENT OF I/O NUMBERS 5.4 What are I/O Numbers? I/O numbers are used in sequence program for reception of ON/OFF data at Basic model QCPU and output of ON/OFF data from Basic model QCPU to outsides. Input (X) is used for the reception of ON/OFF data at Basic model QCPU. Output (Y) is used for the output of ON/OFF data from Basic model QCPU. I/O numbers are expressed as hexadecimals. When using 16-point I/O modules, I/O numbers are consecutive numbers that 1 slot has 16 points to F as follows. The module that is mounted in the base unit assigns the following: For the input module, "X" is assigned at the beginning of the I/O number. For the output module, "Y" is assigned at the beginning of the I/O number. For the case of input module For the case of output module Power supply module X X 1 X 2 Y 3 Y 4 QCPU X2C X F X 1 F X 2 F Y 3 F Y 4 F 16 input points 16 input points 16 input points 16 output points 16 output points

80 5 ASSIGNMENT OF I/O NUMBERS 5.5 Concept of I/O Number Assignment I/O numbers of main base unit, slim type main base unit and extension base unit Basic model QCPU assigns I/O numbers at power-on or reset according to the following items. As a result, you can control Basic model QCPU without using GX Developer for I/O assignment. To assign I/O numbers, follow the items below: (1) Number of slots of base units The number of slots of the main base unit, slim type main base unit and extension base units changes depending on the Base mode setting. (For Base mode, refer to Section 5.3.) (a) In Auto mode, the number of slots is determined as the available number of modules installed to each base unit. For example, 5 slots are assigned for a 5-slot base unit, and 12 slots are assigned for a 12-slot base unit. (b) In Detail mode, the number of slots is determined as the one designated by I/O assignment of PLC Parameter. (2) Order of I/O number assignment The I/O numbers are assigned from left to right consecutively, starting from H assigned to the module mounted on the right of the Basic model QCPU on the main base unit or slim type main base unit. (3) Order of I/O number assignment for extension base units The I/O numbers for extension base units are assigned continuing from the last number of the I/O number of the main base unit. The I/O numbers for extension base units are assigned to the units from left (silkscreened I/O of extension base unit) to right consecutively, in the order of the setting of the stage setting connectors of the extension base units. (4) I/O numbers of each slot Each slot of base units occupies the points of I/O numbers of the installed I/O modules or intelligent function modules. When 32-point input module is installed on the right of Basic model QCPU, X to X1F are assigned as I/O numbers. (5) I/O numbers of empty slots If the base unit has vacant slots where no I/O modules or no intelligent function modules are installed, the points designated by PLC system setting of PLC Parameter are assigned to the empty slots. (Default value is 16 points.) POINT When the assignment of base units is conducted in Auto mode, the number of empty extension stages is not assured even if the extension stage is skipped at the stage number setting connector of the base unit. (Smaller input/output numbers are assigned first.) To reverse empty extension stages for future extension, use the PLC parameter to set the base unit

81 5 ASSIGNMENT OF I/O NUMBERS The following shows the example of the I/O number assignment when the base unit is set in Auto mode without I/O assignment: Q35B (5 slots occupied) Slot No. Extension cable Power supply module QCPU Input module Input module Input module Output module Allocate the I/O number with the I/O points of each slot points points points points points... I/O numbering direction X X1 X2 Y4 Y5 XF X1F X3F Y4F Q65B (5 slots occupied) Output module Y8F The slot numbers of the 1st stage's extension base unit continue from the last slot number of the main base unit. 1 IN OUT Power supply module Intelligent function module Intelligent function module Intelligent function module Output module Empty points points points points points Empty slot points designated on the PLC system Setting screen under the parameter mode are allocated. (Default: 16 points) 9 B D YF 1 AF CF Q68B (8 slots occupied) 1 11 EF YFF 1F The slot numbers of the 2nd stage's extension base unit continue from the last slot number of the 1st stage's extension base unit IN OUT Power supply module Input module Input module Intelligent function module Intelligent function module Intelligent function module Output module points points points points points points Output module Output module points points X11 X Y19 Y1A Y1B X11F X12F 14F 16F 18F Y19F Y1AF Y1BF POINT The above example shows the case where the intelligent function module has 32 I/O points. The number of I/O points may vary depending on the intelligent function module. Refer to the manual of the intelligent function module being used and check the number of the I/O points before assigning the I/O numbers

82 5 ASSIGNMENT OF I/O NUMBERS Remote station I/O number In a CC-Link remote I/O system, you can exercise control after assigning the inputs (X) and outputs (Y) of the Basic model QCPU devices to the I/O and intelligent function modules of remote stations. Also, the inputs (X) and outputs (Y) are used as the refresh destinations (Basic model QCPU side devices) of the link inputs and outputs (LX, LY) of the MELSECNET/H. Take care not to overlap the I/O numbers of the MELSECNET/H refresh destinations and the I/O numbers of the CC-Link remote I/O system. Power module QCPU QJ61BT11 QJ71LP21 QX41 QY41 Q64AD CC-Link Remote station Remote station Allocation of QCPU input (X) and output (Y) possible X/Y to X/YFF X/Y1 to X/Y1FF X/Y2 When using Basic model QCPU device input (X) and output (Y) in remote stations, I/O numbers that succeed the numbers used by the main base unit and extension base units' input/output modules and intelligent function modules will be allocated. For example, if X/Y to X/YFF are being used by the main base unit and extension base units' input/output modules and intelligent function modules, then numbers above X/Y1 can be used by the remote station. However, the I/O numbers for remote stations should be set in consideration of additions to the main base unit and extension base units' input/output modules and intelligent function modules. (Example) If 256 points from X/Y to X/YFF are being used by the main base unit and extension base units, and 256 points from X/Y1 to X/Y1FF are to be held back for use with future additions, then the situation shown in the diagram below is to be observed. Input/Output (X/Y) For CC-Link remote station I/O numbers being used by the main base unit and extension base units Held back for future additions to I/O numbers that can be used by remote stations X/Y7FF POINT If network parameter setting has not been made in a CC-Link system, 124 points of X/Y4 to X/Y7FF are assigned to the CC-Link master/local module of lower I/O numbers

83 5 ASSIGNMENT OF I/O NUMBERS 5.6 I/O Assignment by GX Developer This section describes the I/O assignment using GX Developer Purpose of I/O assignment by GX Developer I/O assignment by GX Developer is used under the following circumstances. (1) Reserving points when converting to module other than 16-point modules You can reserve the number of points in advance so that you do not have to change the I/O numbers when the current module will be changed to one with a different number of I/O points in the future. For example, you can assign a 32-point I/O module to the slot where a 16-point I/O module is installed at present. (2) Preventing I/O numbers from changing when converting modules You can avoid the change in the I/O numbers when an I/O module other than 16- point module or intelligent function module is removed due to a malfunction. (3) Changing the I/O numbers to those used in the program When the designed programs I/O numbers are different from the actual system I/O numbers, each modules I/O numbers of base units can be set to program-i/o numbers. (4) Setting the input response time of input modules and interrupt modules (I/O response time) The input response time of the input modules and interrupt modules can be changed to match it to the system. (For details, refer to Section 7.7.) (5) Setting the switch of intelligent function modules Set the operation conditions of the intelligent function modules. (For details, refer to Section 7.1.) (6) Setting outputs during Basic model QCPU error Set the output (retain/clear) status of the output modules and intelligent modules when the Basic model QCPU stops the operation due to a stop error. (For details, refer to Section 7.8.) (7) Setting Basic model QCPU operation during a hardware error of intelligent function modules Set the operation (continue/stop) status of the Basic model QCPU if a hardware error occurs in an intelligent function module. (For details, refer to Section 7.9.) POINT (1) The I/O assignment setting of the PLC parameters are made valid when the PLC is powered on or the Basic model QCPU is reset. When you have changed the PLC parameter values, power on the PLC again or reset the Basic model QCPU. (2) I/O assignment must be made to change the response time of the input module or make the switch setting of the intelligent function module. (3) If any of the I/O modules other than the 16-point modules fails without I/O assignment being made using GX Developer, the I/O numbers after that module may change, leading to a malfunction. Therefore, it is recommended to make I/O assignment using GX Developer

84 5 ASSIGNMENT OF I/O NUMBERS Concept of I/O assignment using GX Developer (1) I/O assignment for each slot You can designate "Type" (module type), "Points" (number of I/O points), and "Start XY" (head I/O number) individually for each slot of the base unit. For example, to change the number of I/O points of the designated slot, you can designate only the number of I/O points. The items other than designated are set to the status where the base unit is installed. The I/O assignment is conducted according to the I/O assignment setting of PLC Parameter. (a) (b) (c) (d) (e) (a) (b) Slot Displays the slot No. and the ordinal position of the slot in the base unit. If the base unit is not designated in Detail mode, the stage number of the base unit is shown as " ", and the ordinal number of a slot is counted from slot of the main base unit. Type (Used with Basic model QCPU) Select the type of module being installed from the followings: Empty (Empty slot) Input (Input module) Hi Input (Q series corresponding high speed module) Output (Output module) I/O Mix (I/O mixed module) Intelligent (Intelligent function module) Interrupt (Q series corresponding interruption module) If the type is not designated, the type of the actually installed module is used

85 5 ASSIGNMENT OF I/O NUMBERS (c) (d) (e) Model name Designate the model name of the installed module with 16 or less characters. Basic model QCPU does not use the designated model name. (It is used as a user's memo or for parameter printing.) Points (Used with Basic model QCPU) To change the number of I/O points of each slot, select it from the followings: ( point) 128 (128 points) 16 (16 points) 256 (256 points) 32 (32 points) 512 (512 points) 48 (48 points) 124 (124 points) 64 (64 points) If the number of I/O points is not designated for a slot, the one of the actually installed module is used. : Setting is enabled for the Q/Q1CPU only. (Since the number of I/O points of the QJCPU is 256, you cannot set 512/124 points.) Start XY (Used with Basic model QCPU) 1) When the I/O number of each slot is changed, you should designate the head I/O number according to the change. If Start XY is not designated for a slot, the I/O number continuing from the last number of the currently designated slot is assigned. 2) Avoid the I/O number designation of each slot from overlapping the I/O numbers assigned by Basic model QCPU. An error (SP. UNIT LAY ERR.) occurs when the I/O numbers overlap. (2) Slot status after I/O assignment When the I/O number is assigned to a slot, the assigned I/O number takes precedence regardless of the actual installation of a module. (a) If the designated number of I/O points is smaller than that of the actually installed input/output module, some I/O points of the installed module are not used. For example, if a slot where a 32-point input module is installed is designated for a 16-point input module, the latter 16 points of the 32-point input module are disabled. (b) (c) (d) "SP. UNIT LAY ERR." occurs if the number of points set is less than the number of points of the installed intelligent function modules. If the specified number of I/O points is larger than that of the actually installed input/output modules, the points exceeding the actual points are regarded as dummies. The module type of the installed module must be consistent with that of the I/O assignment. Inconsistent I/O assignment may result in malfunctions

86 5 ASSIGNMENT OF I/O NUMBERS Actually installed module I/O assignment Result Input module Output/Empty Empty Output module Input/Empty Empty Input module/output module Intelligent Error (SP. UNIT LAY ERR.) Intelligent function module Empty Empty Input/output Error (SP. UNIT LAY ERR.) Vacant slot Intelligent No error occurs. (e) Be sure to assign the I/O numbers so that the last I/O number is within the range of FFH/3FFH or less. An error (SP. UNIT LAY ERR.) occurs when the last I/O number exceeds FFH/3FFH. (System monitor of GX Developer shows " " as an I/O address.)

87 5 ASSIGNMENT OF I/O NUMBERS 5.7 Examples of I/O Number Assignment This section shows the examples of the I/O number assignment using GX Developer. (1) When changing the number of points of an empty slot from 16 to 32 points: Reserve 32 points to the slot position currently empty (slot No. 3) so that the input/output numbers do not change when a 32-point input module is installed in the future. (The empty slot for slot No. 12 is not changed from 16 points.) 1 (a) System configuration and I/O number assignment before the I/O assignment with GX Developer Q38B Power supply module QCPU 2 Input module Input module Input module Empty Output module Output module Output module Output module points points points points points points points points X X2 X4 6 Y7 Y9 YB YD X1F X3F X5F 6F Y8F YAF YCF YEF Q68B IN OUT Power supply module Intelligent function module Intelligent function module Intelligent function module Intelligent function module Empty Output module Output module Output module points points points points points points points points F Y18 Y1A Y1C 1F 12F 14F 16F 17F Y19F Y1BF Y1DF REMARK 1: This is the case where the number of points for an empty slot is set to 16 with PLC system setting of PLC Parameter. 2: Since the number of I/O points of the QJCPU is 256, use it within the range X/Y to X/YFF

88 5 ASSIGNMENT OF I/O NUMBERS (b) I/O assignment with GX Developer Designate slot No. 3 to "32 points" on the I/O assignment screen of GX Developer. Select 32 points. (When the type is not selected, the type of the installed module will be selected.) (c) I/O number assignment after the I/O assignment with GX Developer Q38B Power supply module QCPU Input module Input module Input module Empty Output module Output module Output module Output module points points points points points points points points X X2 X4 6 Y8 YA YC YE X1F X3F X5F 7F Y9F YBF YDF YFF Q68B IN OUT Power supply module Intelligent function module Intelligent function module Intelligent function module Intelligent function module Empty Output module Output module Output module points points points points points points points points Y19 Y1B Y1D 11F 13F 15F 17F 18F Y1AF Y1CF Y1EF

89 5 ASSIGNMENT OF I/O NUMBERS (2) Changing the I/O number of slots Change the I/O number of a currently vacant slot (slot No. 3) to X2 through X21F so that the I/O numbers of slot No. 4 and later slots do not change when a 32-point input module is installed to the currently vacant slot (slot No. 3). 3 (a) System configuration and I/O number assignment before the I/O assignment with GX Developer Q38B Power supply module QCPU Input module Input module Input module Empty Output module Output module Output module Output module points points points points points points points points X X2 X4 6 Y7 Y9 YB YD X1F X3F X5F 6F Y8F YAF YCF YEF Q68B IN OUT Power supply module Intelligent function module Intelligent function module Intelligent function module Intelligent function module Empty Output module Output module Output module points points points points points points points points F Y18 Y1A Y1C 1F 12F 14F 16F 17F Y19F Y1BF Y1DF REMARK 3: Since the number of I/O points of the QJCPU is 256, use it within the range X/Y to X/YFF

90 5 ASSIGNMENT OF I/O NUMBERS (b) I/O assignment with GX Developer Designate the head I/O number of slot No. 3 to "2" and that of slot No. 4 to "7" on the I/O assignment screen of GX Developer. "2" is designated as the head I/O number. "7" is designated as the head I/O number. (When the head I/O number is not designated, the I/O number following the 3rd slot will be assigned.) (c) I/O number assignment after the I/O assignment with GX Developer Q38B Power supply module QCPU Input module Input module Input module Input module Output module Output module Output module Output module points points points points points points points points X X2 X4 X2 Y7 Y9 YB YD X1F X3F X5F X21F Y8F YAF YCF YEF Q68B IN OUT Power supply module Intelligent function module Intelligent function module Intelligent function module Intelligent function module Empty Output module Output module Output module points points points points points points points points F Y18 Y1A Y1C 1F 12F 14F 16F 17F Y19F Y1BF Y1DF 5.8 Checking the I/O Numbers System monitor of GX Developer allows the check of the installed modules of Basic model QCPU and their I/O numbers. (For system monitor, refer to Section 7.18.)

91 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU (1) Data handled by Basic model QCPU The Basic model QCPU stores such data as parameter, program and device comments into program memory. When ROM operation is performed, the parameter and program in the program memory are written to standard ROM. (2) Write of parameter and program using GX Developer Such data as parameter, program and comment are written to the program memory of the Basic model QCPU by GX Developer (online write to PLC). For online write to PLC, specify the type (e.g. parameter, program, comment) of the data to be written to the Basic model QCPU

92 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU 6.1 About Basic model QCPU's Memory (1) User Memory A user memory can be created within the memory of the Basic model QCPU with GX Developer/sequence program. There are the following user memories. Program memory Standard ROM Standard RAM CPU shared memory (refer to Section 16.4) : QCPU, Q1CPU only (a) Program memory This memory stores program used by the Basic model QCPU to actually perform arithmetic operation. Program stored in the standard ROM is booted (read) into the program memory for arithmetic operation. (Boot operation) (b) Standard ROM Parameter and program are stored in the standard ROM. These data are used for ROM operation of the Basic model QCPU. The parameter and program are batch-copied from the program memory to the standard ROM. (ROMed program memory) (c) Standard RAM This memory stores file register data. The file registers of the standard RAM allow fast access like the data registers. 6 Parameter Data Name Intelligent function module parameter (2) Types of Data Stored in the Basic model QCPU Memory The table below shows the type of data stored in a program memory, standard RAM, and standard ROM. QJCPU Built-In Program Memory Standard ROM Program Memory Q/Q1CPU Built-In Standard RAM Standard ROM File name PARAM.QPA IPARAM.QPA Sequence program MAIN.QPG SFC program MAIN-SFC.QPG File register 3 MAIN.QDR Device comment MAIN.QCD Device initial value MAIN.QDI : Needed, : Stored, : Not stored

93 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU REMARK 1: To execute a program actually, booting must be specified for the program memory using the PLC parameter. 2: Data can be written with GX Developer. Device comments cannot be used in an instruction of a sequence program. 3: The standard RAM can store only one file of 64k points of file registers. 4: The data of either the sequence program or SFC program is required. (3) Drive Number (a) The Basic model QCPU uses drive numbers to control program memory, standard RAM and standard ROM. On GX Developer, however, specify the target memory (program memory, standard RAM, standard ROM) to write/read the parameter, program, etc. to/from the Basic model QCPU. (b) The table below shows the drive numbers used to specify a selected memory (program memory, standard RAM or standard ROM) when using a sequence program. The drive number must be used to specify a selected memory when the read/write is made through access from a serial communication module. QCPU built-in Memory Drive Number Program memory Standard RAM 3 Standard ROM 4 (4) Memory Capacity and Formatting The table below shows the size of a memory of the Basic model QCPU and whether to format a memory. QJCPU QCPU Q1CPU Whether to Format Standard RAM None 128k byte Not required. 5 Program memory 58k byte 94k byte 94k byte Not required. 5 Standard ROM 58k byte 94k byte 94k byte Not required. 5: Before using the Basic model QCPU, always format the memory using GX Developer

94 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU 6.2 About Program Memory (1) What is the Program Memory? (a) The program memory is an internal RAM that stores program executed by the Basic model QCPU. (b) (c) The data storage in the program memory is backed up by Basic model QCPU's built-in battery (Q6BAT). Before using the Basic model QCPU, always format the memory using GX Developer. 1 (However, if the memory is in an initial status or has been unformatted due to battery (Q6BAT) exhaustion, the Basic model QCPU does formatting automatically at power-on or reset of the PLC. For details regarding the formatting procedure by the GX Developer, refer to GX Developer manuals. Table 6.1 Memory capacity after formatting 1 Model Name Memory Max. Number of Program Stored QJCPU 58 kbyte 2 2 QCPU 94 kbyte 2 2 Q1CPU 94 kbyte 2 2 POINT Program is stored in the program memory in 4 bytes units. (2) Data Storage Data on parameter and program can be stored in the program memory. For the types of data stored in the program memory, see Section 6.1. REMARK 1: When the program memory is formatted by GX Developer, the user setting area and multi-block write during RUN area in the system area can also assigned. (-3k steps can be set to the user setting area of the system area in 1k step increments.) The user setting area (data) in the system area is used for registering monitor data from GX Developer connected to serial communication module. Presetting the user setting area of the system area enables fast monitoring from GX Developer connected to the serial communication module, etc. Although the designation of a user setting area speeds up monitoring from GX Developer connected to serial communication module, it also reduces the amount of space available for user files. 2: One sequence program and one SFC program can be stored

95 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU 6.3 About Standard ROM (1) What is the standard ROM? (a) The standard ROM is used for the ROM operation of the Basic model QCPU. (b) (c) Program stored in the standard ROM and booted (read) to the program memory after the setting is made in the Boot File sheet of the PLC Parameter dialog box. Write to the standard ROM is performed by "Write the program memory to ROM" in online write to PLC (flash ROM) of GX Developer. (Refer to Section 6.4.2) POINTS Writing program memory to ROM copies the program memory data to the standard ROM as-is. (2) Data Storage A standard ROM stores data such as parameter and program. See Section 6.1 for the data to store in the standard ROM. (3) Setting of ROM operation When performing ROM operation, select "boot operation from standard ROM" in the boot file setting of PLC parameter

96 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU 6.4 Executing Standard ROM Program (Boot Run) and Writing Program Memory to ROM Executing Standard ROM Program (1) Executing Basic model QCPU program (a) The Basic model QCPU processes program which is stored in the program memory. The Basic model QCPU does not perform operation of program stored in the standard ROM. (b) The program stored in the standard ROM is booted (read) to the program memory to perform arithmetic operation. (2) Preparation for Boot Run Perform the following steps in preparation for boot run: (a) Create a program using GX Developer. Create a program used for the boot run. (b) Select a boot file using GX Developer. Select "Do boot from standard ROM" in the boot file setting of PLC parameter. (c) Write of parameter, program and like to standard ROM using GX Developer 1) Using online "write to PLC" of GX Developer, write parameter and program to the program memory. 2) Write the parameter and program in the program memory to the standard ROM by ROMing the program memory. Refer to Section for write of parameter, program and the like to the standard ROM using GX Developer

97 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU (d) Execute a program. Resetting the Basic model QCPU with the RUN/STOP/RESET switch starts boot from the standard ROM. Refer to the following manuals for the reset operation of the Basic model QCPU. QCPU (Q Mode) User's Manual (Hardware) Basic Model QCPU (Q Mode) User's Manual (Hardware Design, Maintenance and Inspection) (3) Operation for Stopping Boot Run When stopping boot run, perform the following operation. 1) Format the program memory. 2) ROM the program memory. (The parameter and sequence program in the standard ROM are erased.) 3) Write the parameter and sequence program to the program memory. (4) Precautions for Executing Program in the Standard ROM (a) When performing boot run, store the following files into the standard ROM. Parameter 1 Intelligent function module parameter Sequence program 2 SFC program 2 Device comment Device initial value 1: Required 2: Either one sequence program or one SFC program is required. (b) (c) If program is written in the program memory during the RUN status while a boot run is performed by using a standard ROM, any change made will not be reflected in program stored in the standard ROM. If the PLC is powered ON/reset after writing sequence program to the program memory, the contents of the program memory may change. This can be caused when the boot run has been set. 1) Format the program memory. 2) Write the parameter and sequence program to the program memory. 3) Transfer the parameter written in the program memory to the ROM

98 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU Write program memory to ROM To perform write to the standard ROM with GX Developer, perform "Write the program memory to ROM" in online Write to PLC (Flash ROM) of GX Developer. Files cannot be written to the standard ROM by online "Write to PLC" of GX Developer. (1) Write the program memory to ROM (a) The "Write the program memory to ROM" function allows a batch of files stored in a program memory to be written in a standard ROM. Refer to Section 12.1 for the procedure of writing the program memory to ROM. This function writes the debugged program stored in the program memory to ROM. (b) (c) (d) When the "Write a memory to ROM" function is executed, all files stored in the standard ROM are erased before a batch of files stored in a program memory are written. No files can be added to the standard ROM. The memory capacity of a standard ROM is the same as that of a program memory. A memory of a larger size than the memory capacity of a program memory cannot be used. For write of the program memory to ROM by GX Developer, check is made in 18 seconds when the time check period of GX Developer is 18 seconds or shorter. To execute the "Write the program memory to ROM" function via the CC-Link network by operating from a GX Developer at a local station, set the length of CC-Link's CPU monitoring time (SWA) to 18 seconds or longer

99 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU 6.5 About Standard RAM (1) What is the standard RAM? (a) The standard RAM is used when using file registers. (QCPU, Q1CPU only) (b) (c) The standard RAM data are backed up by the battery (Q6BAT) fitted to the CPU module. Even if ROM operation is to be performed with a program written to the standard ROM, the battery is needed when the standard RAM is used by the file registers. Data can be written onto the standard RAM by using the online function: "Write to PLC." (2) Stored Data A standard RAM holds one file: file register file. Any other files cannot be written onto a standard RAM

100 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU 6.6 Program File Configuration (1) Program File Configuration (a) Program files consist of a file header and an execution program. File header 34 steps (by default) Execution program Areas are reserved in units of 4 bytes Steps secured for write during RUN 5 steps (b) When a program file is stored into the program memory of the Basic model QCPU, the program capacity is a total of the above three different areas. 1) File header: The file name, file size, and file creation data, etc., are stored in this area. The file header size is 25 to 35 steps (1 to 14 bytes), which changes depending on the device setting of the PLC parameter dialog box. (Default:34steps) 2) Execution program: The created program is stored in this area. 1 step is 4 bytes. 3) Steps secured for write during RUN: This area is used when write during RUN that will increase the number of steps is performed by GX Developer. When write during RUN that will increase the number of steps is performed by GX Developer, the number of remaining steps in the steps secured for write during RUN is displayed. The default setting is 5 steps (2 bytes). The number of steps secured for write during RUN can be changed by GX Developer (program for online write to PLC). If the number of steps secured for write during RUN is insufficient for write during RUN, the number of steps secured for write during RUN can be set again. (Refer to Section ) (2) The size of the program displayed by GX Developer During programming at the GX Developer, the program size (the total of the file header size and the number of created program steps) is displayed as the number of steps as shown below. During programming, the size of the program created is displayed. "Number of steps used" display

101 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU 6.7 GX Developer File Operation and File Handling Precautions File operation Using the "online" function of the GX Developer, the file operations shown in Table 6.5 below are possible with regard to files stored in the program memory and standard ROM. However the available file operations will vary according to the presence or absence of a password (registered by GX Developer) and the Basic model QCPU RUN/STOP status. Table 6.5 File Operations from GX Developer File Operation Read from PLC Write to PLC Verify with PLC Write the program memory to ROM Delete PLC data Format PLC memory Arrange PLC memory Write during RUN in the ladder mode Operation Enabled/Disabled A B C Operation Description Files are read from target memory. Files are written to the program memory. Verify the target memory and the GX Developer's file. Write a batch of files from the program memory to the standard ROM. A file stored in memory is deleted. Memory formatting is executed. Memory files which ate no longer contiguous are re-organized to make them contiguous. Write changes made in the ladder mode into the program memory. : Execution enabled, : Execution enabled on password match, : Execution disabled REMARK 1) The codes used at the "operation enabled/disabled" item in the above table are explained below. Table 6.6 Operation enabled/disabled Code A B C Description When "write prohibit" password is registered in a file When "read/write prohibit" password is registered in a file When Basic model QCPU RUN status is in effect

102 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU File handling precautions (1) Power OFF (or reset) during program operation (a) If power is switched off during any file operation that will not cause a file shift, the memory data will be indefinite. (b) When the battery (Q6BAT) is used for backup on the Basic model QCPU, switching power off during any of the following operations that will cause a file shift will make the program memory data indefinite. File size change Arrange PLC memory New file creation (2) Simultaneous write to the same file from multiple GX Developers The Basic model QCPU does not allow access from other GX Developers to the file being written. It does not allow write from other GX Developers to the file being accessed, either. Therefore, to perform write from multiple GX Developers to the same file, start the processing of next GX Developer after completing the current processing. (3) Simultaneous access to different files from multiple GX Developers The Basic model QCPU allows simultaneous access from multiple GX Developers to up to 1 different files of the same CPU module

103 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU File capacity Function Drive header 64 The file size differs with the types of files used. When a program memory, standard RAM and standard ROM are used, calculate the size of a file with reference to the table 6.7 shown below. Space for file storage is available as shown below: Program memory, standard ROM: 4 bytes Table 6.7 List of File Size Estimated File Size (in byte) Default: 522 (increased by the parameter setting) For Reference: Boot setting to 96 Parameter With the MELSECNET/H : Increased to up to 496 With Ethernet setting : Maximum 922 With CC-Link setting : Increased to up to 251/module With remote password setting : (No. of modules 1), increased up to 164 Sequence program (4 ((number of steps) + (number of steps secured for write during RUN)) 74 + (Total of comment data size of each device) Device comment Comment data size of a device = a + 4 b a: quotient of (Number of device points) / 256 b: remainder of (Number of device points) / 256 File register 2 (Number of file register points) Device initial value n + 2 (total number of device points set for device initial value) n: Number of device initial value settings Intelligent parameter 68 + (24 number of set modules) + parameter size of each utility User setting area Set value at the time of formatting ( to 3k) Multi-block write during RUN setting Set value at the time of formatting (/1.25k/2.5k) *: 136 is the default (increased by the parameter setting)

104 6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU An example for calculating the amount of memory capacity required when writing the parameter and sequence program in the program memory is shown below. (1) Writing file File name Program capacity parameter sequence program 5 steps (2 bytes) Represents the program capacity displayed with the GX Developer (total number of file headers and created program steps.) (See Section 6.6.) (2) Writing conditions Parameter: Default setting (522 bytes) Steps secured for write during RUN: 5 steps (2 bytes) (3) File memory capacity calculations File name File capacity Memory capacity Parameter 522 bytes 522 bytes Sequence Sequence program capacity 2, bytes program Steps secured for write during RUN 2 bytes 2, bytes File memory capacity total A program memory capacity in units of 4 bytes (1 step) is secured. 22,522 bytes

105 7 FUNCTION 7 FUNCTION Function of Basic model QCPU module is as follows: 7.1 Function List Functions of Basic model QCPU are listed below: 7 Item Description Reference Constant scan Function to make the scan time constant. Section 7.2 Latch function Function to maintain the device data when performing the reset operation during power off. Section 7.3 Selection of output status at switching from STOP to RUN This function selects the output (Y) status (re-output of status before STOP/output of status after execution of operation) when the Basic model QCPU is switched from the STOP status to the RUN status. Section 7.4 Clock function Function to execute the Basic model QCPU internal clock. Section 7.5 Remote operation Function to operate the Basic model QCPU from a remote place. Section 7.6 Remote RUN/STOP Function to stop and start operating the Basic model QCPU. Section Remote PAUSE Function to temporarily stop the Basic model QCPU. Section Remote RESET Function to reset the Basic model QCPU. Section Remote latch clear Function to clear the Basic model QCPU latch data. Section Selection of input response time of input module/hybrid I/O module Selection of input response time of high-speed input module Selection of input response time of interrupt module Error-time output mode setting Hardware error-time CPU operation mode setting Setting of intelligent function module switches This function selects the response time of input module/hybrid I/O module from among 1ms, 5ms, 1ms, 2ms and 7ms. (Default: 1ms) This function changes the response time of the high-speed input module to any of.1ms,.2ms,.4ms,.6ms and 1ms. (Default:.2ms) This function changes the response time of the interrupt module to any of.1ms,.2ms,.4ms,.6ms and 1ms. (Default:.2ms) This function sets whether the output to the output module, hybrid I/O module or intelligent function module will be cleared or held when the CPU module results in a stop error. This function sets whether the operation of the CPU module will be stopped or continued when the hardware error of the intelligent function module occurs. This function makes various settings of an intelligent function module. (Refer to the corresponding intelligent function module for settings.) Section Section Section Section 7.8 Section 7.9 Section 7.1 Write during RUN This function writes program when the Basic model QCPU is in the RUN status. Section 7.11 Multiple-user debugging function This function performs debugging from multiple GX Developers simultaneously. Section 7.12 Watchdog timer This function monitors operational delays caused by Basic model QCPU's hardware and program errors. Section 7.13 Self-Diagnosis function This function enables the Basic model QCPU to check for failures. Section 7.14 Failure history This function stores a failure history of diagnosis results in the memory. Section 7.15 System protect Password registration Remote password This function prevents the program from being altered by the GX Developer communication module. This function provides read/write protection for files stored in the Basic model QCPU against access from the GX Developer. This function prevents illegal external access in the serial communication module and Ethernet module. Section 7.16 Section Section System display This function connects to the GX Developer and monitors system configuration. Section 7.17 LED display Serial communication function This function enables the front-mounted LEDs to indicate the operating conditions of the Basic model QCPU. This function makes communication in the MC protocol with the RS-232 interface of the QCPU/ Q1CPU connected with a personal computer, display device or like by an RS-232 cable. Section 7.18 Section

106 7 FUNCTION 7.2 Constant Scan (1) What is Constant Scan? The scan time differs because the processing time differs depending on whether the instruction, which is used in the sequence program, is executed or not. Constant scan is a function to execute the sequence program repeatedly while maintaining the scan time at a constant time. The I/O refresh is executed before the sequence program is executed. So the I/O refresh stays constant even when the execution time of the sequence program varies. Scan time when constant scan is not used Sequence program END processing END END END END 5ms 6ms 5ms Scan time when constant scan setting is set to 7 ms Sequence program END processing END END END END Wait time 5ms 2ms 6ms 1ms 5ms 2ms 7ms 7ms 7ms Fig. 7.1 Constant scan operation

107 7 FUNCTION (2) Setting the constant scan time (a) The constant scan time setting is performed with the parameter mode PLC RAS. The constant scan setting range is 1 ms to 2 ms. A setting can be made in modules of 1 ms. When executing constant scan, set the constant scan time. When not executing a constant scan, leave the constant scan time blank. [Example] When the constant scan is set to 1 ms. (b) Set the set time of the constant scan larger than the maximum scan time of the sequence program. Also, set the constant scan set time less than the WDT set time. (WDT Set Time) > (Constant Scan Set Time) > (Sequence Program maximum Scan Time) If the sequence program scan time is larger than the constant scan set value, the Basic model QCPU detects PRG.TIME OVER (an error code: 51), the sequence program is executed with the scan time by ignoring the constant scan. Constant scan setting Constant scan Sequence program END 3.5ms 4ms.5ms 5.3ms END ms 3.5ms 3.7ms.2ms END END 3.4ms 4ms.6ms Scan where the constant scan is not normal Fig. 7.2 Operation when the Scan Time is More than the Constant Scan If the value is larger than the WDT set time, the Basic model QCPU detects a WDT error and stops the program execution

108 7 FUNCTION (c) (d) Sequence program processing is suspended during the waiting time from END processing execution in a sequence program until the start of the next scan. However, if an interrupt factor occurs after END processing execution, the corresponding interrupt program is run. Constant scan accuracy The following explains the accuracy when the constant scan time has been set. 1) Refer to Chapter 11 for errors produced when the constant scan time has been set and the interrupt program is not executed. 2) The interrupt program is also executed during the constant scan waiting time. Interruption is disabled during interrupt program execution. Therefore, if the constant scan time is reached during interrupt program execution, the constant scan cannot be finished unless the interrupt program ends. When the interrupt program is used, the constant scan time may delay by the interrupt program execution time. REMARK Refer to QCPU (Q mode)/qnacpu Programming Manual (Common Instructions) for the command processing time

109 7 FUNCTION 7.3 Latch Functions (1) What is Latch Functions? (a) The values of each Basic model QCPU device are set back to the default (bit device: OFF and word device: ) when; The PLC power is turned on. The reset operation is performed. There is a momentary power failure for more than the permissible amount of time. Latch is a function to maintain the device details when the above conditions occur. The availability of latches does not affect the operation performed by a program. (b) (c) Latch can be used to maintain the production count, defective count, address and other data to continue control if the PLC is powered OFF, reset operation is performed, or an instantaneous power failure occurs for longer than the permissible time during management of the above data for continuous control. The following devices can use the latch function: (The default latch range is only the latch relay.) 1) Latch relay(l) 2) Link relay(b) 3) Annunciator(F) 4) Edge relay(v) 5) Timer(T) 6) Retentive timer(st) 7) Counter(C) 8) Data register(d) 9) Link register(w) (2) Latch Range Setting The latch range setting is performed with the PLC parameter mode device setting. Latch range setting can be made in two ranges: latch clear (remote latch clear operation) valid range and invalid range

110 7 FUNCTION (3) Clearing the Latch Range Device Data The following table indicates the device status when latch clear is performed. Latch Setting Made or Not Device without latch range specified Latch (1) setting (device set to "The clear is possible with latch clear.") Latch (2) setting (device set to "The clear is impossible with latch clear.") Cleared or Maintained by Latch Clear Cleared Cleared Maintained POINT File registers (R) cannot be cleared with latch clear. (See Section 1.7 for clearing file registers.) (4) Precautions The device details of the latch range are maintained with the battery (Q6BAT) attached to the Basic model QCPU. (a) (b) The battery is needed to latch devices if sequence program are stored onto the standard ROM to perform ROM operation. Note that if the battery connector is unplugged from the Basic model QCPU connector during PLC power-off, the device contents in the latch range are not maintained and will be indefinite values

111 7 FUNCTION 7.4 Setting the Output (Y) Status when Changing from STOP Status to RUN Status (1) Output (Y) Status when changing from STOP Status to RUN Status When changing from RUN status to STOP status, the RUN status output (Y) is stored in the sequence and all the outputs (Y) are turned OFF. The state after transition from STOP to RUN can be selected from the following two options with the Basic model QCPU. The output state prior to STOP is output. The output is cleared. (Default: After transition from STOP to RUN, the output (Y) state prior to STOP is output then the program is executed.) (a) Previous State After the output (Y) status before the STOP status is output, the sequence program calculations are performed. (b) Recalculate (Output is 1 Scan later) Clears all output (Y) and outputs the output (Y) after executing the sequence program calculations. STOP status to RUN status Replay output? NO (Output after calculation execution) YES (Replay output) Output the output (Y) status right before changing to STOP status. Clear the output (Y) status. Execute the sequence program calculations Fig. 7.3 Processing when Change from STOP Status to RUN Status

112 7 FUNCTION (2) Setting the Output (Y) Status when Changing from STOP Status to RUN Status The output (Y) status before the STOP status when switching from STOP status to Run status can be set in the PLC System sheet of the PLC Parameter dialog box. Output mode setting at stop to RUN (3) Precaution If an output (Y) is forcefully turned ON with the Basic model QCPU in the STOP status, it will not remain in the ON status even if the STOP status is switched to the RUN status. The output status is effected as set in the PLC System setting of the output mode at STOP to RUN

113 7 FUNCTION 7.5 Clock Function (1) What is Clock Function? (a) (b) The Basic model QCPU has a clock function in the CPU module. Because the time data from the clock function can be read by the sequence program, the time data can be used for time maintenance. Also, the time data is used for time maintenance for the Basic model QCPU system functions such as those for failure history. The clock operations for the clock function are maintained even when the PLC power is off or when there is a momentary power failure for more than the permitted time, using the battery (Q6BAT). Clock Data The time data is the year, month, day, hour, minute, second, and day of the week data used for the Basic model QCPU clock element. There are the following: Data Name Contents Year Four digits in AD (Countable from 198 to 279) Month 1 to 12 Day Hour 1 to 31(Automatic leap year calculation) to 23 (24 hours) Minute to 59 Second to 59 Day of the week Sunday 1 Monday 2 Tuesday 3 Wednesday 4 Thursday 5 Friday 6 Saturday (2) Writing to and Reading from the Time Data Clock Element (a) The following two methods can be used to write to the time data clock element. 1) Method to write from GX Developer The time data is written in the clock element by displaying "Online" "Set time" window

114 7 FUNCTION 2) Method to Write from the Program The time data is written in the clock element by using the clock instruction (DATEWR). A program example to write the time data using the time data write instruction (DATEWR). Write request X MOVP K21 D Year 21 MOVP K8 D1 Month 8 MOVP K1 D2 Day 1 MOVP K11 D3 Hour 11 MOVP K35 D4 Minute 35 MOVP K24 D5 Second 24 MOVP K4 D6 Day Thursday: 4 DATEWR D Refer to "QCPU (Q mode)/qnacpu Programming Manual (Common Instructions)" for details of the DATEWR instruction. (b) Reading Time Data When reading the time data to the data register, use the time data read instruction (DATERD) from the program. The figure below shows an example of a program used to read the clock data with the DATERD instruction and then store it in D1 to D16. Read request X1 DATERD D1 The time data is read in D1 to D16. Refer to the "QCPU (Q mode)/qnacpu Programming Manual (Common instructions) for the details of the DATERD instruction. REMARK 1) Writing to and Reading from Time Data can be executed by special relays (SM21 to SM213) and special registers (SD21 to SD213). See Appendix 1 for details on special relay. See Appendix 2 for details on special registers. 2) : The figure below shows the clock data stored in D1 to D16. D1 D11 D12 D13 D14 D15 D digits in AD Month Date Hour Minute Second Day of the week Refer to Section 7.5.1(1)

115 7 FUNCTION (3) Precautions (a) The clock data is not set before shipment. The clock data is used by the Basic model QCPU system and intelligent function module for failure history and other functions. Be sure to set the accurate time when operating the Basic model QCPU for the first time. (b) (c) Even if a part of the time data is being corrected, all data must be written to the clock again. The data written in the clock element is checked in the range described in (1) (b) of Section 7.5. For this reason, if improbable clock data in the range described in (1) (b) of Section 7.5 is written in the clock element, correct clock function is unavailable. Example Writing to clock element CPU module operation state February 3 Executed No error detected 32 of month 13 Not executed Upon execution of DATEW command: OPERATION ERROR (Error code 41) Upon activation of SM21: SM211 turns ON (4) Precision The precision of the clock function differs with the ambient temperature, as shown below: Ambient Temperature ( C) Accuracy (Day difference, S) -3.2 to (TYP.+1.98) to (TYP.+2.22) to (TYP.-2.64) (5) Comparison of Clock Data To compare Basic model QCPU's clock data with a sequence program, use the DATERD instruction to read the clock data. The year data is read out in 4 digits. It can be compared as it is by using a compare instruction

116 7 FUNCTION 7.6 Remote Operation The Basic model QCPU provides the RUN/STOP/RESET switches for switching between the STOP status and the RUN status. The RUN/STOP/RESET switch also provides the Reset and Latch Clear functions. The Basic model QCPU performs self control of the operation status from an external (GX Developer function, intelligent function module, and remote contact) source. The following four options are available for remote operations: Remote RUN/STOP Remote PAUSE Remote RESET Remote LATCH CLEAR REMARK The serial communication module is used as the example to describe the intelligent function module Remote RUN/STOP (1) What is Remote RUN/STOP? (a) The remote RUN/STOP performs RUN/STOP of the Basic model QCPU from an external source with the Basic model QCPU RUN/STOP/RESET switch at RUN. (b) (c) Using remote RUN/STOP for the following remote operations are useful: 1) When the Basic model QCPU is at a position out of reach 2) When performing RUN/STOP of the control board Basic model QCPU from an external source Calculations during Remote RUN/STOP The program calculation that performs remote RUN/STOP is as follows: 1) Remote STOP Executes the program to the END instruction and enters the STOP state. 2) Remote RUN When remote RUN is performed while in the STOP state using remote STOP, the state changes to RUN and executes the program from step

117 7 FUNCTION (2) Remote RUN/STOP Method There are two ways to perform remote RUN/STOP: (a) Remote RUN contact method The remote RUN contact is set with the PLC parameter mode PLC system setting. The device range that can be set is input X to 7FF. By turning the set remote RUN contact ON/OFF, the remote RUN/STOP can be performed. 1) When the remote RUN contact is OFF, the Basic model QCPU enters the RUN state. 2) When the remote RUN contact is ON, the Basic model QCPU enters the STOP state. Step END Step END ON Remote RUN contact QCPU: RUN/STOP state OFF RUN STOP STOP state Fig. 7.4 Time Chart for RUN/STOP with Remote RUN Contact (b) Method using the GX Developer function, serial communication module, etc. Basic model QCPU can be performed by the remote RUN/STOP operation from the GX Developer function, serial communication module, etc. The GX Developer operation is performed with on-line remote operations. The serial communication module and Ethernet interface module are controlled by commands complying with the MC protocol. For details of the MC protocol, refer to the following manual. Q corresponding MELSEC Communication Protocol Reference Manual Step ON END Step END GX Developer Serial communication module Remote STOP command Remote RUN command RUN/STOP state OFF OFF RUN STOP ON STOP state Fig. 7.5 Remote RUN/STOP Time Chart using GX Developer, serial communication module, etc

118 7 FUNCTION (3) Precautions (a) Take note of the following, because STOP has priority in Basic model QCPU: 1) The Basic model QCPU enters the STOP state when remote STOP is performed from remote RUN contact, GX Developer function, or serial communication module. 2) When Basic model QCPU is set to the STOP state with remote STOP, all external factors which performed a remote STOP (remote RUN contact, serial communication module, etc.) must be set to RUN. REMARK The RUN/STOP state is described below: RUN State...State which repeatedly executes the calculations from step to the END instruction in the sequence program. STOP State...State where the sequence program calculations are stopped and the output (Y) is all OFF

119 7 FUNCTION Remote PAUSE (1) What is Remote PAUSE? (a) Remote PAUSE performs the Basic model QCPU PAUSE function from an external source, with the CPU RUN/STOP/RESET switch at RUN position. The PAUSE function stops the Basic model QCPU calculations while maintaining the ON/OFF state of all output (Y). (b) This can be used to maintain the output (Y) on even if the QCPU is changed to the STOP state, in such areas as process control. POINT The output (Y) turns OFF at stop error occurrence. To retain the output at stop error occurrence, make the output retention setting in the I/O assignment PLC parameters. (2) Remote PAUSE Method There are two ways to use remote PAUSE: (a) Remote PAUSE Contact Method The remote PUASE contact is set in the GX Developer function parameter mode PLC system setting. Setting of only the remote PAUSE contact cannot be made. When setting the remote PAUSE contact, also set the remote RUN contact. The device range that can be set is input X to 7FF. 1) The PAUSE state contact (SM24) is turned on when the END processing is executed for the scan with both remote PAUSE contact and PAUSE permission flag (SM26) on. 2) When the remote PAUSE contact is off or SM26 is turned off, the PAUSE state is canceled, and the sequence program calculation is performed again from step. END END ON END END Remote PAUSE contact OFF ON SM26 OFF ON SM24 RUN/PAUSE state OFF RUN ON when PAUSE condition met PAUSE PAUSE state Fig. 7.6 PAUSE Time Chart with Remote PAUSE Contact

120 7 FUNCTION (b) GX Developer function, Serial Communication Module Method The remote PAUSE operation can be performed from the GX Developer function or serial communication module. The GX Developer function operation is performed from on-line remote operation. Use the MC protocol commands to exercise control with the serial communication module or Ethernet interface module. Refer to the following manual for details of the MC protocol. Q-Compatible MELSEC Communication Protocol Reference Manual 1) When the END processing is executed for the scan where the remote PAUSE command was accepted, the PAUSE state contact (SM24) is turned on. When the scan after the PAUSE state contact is turned on is executed to the END process, it enters the PAUSE state and stops the calculations. 2) When the remote RUN command is received, the sequence program calculations are performed again from step. Remote PAUSE command END END ON OFF END ON Remote RUN command OFF ON SM24 RUN/PAUSE state OFF RUN ON when PAUSE condition met PAUSE PAUSE state Fig. 7.7 PAUSE Time Chart with GX Developer function (3) Precaution To set the output (Y) ON/OFF status when change to the PAUSE state, perform an interlock with the PAUSE state contact (SM24). M2 Y7 Y7 ON/OFF is determined with the ON/OFF of the M2 in the PAUSE state. X SM24 Y71 Turns off at PAUSE state. M Y72 Turns on at PAUSE state. SM

121 7 FUNCTION Remote RESET (1) What is Remote RESET? (a) The remote RESET resets the Basic model QCPU from an external source when the Basic model QCPU is at STOP state. Even if the Basic model QCPU RUN/STOP key switch is at RUN, the reset can be performed when the Basic model QCPU is stopped and an error that can be detected by the self-diagnosis function occurs. (b) Remote RESET can reset the Basic model QCPU remotely when an error occurs for which the Basic model QCPU cannot be operated directly. Remote RESET can be executed only at the STOP state. When the Basic model QCPU is at RUN state, use Remote STOP to arrange the STOP state. (2) Remote RESET Method The remote RESET can only be performed from the GX Developer function or serial communication module operation. To perform the remote RESET, follow the following steps: (a) In the PLC System sheet of the PLC Parameter dialog box, turn on the "Allow" check box in the "Remote reset" section, and then write parameters onto the Basic model QCPU. Allow the remote reset (b) (c) When the Basic model QCPU is at RUN state, use remote STOP to arrange the STOP state. Reset Basic model QCPU with the remote RESET operation. 1) For the GX Developer function, this is performed in on-line remote operation. 2) The serial communication module and Ethernet interface module are controlled by commands complying with the MC protocol. For details of the MC protocol, refer to the following manual. Q corresponding MELSEC Communication Protocol Reference Manual

122 7 FUNCTION (3) Precautions (a) To perform the remote RESET, turn on the "Allow" check box of the "Remote reset" section in the PLC System sheet of the PLC Parameter dialog box, and then write parameters onto the Basic model QCPU. If the "Allow" check box is not checked, a remote RESET operation is not performed. (b) (c) (d) Remote RESET cannot be performed when the Basic model QCPU is at the RUN state. After the reset operation is complete, the Basic model QCPU will enter operation state set at the RUN/STOP/RESET switch. 1) With the RUN/STOP/RESET switch in the "STOP" position, the Basic model QCPU enters into the "STOP" status. 2) With the RUN/STOP/RESET switch in the "RUN" position, the Basic model QCPU enters into the "RUN" status. Take care that Remote RESET does not reset Basic model QCPU if there is an error in the Basic model QCPU due to noise. If Remote RESET does not reset, use the RUN/STOP/RESET switch to reset or turn the PLC off then on again. POINT (1) If Remote RESET is executed when the Basic model QCPU is stopped due to an error, the Basic model QCPU enters the operation state set at the RUN/STOP/RESET switch after it is reset. (2) Even if the "Allow" check box of the "Remote reset" section in the PLC System sheet of the PLC Parameter dialog box, the remote process of the GX Developer is completed. However, the reset process does not proceed in the Basic model QCPU and therefore it is not reset. If the state of the Basic model QCPU does not change though a reset process is performed at the GX Developer, check if the "Allow" check box of the "Remote reset" section in the PLC System sheet of the PLC Parameter dialog box is turned on

123 7 FUNCTION Remote Latch Clear (1) What is Remote Latch Clear? (a) The remote latch clear resets the device data latched to the Basic model QCPU using the GX Developer function or other function, when it is at the STOP state. (2) Remote Latch Clear Method The remote latch clear can only be performed from GX Developer function or serial communication module. To perform the remote latch clear, follow the following steps: (a) Use the RUN/STOP/RESET switch or the remote STOP to place the Basic model QCPU to the STOP status. (b) Use the Latch Clear to bring the Basic model QCPU to the Latch Clear status. 1) The GX Developer function operations are performed with on-line remote operation. 2) The serial communication module and Ethernet interface module are controlled by commands complying with the MC protocol. For details of the MC protocol, refer to the following manual. Q corresponding MELSEC Communication Protocol Reference Manual (c) To return the Basic model QCPU to the RUN status after the remote latch clear, perform a remote RUN operation. (3) Precautions (a) Either remote latch clear cannot be performed when the Basic model QCPU is at RUN status. (b) (c) There the latch clear (remote latch clear operation) valid range and invalid range as the device latch ranges set in the device setting in the parameter mode. In the remote latch clear operation, only the device range set as the "latch clear valid" range is reset. Refer to Section 4.6 for the way to reset the device set to latch clear invalid. Devices that are not latched are cleared when the remote latch clear is executed. The data in the failure history storage memory of the Basic model QCPU will also be cleared by a remote latch clear operation

124 7 FUNCTION Relationship of the remote operation and Basic model QCPU RUN/STOP switch (1) Relationship of the Remote Operation and Basic model QCPU Switch The Basic model QCPU operation status is as follows with the combination of remote operations to RUN/STOP/RESET switch. Remote operation RUN/STOP switch RUN 1 STOP PAUSE 2 RESET RUN RUN STOP PAUSE Cannot operate STOP STOP STOP STOP RESET Latch clear Cannot operate 4 Latch clear 1 When performing the operation with remote RUN contact, "RUN-PAUSE contact" must be set in the parameter mode PLC system setting. 2 When performing the operation with remote PAUSE contact, "RUN-PAUSE contact" must be set in the parameter mode PLC system setting. In addition, the remote PAUSE enable coil (SM26) must be set ON. 3 "Remote reset enable" must be set in the parameter mode PLC system setting. 4 RESET or LATCH CLEAR can be performed if the Basic model QCPU changed to the STOP state from a remote operation. 5 This includes a situation where the Basic model QCPU is stopped due to error. (2) Remote Operations from the Same GX Developers When remote operations are performed from the same GX Developer, the status of the remote operation that is executed last will be effective. (3) Remote Operations from Multiple GX Developers While a remote operation is being performed by one GX Developer, another remote operation cannot be performed by another GX Developer. After a remote operation that is being performed by one GX Developer is cancelled, a new remote operation can be performed by another GX Developer. For example, a remote PAUSE operation is being performed by one GX Developer, the PAUSE status will remain active even if a remote STOP/remote RUN operation is attempted by another GX Developer. When a remote RUN operation is performed by the GX Developer that is performing a remote PAUSE operation, and then that remote operation is cancelled, a new remote operation can be performed by another GX Developer

125 7 FUNCTION 7.7 Selection of Module Input Response Time (I/O Response Time) Selection of input response time of the input module/composite I/O module (1) Selection of Input Response Time of the Input Module/Composite I/O Module Selection of the input response time of the input module/composite I/O module is to change the input response time of the input module/composite I/O module to 1ms, 5ms, 1ms, 2ms or 7ms on a module basis. The input module/composite I/O module imports external inputs at the specified input response time. The default setting of the input response time is 1ms. ON External input OFF ON Input module OFF Input response time (2) Setting of Input Response Time Set the input response time in the I/O assignment of the PLC parameter dialog box. Choose "Input" as the type of the slot to which the input response time is set. For the composite I/O module, choose "Composite I/O". Input module: Select Input. Composite I/O module: Select Composite I/O. Select "Detail Setting". Select "Input response time". (3) Reactions (a) Setting of shorter input response time increases sensitivity to noise. Take the operating environment into consideration when setting the input response time. (b) The setting of the input response time is made valid when: The PLC is powered ON; or CPU module is reset

126 7 FUNCTION Selection of input response time of the high-speed input module (1) Selection of input response time of the high-speed input module The input response time of the high-speed input module (QX4-S1).1ms,.2ms,.4ms,.6ms or 1ms on a module basis. The high-speed input module imports external inputs the specified input response time. The default value is set to.2ms. ON External input OFF ON High-speed input module OFF Input response time (2) Input response time setup Set the input response time in the I/O assignment PLC parameters. Choose "Hi. input" as the type of the slot to which the input response time is set. Select "Hi. Input" Click on this for detailed setting Select input response time (3) Precautions (a) (b) Setting of a higher input response time increases sensitivity to noise. Take the operating environment into consideration when setting the input response time. The setting of the input response time is made valid when: The PLC is powered ON; or CPU module is reset

127 7 FUNCTION Selection of input response time of the interrupt module (1) Selection of input response time of the interrupt module The input response time of the interrupt module (QI6) can be selected from.1ms,.2ms,.4ms,.6ms or 1ms on a module basis. The interrupt module imports external inputs the specified input response time. The default value is set to.2ms. ON External input OFF ON Interrupt module OFF Input response time (2) Input response time setup Set the input response time in the I/O assignment PLC parameters. Choose "Interrupt" as the type of the slot to which the input response time is set. Select "Interrupt" Click on this for detailed setting Select input response time (3) Precautions (a) (b) Setting of a higher input response time increases sensitivity to noise. Take the operating environment into consideration when setting the input response time. The setting of the input response time is made valid when: The PLC is powered ON; or CPU module is reset

128 7 FUNCTION 7.8 Error-time Output Mode (1) Error-time Output Mode Setting The error-time output mode setting is to set whether the output to the Q series compatible output module, hybrid I/O module or intelligent function module will be cleared or held when the CPU module results in a stop error. (2) Error-time Output Mode Setting Make the error-time output mode setting in the I/O assignment of the PLC parameter dialog box. Choose "Output", "Hybrid I/O" or "Intelligent" as the type of the slot to which the error-time output mode is set. Then select Detailed setting. Choose "Clear" or "Hold" for the slot to which the error-time output mode is set. (The default is "Clear".) Select Type. Select Detailed setting. Select "Clear" or "Hold" under Error-time output mode. (3) Precautions The error-time output mode setting is made valid when: The PLC CPU is power ON. The CPU module is reset. Failure to perform either operation after changing the error-time output mode setting will result in "PARAMETER ERROR (error code: 3)"

129 7 FUNCTION 7.9 Hardware Error-time CPU Operation Mode Setting (1) Hardware Error-time CPU Operation Mode Setting The hardware error-time CPU operation mode setting is to set whether the operation of the CPU module will be stopped or continued when a hardware error occurs in the intelligent function module. (2) Hardware Error-time CPU Operation Mode Setting Make the hardware error-time CPU operation mode setting in the I/O assignment of the PLC parameter dialog box. Choose "Intelligent" as the type of the slot to which the hardware error-time CPU operation mode is set. Then select Detailed setting. Choose the hardware error-time CPU operation mode of the slot to which the hardware error-time CPU operation mode is set. (The default is "Stop".) Select Intelligent. Select Detailed setting. Select "Stop" or "Continue" under Hardware error-time CPU operation mode. (3) Precautions The hardware error-time CPU operation mode setting is made valid when: The PLC CPU is power ON. The CPU module is reset. Failure to perform either operation after changing the hardware error-time CPU operation mode setting will result in "PARAMETER ERROR (error code: 3)"

130 7 FUNCTION 7.1 Setting the Switches of the Intelligent-Function Module (1) Setting the Switches of the Intelligent-Function Module The switches of the intelligent-function module is to set the switches of an QCPUcompatible intelligent function module using GX Developer. The settings of the switches set by GX Developer is written from Basic model QCPU to each intelligent function module at the leading-edge or reset of Basic model QCPU. GX Developer Parameter Switch setting of the intelligent function module at the I/O assignment Write Basic model QCPU Parameter Intelligent function module Power supply On/QCPU module Reset Switch setting (2) Setting the Switches of the Intelligent-Function Module In the "I/O assignment" sheet of the PLC Parameter dialog box, specify the desired switch setting. Select "Intelli." in the "type" column of a slot for which to set the switches of the intelligent function module. Select "Intelli". Select "Switch Setting". Designate the contents of the intelligent function module switch. (3) Precautions (a) Do not apply the switch setting for an intelligent function module. If the switch setting for an intelligent function module is specified an error (SP.PARA.ERROR) will occur. (b) (c) Set "Interrupt" as the type to set the switches of the intelligent function module using GX Developer. Refer to the following manual for details of the interrupt module switch setting. Building Block Type I/O Module User's Manual The switch setting is made valid when: The PLC is powered ON; or CPU module is reset

131 7 FUNCTION 7.11 Program Write during RUN of Basic Model QCPU There are the following two different types for program write during RUN of the Basic model QCPU. Write during RUN in ladder mode (refer to Section ) Write during RUN using pointer (refer to Section ) Writing Data in the Ladder Mode during the RUN Status (1) Writing data in the ladder mode during the RUN Status (a) Writing data in the circuit mode during the RUN status is used to write a program during the Basic model QCPU RUN status. (b) Changing the program can be performed without stopping the process in Basic model QCPU program using writing data in the ladder mode during the RUN status. X X2 X1 Y3 X3 X4 X5 SET M1 END GX Developer Change by GX Developer and write in Basic model QCPU at the conversion. (c) Writing to the program during RUN can be performed from a GX Developer function peripheral device connected to another station in the network. MELSECNET/H Writing data the ladder mode during the RUN status. Personal computer (GX Developer)

132 7 FUNCTION (2) Precautions Take a note of the following when writing during RUN: (a) The memory that can be written during RUN is only program memory. If the write during RUN is performed while booting a program from the standard ROM, the program to be booted will not be changed. Write the contents of the program memory to the standard ROM before powering off the PLC or resetting the Basic model QCPU. (b) (c) A maximum of 512 steps can be written at once during RUN. The program file capacity of the Basic model QCPU is the value of adding the "steps secured for write during RUN" to the created program capacity. When the program file capacity is increased from the capacity secured first by write during RUN that increases the program file capacity, the steps secured for write during RUN can be set again at the time of write during RUN. Therefore, when the user memory area has a free space, write during RUN can be performed. However, if the steps secured for write during RUN are re-set at the time of write during RUN, note that the scan time will increase by the value given in the following table. (Control will be suspended during the time indicated in the following table.) (d) CPU Module Model Steps Secured for Write during RUN Name No change Re-setting QJCPU Maximum 2.1ms Maximum 3ms QCPU Maximum 1.7ms Maximum 26ms Q1CPU Maximum 1.7ms Maximum 36ms Normal operation will not be performed if any of the following instructions is written using online write. 1) Trailing edge instructions Any of the following trailing edge instructions is executed if the execution condition of the trailing edge instruction is OFF on completion of write. LDF ANDF ORF MEF PLF 2) Leading edge instructions The leading edge instruction is not executed if the execution condition of the leading edge instruction (PLS instruction/ P instruction) is ON on completion of write. The leading edge instruction is executed when the execution condition turns from OFF to ON again. 3) SCJ instruction If the execution condition of the SCJ instruction is ON on completion of write, a jump to the specified pointer is made without waiting for one scan

133 7 FUNCTION 7.12 Multiple-User Debugging Function (1) What is Multiple-User Debugging Function? The multiple-user debugging function executes debugging simultaneously from multiple GX Developers connected to the Basic model QCPU, serial communication module, etc. (2) Function Explanation There are the following combinations of multiple-user debugging functions. Function in Execution Monitor Write during RUN Function Executed Later Monitor Write during RUN : Can be executed simultaneously. : Can be executed from only one GX Developer. (While the function is being executed by one GX Developer, it cannot be executed by other GX Developers.)

134 7 FUNCTION Multiple-user monitoring function (1) What is Multiple-User Monitoring Function? (a) The multiple-user monitoring operation can be performed by operating from multiple GX Developers connected to the Basic model QCPU or the serial communications module. (b) Multiple users can monitor at the same time. By setting a station monitor file, high-speed monitoring can be performed. (Setting of station monitor file is not necessary.) (2) Operation Procedure (a) For multi-user monitoring operation, create a user-defined system file in the following steps. 1) Choose "Online" "Format PLC Memory" to open the Format PLC Memory dialog box. 2) Select "program memory/device memory" from the Target Memory list box. 3) In the Format section, select "Create a user setting system area..." so that its radio button is checked. 4) Specify the desired K steps in the System Area text box. (b) The figure below illustrates an example in which "1k step" is specified in the System Area text box. 1) A maximum of 15 k steps can be set in 1 k step modules as a system area. Only 1 k step can correspond to one station monitor file. Therefore, a maximum of 15 station monitor files can be set. (3) Precautions (a) Monitoring can be performed even if a station monitor file is not set, but high-speed monitoring cannot be performed. The system area is in the same area as the program memory, so the area of the stored program reduced when the system area is set. (b) When the user-set system area of 3k steps is created, the simultaneous monitoring of one CPU from four locations can be speeded up

135 7 FUNCTION Multiple-user simultaneous write during RUN (1) What is Multiple-User Simultaneous Write during RUN? (a) Multiple-user simultaneous write during RUN allows multiple users to perform write during RUN simultaneously to one file or different files. (b) When multiple users perform write during RUN simultaneously to one file, preset the pointer for write during RUN and select "Relative write during RUN using pointer". (2) Operation Procedure (a) Choose "Tools" - "Options" and set "Set write during RUN" and "Write during RUN system". 1) 2) 1) Set "Perform write during RUN to PLC after conversion" under "Set write during RUN". 2) Select "Normal write during RUN" or "Relative write during RUN using pointer" under "Write during RUN system"

136 7 FUNCTION (b) Write during RUN of P and later in machining program is performed. X X2 P Y3 X1 X3 X4 P1 X5 SET M1 Display the ladder of the specified pointer and perform write during RUN of the changed ladder. The following figure shows an example where the personal computer A performs write during RUN from P and the personal computer B performs write during RUN from P1. The program enclosed by is the target of write during RUN. Serial communication module Write during RUN of P and later in machining program is performed. X X2 P Y3 X1 X3 X4 P1 X5 SET M1 END END Personal computer A (GX Developer) Personal computer B (GX Developer) (3) Precautions The precautions for write during RUN are the same as those for write during RUN in ladder mode in Section Refer to Section

137 7 FUNCTION 7.13 Watchdog Timer (WDT) (1) What is Watchdog Timer (WDT)? (a) The watchdog timer is an internal sequence timer to detect Basic model QCPU hardware and/or sequence program error. (b) (c) When the watchdog timer expires, a watchdog timer error occurs. The Basic model QCPU responds to the watchdog timer error in the following way. 1) The Basic model QCPU turns off all outputs. 2) The front-mounted RUN LED goes off, and the ERR. LED starts flashing. 3) SM1 turns ON and the error code 51 (WDT ERROR) is stored into SD. The default value of the watchdog timer is 2 ms. The setting range is 1 to 2 ms (1ms units). (2) Watchdog Timer Setting and Reset (a) The PLC RAS setting of the PLC parameter resets the watchdog timer. (b) Basic model QCPU resets the watchdog timer when the END instruction is executed. 1) When the END/FEND instruction is executed within the set value of the watchdog timer in the sequence program and the Basic model QCPU is operating correctly, the watchdog timer does not time out. 2) When there is a Basic model QCPU hardware failure or the sequence program scan time is too long, and the END/FEND instruction could not be executed within the set watchdog timer value, the watchdog timer times out. (3) Precautions (a) An error of to 1 ms occurs in the measurement time of the watchdog timer. Set the watchdog timer for a desired value by taking such an error into account. (b) The watchdog timer is reset with the WDT instruction in the sequence program. If the watchdog timer expires while the FOR and NEXT instructions are repetitiously executed, reset the watchdog time with the WDT instruction. FOR K1 Program for repetition processing M WDT WDT reset Repetition (1 times) NEXT

138 7 FUNCTION (c) The scan time value is not reset even if the watchdog timer is reset in the sequence program. The scan time value is measured to the END instruction. Internal processing time Sequence program Internal processing time END END WDT reset (QCPU internal processing) Next scan time Scan time WDT reset (QCPU internal processing) Watchdog timer measured time Fig. 7.9 Watchdog Timer Reset REMARK Scan time is the time elapsed from the time the Basic model QCPU starts processing a sequence program at Step until the it restarts processing another sequence program with the same filename at Step. The scan time is not the same at every scan, and differs, depending on Whether the commands used are executed or not executed. Whether to execute or not an interrupt program. Use the constant scan function to execute a program at the same scan time every scan. Refer to section 7.2 for details of the constant scan function

139 7 FUNCTION 7.14 Self-Diagnosis Function (1) What is Self-Diagnosis Function? (a) The self-diagnosis is a function performed by Basic model QCPU itself to diagnose whether there is an error in the Basic model QCPU. (b) The self-diagnosis function's objective is to prevent Basic model QCPU erroneous operation and as preventive maintenance. The self-diagnosis processing detects and displays the error when an error occurs when the Basic model QCPU power is turned on or during Basic model QCPU RUN mode. It also stops Basic model QCPU calculations. (2) Processing for Error Detection (a) When Basic model QCPU detects an error, it turns on ERR. LEDs. When an error is detected, special relays (SM, SM1) are turned ON and an error code of the error is stored in the special register SD. When multiple errors are detected, error codes of the latest errors are stored in the special register SD. For error detection, use special relays and special registers in program so that these devices can interlock with sequencers and mechanical systems. (b) Basic model QCPU stores 16 latest error codes. (Refer to Section 7.13.) The failure history can be checked in the GX Developer function PLC diagnostics mode. The failure history can be stored even when the power is shut off using the battery backup. (3) Basic model QCPU operation at the time of error detection (a) When an error is detected from the self-diagnosis, there are two types of modes that the Basic model QCPU operation can change to. 1) Basic model QCPU calculation stop mode Stops the calculation at the point when the error is detected, and turns off all external outputs of the module for which "Clear" (default) has been set to "Error-time output mode" in the I/O assignment of the PLC parameter dialog box. (The outputs (Y) on the device memory are retained.) However, the external outputs of the module for which "Retain" has been set to "Error-time output mode" are retained. (The outputs (Y) on the device memory are retained.) 2) Basic model QCPU calculation continue mode When an error is detected, the program (Instruction) area where the error occurred is skipped and the rest of the program is executed. (b) The following errors can set the calculation "continue/stop" in the parameter mode PLC RAS. (All parameter defaults are set at "Stop".) 1) Operation error 2) Fuse blown 3) I/O unit comparison 4) Intelligent function module program execution error For example, when the I/O module verification error is set to "continues", the calculations are continued in the I/O address before the error occurred

140 7 FUNCTION (c) For the following error, selection of calculation "Continue/Stop" can be made in the detailed setting of I/O assignment setting. Intelligent function module error (4) Error check selection The error checking can be set to "yes/no" in the following error checking in the parameter mode PLC RAS setting. (All parameter defaults are set at "Yes".) (a) Battery check (b) Fuse blown check (c) I/O unit comparison Self-Diagnosis List Diagnosis description Error message Diagnostic timing CPU error MAIN CPU DOWN Always END instruction not executed END NOT EXECUTE When the END instruction is executed SFC program execution error SFCP. END ERROR When the SFC program is executed RAM check RAM ERROR When the power is turned on/when reset Hardware failure Handling error Calculation circuit check OPE.CIRCUIT ERR. When the power is turned on/when reset Fuse short (default... stop) 1 FUSE BRAKE OFF When the END instruction is executed 2 (Default... Yes) I/O interrupt error I/O INT ERROR When an interrupt occurs Intelligent function module error 1 SP.UNIT DOWN When the power is turned on/when reset When the FROM/TO instruction is executed Control bus error CONTROL-BUS ERROR. When the intelligent function module dedicated instruction is executed When the END instruction is executed Momentary stop occurred AC/DC DOWN Always Battery low BATTERY ERROR Always (Default...Yes) I/ module verification (Default... When the END instruction is executed 1 UNIT VERIFY ERROR 2 Stop) (Default... Yes) Base allocation error BASE LAY ERROR When the power is turned on/when reset Intelligent program execution error 1 (Default... Stop) SP. UNIT ERROR When an instruction is executed Intelligent function module When the power is turned on/when rest SP.UNIT LAY ERR. allocation error When switched from STOP to RUN No parameter MISSING PARA. When the power is turned on/when rest Boot error BOOT ERROR When the power is turned on/when rest File setting error FILE SET ERROR When the power is turned on/when reset Instruction execution not possible CAN T EXE.PRG. When the power is turned on/when reset 3 1:Can be changed to "Continue" in the GX Developer function parameter setting. 2:Can be set to "No" in the GX Developer function parameter setting

141 7 FUNCTION Self-Diagnosis List (Continued from the preceding page) Diagnosis description Error message Diagnostic timing Parameter error Password error Program error PLC error Multiple CPU Parameter setting check PARAMETER ERROR When the power is turned on/when reset When switched from STOP to RUN Link parameter error LINK PARA.ERROR When the power is turned on/when reset When switched from STOP to RUN SFC parameter error SFC PARA.ERROR When switched from STOP to RUN Intelligent function module parameter error SP.PARA.ERROR When the power is turned on/when reset REMOTE PASS.ERROR When the power is turned on/when reset When switched from STOP to RUN When the power is turned on/when reset Instruction code check INSTRUCT CODE ERR. When switched from STOP to RUN When an instruction is executed No END instruction MISSING END INS. When the power is turned on/when reset When switched from STOP to RUN Pointer setting error CAN T SET(P) When the power is turned on/when reset When switched from STOP to RUN Pointer setting error CAN T SET(I) When the power is turned on/when reset When switched from STOP to RUN Operation check error (Default... 1 Stop) OPERATION ERROR When an instruction is executed FOR to NEXT instruction structure error FOR NEXT ERROR When an instruction is executed CALL to RET instruction structure error CAN T EXECUTE(P) When an instruction is executed Interrupt program error CAN T EXECUTE(I) When an instruction is executed Instruction execution disable INST.FORMAT ERR. When an instruction is executed SFC block structure error CAN T SET(BL) When switched from STOP to RUN SFC step structure error CAN T SET(S) When switched from STOP to RUN SFC syntax error SFCP.FORMAT ERR. When switched from STOP to RUN SFC program execution error SFCP.EXE.ERROR When switched from STOP to RUN SFC block execution error BLOCK EXE.ERROR When an instruction is executed SFC step execution error STEP EXE. ERROR When an instruction is executed Watchdog error supervision WDT ERROR Always Program time exceeded PRG.TIME OVER Always Other CPU major fault MULTI CPU DOWN Always When the power is turned on/when reset Multiple CPU execution error MULTI EXE.ERROR When the power is turned on/when reset Multiple CPU matching error CPU LAY ERROR When the power is turned on/when reset Other CPU minor fault MULTI CPU ERR. Always 1:Can be changed to "continues" in the GX Developer function parameter setting

142 7 FUNCTION LED display when error occurs When an error occurs, the ERR. LED located on the front of Basic model QCPU turns on. Refer to Section 7.18 for details of the ERR. LED operation Cancel error Basic model QCPU error cancel operation can be performed only for error that can continue the Basic model QCPU operation. (1) Cancellation of error (a) Procedures for cancellation of error The error cancel is performed in the following manner: 1) Resolve the cause of error. 2) Store the error code of the error to be canceled in the special register SD5. 3) Switch special relay SM5 from OFF to ON. 4) The error is canceled. (b) (c) Status after cancellation of error When the CPU is recovered from canceling the error, the special relay, special register, and LED affected by the error are set to the state before the error occurred. When the same error occurs after canceling the error, it is logged again in the failure history. Cancellation of annunciator For the cancellation of the annunciator detected multiple times, only the first detected "F" is canceled. POINT (1) When error cancellation is performed by storing the code of the error to cancel is stored in SD5, the lower 1 digits of the code number is ignored. (Example) When the error codes 21 and 211 occur, canceling the error code 21 will also cancel the error code 211. When the error codes 21 and 2111 occur, canceling the error code 21 will not cancel the error code (2) If the cause of the error is not in the CPU module, the error cause cannot be resolved if error cancellation is performed using the special relay (SM5) and special register (SD5). (Example) Since "SP. UNIT DOWN" is an error that occurred on the Q bus, the error cause cannot be resolved if error cancellation is performed using the special relay (SM5) and special register (SD5). Refer to the error code list in the Basic model QCPU (Q mode) User's Manual (Hardware Design, Maintenance and Inspection), and resolve the error cause

143 7 FUNCTION 7.15 Failure History The Basic model QCPU can store the failure history (results detected from the selfdiagnosis function and the time) in the memory. POINT The detection time uses the Basic model QCPU internal clock, so make sure to set the correct time when first using Basic model QCPU. (1) Storage Area The latest 16 failures are stored in the latched Basic model QCPU failure history storage memory. (2) Stored data If the same error occurs more than once during PLC power-on, it is stored into the failure history storage memory only once. (3) Failure History Clearing Method The failure history storage memory are cleared using the failure history clear in the GX Developer PLC diagnosis mode. Data files stored in Basic model QCPU failure history storage memory can be cleared with a failure history clear

144 7 FUNCTION 7.16 System Protect Basic model QCPU has a few protection functions (system protect) for the program changes to processing of general data obtained from a third party other than the designer (access processing from GX Developer function or serial communication module). There are the following methods for system protects. Item to protect Protect valid file Protection description Method The attributes for a file is Program Change the attributes for changed to the following: File unit Device comments the file in the Password 1) Read/Write display prohibit Device initial value Registration. 2) Write prohibit Valid Timing Always Remarks The control instruction, read/write display, and write are mentioned above are as follows: Item Read/Write display Write Program read/write operations. Description Operation that writes the program and tests Password registration Password is used to prohibit the data read and write of the program and comments in Basic model QCPU from a GX Developer peripheral device. Password Registration is applicable to the program file, device comment file and device initial value file in the program memory. There are two descriptions of items to be registered. The file name is not displayed and read/write cannot be performed as well. Write cannot be performed to the file. (Read only) If the password is registered, file operations from GX Developer cannot be performed unless the same password is input

145 7 FUNCTION (1) Password Registration To perform the password registration, select GX Developer Online setup/keyword set up for writing to PLC Register password. Password (a) (b) (c) (d) (e) (f) Each item is described below: (a) Target memory...set the memory storing the file whose password is to be registered or changed. (b) (c) Data type...specifies the type of a file stored in the target memory. Data name...displays a filename of a file stored in the target memory. (d) Registration...Displays an asterisks " " that indicates a password-protected file. (e) (f) Password...Defines or changes a password. Setting a password allows you to set the registration condition. Registration Condition 1) Write Protect...Write operation is restricted by the password. (Reading is possible.) 2) Read/Write protect...read/write operation is restricted by the password. 3) Clear...Password is cleared. (Sets password currently registered in the Password.) POINT (1) Password-protected files are limited to the program file, device comment file and device initial value file. Other files cannot be password-protected. (2) The password registered to a file can not read out from the file. If the password can not be remembered, file operation other than following can not be performed. Program memory: PLC memory format Standard ROM: storage of program memory data onto ROM Take notes of the password registered and keep it on hand

146 7 FUNCTION Remote password The remote password function is used to prevent illegal access to the Basic model QCPU from a remote user. By setting a remote password to the Basic model QCPU, the remote password function can be used. With the remote password preset, the serial communication module and Ethernet module of the modem function check the remote password when access is made from a remote user to the Basic model QCPU. (1) Setting, change and cancellation of remote password (a) Setting of remote password Set the remote password on the remote password setting screen of GX Developer, connect GX Developer to the Basic model QCPU where the remote password will be set, and write the remote password. The Basic model QCPU transfers the remote password to the specified one of the following modules when the PLC is powered on or the Basic model QCPU is reset. Serial communication module Ethernet module Modem interface module (b) Change and cancellation of remote password By connecting GX Developer to the Basic model QCPU, the remote password of the connected Basic model QCPU can be changed or canceled. Using GX Developer, set a new password or delete the remote password, and write it to the Basic model QCPU. This enables the remote password of the Basic model QCPU to be changed or canceled. Change or cancellation of the remote password cannot be performed from a remote location. The following figure shows the outline of setting, changing and canceling the remote password for the Ethernet module, for example. GX Developer Ethernet Transfers remote password to QJ71E71 at power-on or reset. s P Q Q u o C J p w P 71 p e l U E r y 71 GX Developer Checks remote password. Set Change Cancel remote password and write to QCPU

147 7 FUNCTION (2) Remote password lock/unlock processing At the access source, unlock the remote password of the serial communication module via modem or that of the Ethernet module via Ethernet. On a remote password match, access to the Basic model QCPU is allowed. The following figure shows the outline of the remote password unlock and lock processing performed by the Ethernet module, for example. The following figure shows the outline of setting, changing and canceling the remote password for the Ethernet module, for example. GX Developer Unlocks (cancels) remote password and makes access to QCPU. When closing line, performs lock processing of remote password. Ethernet s P Q Q u o C J p w P 71 p e l U E r y 71 Transfers remote password to QJ71E71 at power-on or reset. Checks remote password. GX Developer

148 7 FUNCTION (3) Remote password setting procedure Choose "GX Developer" [Remote password] "Remote password setup" screen "Remote password detail setup" screen. (a) Setting screen Remote password setting Detailed setting is necessary for QJ71E71. (b) Setting items Item Setting Setting Range/Choices 4 bytes Password setting Remote password input Alphanumeric characters, special symbols Model name Select the model name. QJ71E71/QJ71C24/QJ71CMO Password valid Set the head address of the module setting Head I/O H to FEH module. Detailed setting User connection No. Set the user connection No. Connection No. 1 to connection No. 16 Automatic open UDP port FTP communication port (TCP/IP) GX Developer communication port System Check the remote password (TCP/IP) connection valid port. GX Developer communication port (UDP/IP) HTTP port POINT Refer to the following manuals for details of the remote password function. When the serial communication module is used Q Corresponding Serial Communication Module User's Manual (Application) When the Ethernet module is used Q Corresponding Ethernet Interface Module User's Manual (Fundamentals) When the QJ71CM is used QJ71CM Modem Interface Module User's Manual (Details)

149 7 FUNCTION 7.17 GX Developer system monitor It is possible to confirm the following information for Basic model QCPUs connected to personal computers with the GX Developer system monitor (see illustration below.) Installed status Operation status Module s detailed information Product information (a) (c) (b) (d) (e) (f) (g) (a) (b) (c) (d) Installed status You can confirm the types and points of the modules loaded on the selected base unit. "Not installed" will be displayed for slots in which modules have not been mounted. When slots have been set as "Empty" with the PLC parameter's I/O allocation setting, the module's model will not be displayed when if a module has been mounted. Operation status Enables the I/O number, the module type and the number of modules mounted for each of the slots on the selected base unit to be confirmed. If the operation status shows empty points and an allocation error is displayed, it means that the PC parameter's I/O allocation and the actual status are different. In this event, align the PLC parameter's I/O allocation with the actual status by allocating an I/O. Base Enables the status of the modules mounted onto the base unit in use to be confirmed. The module column displays an error or warning status if even one module is faulty. Diagnostics This function is used to confirm the status of Basic model QCPU and errors

150 7 FUNCTION (e) (f) (g) Module s detailed information This function is used to confirm the detailed information for selected modules. Refer to the instruction manual for the relevant intelligent function module for details on the detailed information for intelligent function modules. Base information Enables the "Overall Information" and "Base Information" to be confirmed. 1) Overall information Enables the number of base units in use and the number of modules mounted on the base units to be confirmed. 2) Base information Enables the base name, the number of slots, the base type and the number of modules mounted on the base unit for the selected base unit (main base unit, extension base units 1 to 7) to be confirmed. List of product information Enables the individual information on the mounted CPU module, input/output modules and intelligent function modules to be confirmed (Type, Series, Model name, Points, I/O No., Control CPU, Serial NO., Function version). Serial No. Function version

151 7 FUNCTION 7.18 LED Display The LEDs that indicate the operation statuses of the Basic model QCPU are provided on the front panel of the Basic model QCPU. The indications of the LEDs are described below. (1) The details of the LED display are shown below: LED name RUN ERR. POWER Display Description Indicates the operation status of the CPU module. On : When operating with the RUN/STOP/RESET switch at "RUN". Off : When stopped with the RUN/STOP/RESET switch at "STOP". Or when an error that stops operation is detected. Flicker : When writing parameters ad program during STOP, and when setting the RUN/STOP/RESET switch from [STOP] [RUN]. Perform the following operations in order to illuminate the RUN LED after program writing. Set the RUN/STOP/RESET switch to [RUN] [STOP] [RUN]. Reset the system with the RUN/STOP/RESET switch. Switch on the power to the PLC again. Perform the following operations in order to illuminate the RUN LED after parameter writing. Reset the system with the RUN/STOP/RESET switch. Switch on the power to the PLC again. (When the RUN/STOP/RESET switch has been set to [RUN] [STOP] [RUN] after the parameters have been amended, the parameters related to intelligent function modules and other network parameters will not be reflected back.) Indicates the error detection status of the CPU module. On : When a self-diagnosis error that does not stop the operation is detected. (Set the operation error set mode to "continue" in the parameter mode PLC RAS setting.) Off : Normal Flicker : When an error that stops the operation is detected. When the CPU is reset with the RUN/STOP/RESET switch. Goes off on completion of reset. Indicates the 5VDC output status of the power supply built in the QJCPU. On : Normal output of 5VDC Off : PLC power off or 5VDC output error

152 7 FUNCTION (2) How to turn off the ERR. LED To turn off the ERR. LED that is on, remove the cause of the error and then operate the special relay SM5 and special register SD5 to cancel the error. (This does not apply to reset operation.) REMARK Refer to Section for canceling the error

153 7 FUNCTION 7.19 Serial Communication Function (Usable with the QCPU or Q1CPU) The serial communication function is designed to make communication in the MC protocol (*1) by connecting the RS-232 interface of the CPU module and personal computer, display device or the like by an RS-232 cable. The serial communication function is not used for connection of GX Developer or GX Configurator and the CPU module. Communication using the serial communication function can be made by the QCPU or Q1CPU. (The QJCPU does not have the serial communication function.) The following explains the specifications, functions and various settings needed to make communication with a personal computer, display device or the like using the serial communication function. RS-232 cable Personal computer, display device Communication in MC protocol 1 The MC protocol is the abbreviation of the MELSEC communication protocol. The MELSEC communication protocol is a name of the communication method to make access from the mating equipment to the CPU module in accordance with the communication procedure of the Q series PLC (e.g. serial communication module, Ethernet interface module). POINT The CPU that can make communication with a personal computer, display device or the like using the serial communication function is only the CPU module that is connected with the personal computer, display device or the like. Communication cannot be made with the other station of MELSECNET/H, Ethernet or CC-Link via the CPU module that is connected with the personal computer, display device or the like

154 7 FUNCTION (1) Specifications (a) Transmission specifications The following table indicates the transmission specifications of RS-232 used for the serial communication function of the CPU module. Use the serial communication function after making sure that the specifications of the personal computer, Display device or the like match those of the following table. Item Default Setting Range Communication system Full duplex communication Synchronization system Asynchronous system Transmission speed kbps Data format MC protocol format 2 (Automatic judgment) Frame 2 Start bit: 1 Data bit: 8 Parity bit: Odd Stop bit: 1 Format 4 (ASCII) Format 5 (binary) QnA-compatible 3C frame QnA-compatible 4C frame 9.6kbps, 19.2kbps, 38.4kbps, 57.6kbps, 115.2kbps Transmission control DTR/DSR control Sum check 1 No Yes, No Transmission wait time 1 No wait No wait, 1ms to 15ms (1ms increments) Write during RUN setting 1 Not enabled Enabled, Not enabled Extension distance 15m 1: Can be set in the PLC parameter setting of GX Developer. 2: The relationships between the MC protocol formats and frames are indicated in the following table. Function Format 4 Format 5 Communication in ASCII code QnA-compatible 3C frame QnA-compatible 4C frame Communication in binary code QnA-compatible 4C frame : Usable, : Unusable

155 7 FUNCTION (b) RS-232 connector specifications The following table indicates the applications of the RS-232 connector of the CPU module. Appearance Pin No. Signal Symbol Signal Name Mini-Din 6 pins (female) 1 RD (RXD) Receive data 2 SD (TXD) Send data 3 SG Signal ground 4 5 DSR (DR) Data set ready 6 DTR (ER) Data terminal ready (c) RS-232 cable The following RS-232 cable can be used for connection of the CPU module with the personal computer, display device or the like. QC3R2 (cable length: 3m) FKRK62- (KURAMO ELECTRIC) manufactured Cable with a mini-din connector on one side and without connector on the other side indicates the cable length, which can be specified up to 15ms in.1m increments (QCPU,Q1CPU side) FKRK62-*** Effective length Signal layout of QCPU,Q1CPU side connector of FRRK62-*** Pin No Metal Signal name RD SD SG DR ER shell Wire core Red Black Green White Yellow Brown Shield

156 7 FUNCTION Batch read (2) Functions The serial communication function allows the MC protocol commands in the following table to be executed. Refer to the following manual for details of the MC protocol. Q-Compatible MELSEC Communication Protocol Reference Manual Function Command Processing Processing Points Reads bit devices by 1 point. ASCII: 3584 points in bits 41 ( 1) BIN: 7168 points Reads bit devices by 16 points. 48 words (768 points) in words 41 ( ) Reads word devices by 1 point. 48 words Batch write 1 Writes to bit devices by 1 point. ASCII: 3584 points in bits 141 ( 1) BIN: 7168 points Writes to bit devices by 16 points 48 words (768 points) in words 141 ( ) Writes to word devices by 1 point. 48 words Device memory Reads bit devices by 16 points or 32 points by Random read in words 43 ( designating the devices at random. ) Reads word devices by 1 point or 2 points by designating the devices at random. in bits 142 ( 1) Sets/resets bit devices by 1 point by designating the devices at random. Test 1 Sets/resets bit devices by 16 points or 32 points (Random write) by designating the units at random. in words 142 ( ) Writes to word devices by 1 point or 2 points by 96 points 94 points 2 designating the devices at random. Registers the bit devices to be monitored by points Monitor points or 32 points. in words 81 ( ) registration Registers the word devices to be monitored by 1 96 points point or 2 points. Monitors the devices registered for monitoring. Number of points Monitor in words 82 ( ) registered for monitor 1: When performing write during RUN of the CPU module, set write during RUN setting to "Enable". 2: Set the number of processing points within the range of the following expression. (Number of word access points) 12 + (number of double word access points) One point of a bit device corresponds to 16 bits for word access or to 32 bits for double word access. One point of a word device corresponds to one word for word access or to two words for double word access

157 7 FUNCTION (3) Accessible devices Class Device Device Code Internal system device Internal user device Device Number Range 1 (Default Value) Function input FX 2 to F Hexadecimal Function output FY 2 to F Hexadecimal Function register FD to 4 Decimal Special relay SM to 123 Decimal Special register SD to 123 Decimal Input X to 7FF Hexadecimal Output Y to 7FF Hexadecimal Internal relay M to 8191 Decimal Latch relay L to 247 Decimal Annunciator F to 123 Decimal Edge relay V to 123 Decimal Link relay B to 7FF Hexadecimal Data register D to Decimal Link register W to 7FF Hexadecimal Timer Retentive timer Counter Contact TS Coil TC Current value TN Contact Coil SS SC Current value SN Contact CS Coil CC Current value CN to 511 Decimal Decimal to 511 Decimal Special link relay SB to 3FF Hexadecimal Special link register SW to 3FF Hexadecimal Step relay S to 247 Decimal Direct input DX to 7FF Hexadecimal Direct output DY to 7FF Hexadecimal Index register Z to 9 Decimal File register R to Decimal ZR to 7FFF Hexadecimal 3 Write Read : Read/write enabled, : Write disabled 1: The device number ranges given in the above table are default values. When you have changed the number of device points on the QCPU or Q1CPU, use the new device number range. 2: Undefined values enter into 5 to F of FX and FY. 3: Hexadecimal when specified for the command of the MC protocol

158 7 FUNCTION (4) Setting of transmission specifications Use the serial communication setting PLC parameters to set the transmission speed, sum check, transmission wait time and write during RUN setting of the serial communication function. (a) (b) When using the serial communication function to make communication with the personal computer, Display device or the like, specify "Use serial communication". The default values of the transmission speed, sum check, transmission wait time and write during RUN setting are displayed. You can change the transmission speed, sum check, transmission wait time and write during RUN setting according to the specifications of the external device. Click here to use the serial communication function. Selecting "Use serial communication" allows you to change the settings. (5) Instructions (a) (b) Connection can be switched to GX Developer during communication with the personal computer, Display device or the like using the serial communication function. However, the personal computer, Display device or the like that was making communication using the serial communication function results in a communication error. Refer to the manual of the used device for the way to start the personal computer, Display device or the like when the CPU module is reconnected with the personal computer, Display device or the like. When "Use serial communication" is set, the transmission speed changed on the connection target setup screen of GX Developer is not made valid. POINT The data set in serial communication setting is made valid when: The PLC is powered on; or The CPU module is reset

159 7 FUNCTION Error Code (Hexadecimal) 4H to 4FFFH 7153H 7155H 7164H 7167H 7168H 716DH 7E4H 7E41H 7E42H 7E43H 7E47H 7E4FH 7E5FH 7E64H 7F1H 7F21H (6) Error codes for communication made using serial communication function The following table indicates the error codes, error definitions and corrective actions that are sent from the CPU module to the external device when errors occur during communication made using the serial communication function. Error Item Error Definition Corrective Action Frame length error Unregistered monitor error Requested data error Disabled during RUN Monitor registration error Command error Data length error Data count error Device error Continuous request error Device point count error Request destination module I/O number error Registered point count range error Buffer full error Receive header section error (CPU detected error) Error that occurred in other than the serial communication function The length of the received message is outside the permissible range. A monitor request was given before monitor registration was made. The requested data or device specifying method is in error. A write command was specified for the setting of write during RUN disable. The command specified cannot be executed during RUN. The QnA-compatible 3C/4C frame was not used for monitor registration. The command or sub-command specified does not exist. The number of points specified for random read/write exceeds the number of points enabled for communication. The requested number of points exceeds the range of the command. The device specified does not exist. The device specified cannot be specified for the corresponding command. The next request was received before the reply message was returned. The number of access points is incorrect. The request destination module I/O number is in error. Refer to the Appendices of the Basic Model QCPU (Q Mode) User's Manual (Hardware Design, Maintenance and Inspection), and take corrective action. Reconsider the sent message. The number of access points of the message should be within the permissible range. Give a monitor request after registering the device to be monitored. Check and correct the sent message/requested data of the device on the other end, and restart communication. Change the setting to write during RUN enable and restart communication. Set the CPU module to STOP and restart communication. Perform monitor registration again. Check and correct the sent message of the device on the other end and restart communication. Check and correct the sent message of the device on the other end and restart communication. Check and correct the sent message of the device on the other end and restart communication. Check and correct the sent message of the device on the other end and restart communication. Do not give continuous requests from the device on the other end. Match the monitoring time of timer 1 with the time-out period of the device on the other end. Check and correct the sent message of the device on the other end and restart communication. Correct the module I/O number of the data send destination. The number of registered points (word/bit) is outside the range. Correct the set value of the registered points (word/bit). The next data was received before Perform handshake with the device on the completion of received data other end, for example, to increase the processing. sending intervals. The command (frame) section specified Check and correct the sent message of the is in error. device on the other end and restart The ASCII code received cannot be communication. converted into binary

160 7 FUNCTION Error Code (Hexadecimal) 7F22H 7F23H 7F24H 7F67H Error Item Error Definition Corrective Action Command error MC protocol message error Sum check error Overrun error The command or device specified does not exist. The remote password length is in error. The data (e.g. ETX, CR-LF) specified after the character part does not exist or in error. The calculated sum check does not match the received sum check. The next data was received before the CPU module completed receive processing. 7F69H Parity error The parity bit setting does not match. 7F6AH Buffer full error F H The receive buffer of the OS overflew, resulting in skipped receive data. Error detected by the MELSECNET/H network system. Check and correct the sent message of the device on the other end and restart communication. Check and correct the sent message of the device on the other end and restart communication. Reconsider the sum check of the device on the other end. Reduce the communication speed and restart communication. Check the CPU module for occurrence of an instantaneous power failure. (For the CPU module, use the special register SD53 to check.) When an instantaneous power failure has occurred, remove its cause. Match the setting of the CPU module with that of the device on the other end. Exercise DTR control to make communication, preventing a buffer full error. Check the send message of the device on the other end, make corrections and retry. (The station number may have been specified. Communication with stations on other than MELSECNET/H or Ethernet is not available.)

161 8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE 8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE (1) Description of intelligent function modules Basic model QCPU allows the use of the Q series-compatible intelligent function modules. The intelligent function module is a module that allows Basic model QCPU to process analog values or high-speed pulses which cannot be processed with I/O modules. For example, an analog value is converted into a digital value with the analog/digital conversion module, one of the intelligent function modules, before being used. (2) Communication with intelligent function modules The intelligent function module is equipped with memory (buffer memory) to store the data received from or output to external devices. Basic model QCPU reads/writes the data from/to the buffer memory. 8.1 Communication Between Basic model QCPU and Q-series Intelligent Function Modules 8 Communication method with intelligent function modules GX Configurator The following methods enable the communication between Basic model QCPU and intelligent function modules: Initial setting or automatic refresh setting using the GX Configurator Device initial value Intelligent function module device Instructions dedicated for intelligent function modules FROM/TO instruction The following table shows the communication timing for the communication methods with intelligent function modules described above: Initial setting Automatic refresh setting 1 1 Power ON Basic model QCPU reset Communication timing STOP RUN Instruction execution END processing Device initial value Intelligent function module device(u \G ) Instructions dedicated for intelligent function modules FROM/TO instruction Communication timing... : Executed : Not executed REMARK 1: The initial setting and automatic refresh setting of GX Configurator are stored into the program memory or standard ROM in the Basic model QCPU

162 8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE Initial setting and automatic refresh setting using GX Configurator (1) Initial and automatic refresh settings of intelligent function modules Installing the GX Configurator compatible with the intelligent function module enables the initial setting and automatic refresh setting with GX Developer. When the initial setting and automatic refresh setting of the intelligent function module is designated with GX Developer, you can write/read data without creating the program for the communication with the intelligent function module. Moreover, you can conduct the initial setting or automatic refresh setting without designating the buffer memory address of the intelligent function module. (2) Setting using the GX Configurator This section describes the example to set the initial setting and automatic refresh setting of A/D conversion module Q64AD. (a) Initial setting The initial setting of Q64AD offers the following four settings: Designation of enable/disable A/D conversion Designation of sampling/averaging processing Designation of time averaging/execution averaging Designation of average time/average execution The initial setting of Q64AD is designated on the following initial setting screen of GX Configurator. [Initial setting screen] 8 The designated initial setting data is stored in the intelligent function module

163 8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE (b) Automatic refresh setting For the automatic refresh setting, designate the device at Basic model QCPU to store the following data. Digital output of Q64AD Maximum/minimum values of Q64AD Error code The automatic refresh setting of Q64AD is designated on the following automatic refresh setting screen of GX Configurator. [Automatic refresh setting screen] The designated automatic refresh setting data is stored in the intelligent function parameters of Basic model QCPU. REMARK For the details of the GX Configurator, refer to the manual of the intelligent function module being used

164 8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE Communication using device initial values (1) Device initial values Using the device initial values, the initial setting of the intelligent function module can be made without a program. The set device initial values are written from the Basic model QCPU to the intelligent function module when the PLC is powered on, the Basic model QCPU is reset, or the mode is switched from STOP to RUN. (2) Setting of device initial values Make the following setting using GX Developer. Set to the device memory the intelligent function module data to be used as the device initial values. In the device initial value setting, specify the range of the intelligent function module device to be used as the device initial values. REMARK 1) Refer to Section for the device initial values. 2) Refer to Section 1.5 for the intelligent function module device Communication using FROM/TO instructions (1) FROM/TO instructions When the FROM/TO instruction is executed, the data stored in the buffer memory of the intelligent function module can be read or data can be written to the buffer memory of the intelligent function module. The FROM instruction stores the data read from the buffer memory of the intelligent function module to the specified device. REMARK 1) Refer to the following manual for details of the FROM/TO instructions. QCPU (Q mode)/qnacpu Programming Manual (Common Instructions) 2) For details of the buffer memory of the intelligent function module, refer to the manual of the used intelligent function module

165 8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE Communication Using The Intelligent Function Module Device (1) Intelligent function module device The intelligent function module device is the buffer memory of the intelligent function module represented as a device of Basic model QCPU program. It enables reading data stored in the buffer memory of the intelligent function module, or enables writing data to the buffer memory of the intelligent function module. For example, programming can be performed as shown below when "1" is written to the buffer memory address of the intelligent function module whose I/O numbers are X/Y2 to X/Y2F. [ ] MOV K1 U2\G Buffer memory address I/O number X/Y2 (2) Difference from the FROM/TO instruction The intelligent function module device can be handled as a device of Basic model QCPU, enabling the processing of data read from the intelligent function module with one instruction. For example, programming can be performed as show below when the result of adding the data imported from the intelligent function module and the data of D is stored into D2. [ ] + U2\GO D D2 This saves the number of steps in the entire program. The instruction processing time is the time obtained by adding the time for access to/from the intelligent function modules to the instruction execution time. POINT When reading and processing the data of the intelligent function module frequently in the program, use the FROM instruction to read the data at one point in the program and store and process it in a data register, instead of using the intelligent function module device every time. Otherwise, the intelligent function module device accesses the intelligent function module every time the instruction is executed, resulting in longer scan time for the program. REMARK For the intelligent function module device, refer to Section

166 8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE Communication Using The Instructions Dedicated for Intelligent Function Modules (1) Description of the instructions dedicated for intelligent function modules (a) The instructions dedicated for intelligent function modules are the instructions that facilitate programming using the functions of the intelligent function modules. For example, the OUTPUT instruction, which is the instruction dedicated for serial communication modules, allows data transmission in user-specified message format with no handshaking protocol. In this case, the communication is possible without considering the buffer memory address of the objective serial communication module. Basic model QCPU b15 S b Serial communication module Channel 1 Channel 2 transmission transmission set the channel to use by control data (b) A completion device should be designated for the instruction dedicated for intelligent function modules. The designated completion device turns ON for one scan when the execution of the instruction dedicated for intelligent function modules is completed. When the completion device turns ON, another instruction dedicated for intelligent function modules can be executed to the same intelligent function module. To use two or more instructions dedicated for intelligent function modules to one intelligent function module, be sure to execute the next instruction dedicated for intelligent function modules after the completion device turns ON. (2) Instructions (a) If the instruction dedicated for intelligent function modules are executed and Basic model QCPU is switched from RUN to STOP before the completion device turns ON, the completion device turns ON one scan later when Basic model QCPU is switched to RUN next time. REMARK For the instruction dedicated for intelligent function modules and the completion device, refer to the manual of the intelligent function module being used

167 8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE 8.2 Request of Intelligent Function Module to Basic Model QCPU Interrupt from intelligent function module (1) Interrupt from intelligent function module The Basic model QCPU can execute an interrupt program (I5 to I127) at the interrupt request of the intelligent function module. For example, the serial communication module can perform data receive processing in an interrupt program when either of the following data communication functions is executed. Data receive at communication in no-procedure protocol Data receive at communication in bidirectional protocol By performing data receive processing in an interrupt program, the import of receive data to the Basic model QCPU can be speeded up. Device on other end of communication Data send Serial communication module Receive Interrupt issue Main program Main program Basic model QCPU Interrupt program execution FEND I SM4 BUFRCVS (2) Setting of interrupt from intelligent function module To execute an interrupt program by making interrupt from the intelligent function module, "Intelligent function module setting (interrupt pointer setting) must be made in the PLC system setting of the PLC parameter dialog box. Also, "System setting" must be made in the intelligent function module. When executing an interrupt program by making interrupt from the intelligent function module, refer to the manual of the used intelligent function module

168 9 PARAMETER LIST 9 PARAMETER LIST (1) Parameter types and setting (a) The Basic model QCPU has two different parameter types: the "PLC parameters" set for a system that uses the PLC independently; and the "network parameters" set for use of MELSECNET/H, Ethernet or CC-Link. (b) In the Basic model QCPU of function version B, the following items necessary to configure a multiple PLC system have been added to the PLC parameters. (Refer to Section ) Multiple PLC setting Control CPU setting (I/O assignment) (c) In this chapter, the PLC parameters and network parameters to be set using GX Developer are listed in a table. For details of each setting item, refer to the reference section or reference manual given in the table. For the setting operation on GX Developer, refer to the GX Developer Operating Manual. (2) When any PLC parameter setting has been changed, power off and then on the PLC (ON to OFF to ON), or reset the QCPU. If the Basic model QCPU is switched from STOP to RUN without any operation after the PLC parameter setting change, the new parameter setting may not became valid or PARAMETER ERROR (error code: 3) may occur

169 9 PARAMETER LIST Table 9.1 Parameter List Item Parameter No. Description PLC name settings Designate the label and comment for the CPU module to be used. These settings do not affect CPU module operation Label H Designates the label setting (name and use). Comment 1H Designates the comment setting. PLC system settings These are the settings required for using the CPU module. Default values are available for PLC control. Timer setting Low-Speed timer High-Speed timer 1H Designates the low-speed/high-speed timer settings Designates the contact which controls the CPU's module RUN-PAUSE contact 11H RUN/PAUSE operation. Setting of only the PAUSE contact cannot be made. (Setting of the RUN contact or RUN contact + PAUSE contact can be made.) Remote reset 12H Enables/disables the remote reset operation from the GX Developer. STOP to RUN output mode 13H Designates the output(y) mode at STOP-RUN switching. Intelligent function module setting (interrupt pointer setting) 1AH Set the assignment of the interrupt pointers (I5 to I127) and the head I/O No. and head SI No. of the intelligent function module. Number of vacant slot points 17H Designates the number of vacant slot points in the base/extension base midule. System interrupt settings Interrupt counter In Fixed cycle interval (n: 28 to 31) Designates the interrupt counter "first No." 18H Specifies time intervals at which to execute interrupt pointers (I28 to I31). 9 Interrupt program/fixed scan Specifies whether to perform the high-speed execution of an 18H program setting interrupt program. Module synchronization 1CH Specifies whether to bring the start of a CPU module into synchronization with the start of an intelligent-function module. PLC file setting Set the file to be used by the CPU module. Device initial value 112H Sets the device initial value file to be used by the CPU module. PLC RAS settings These settings are used for the RAS function. WDT settings WDT setting 3H Set the watchdog timer of the CPU module. Operation mode at error occurrences 32H Designates the CPU module operation mode to be established when an error is detected. Error check 31H Designates whether or not to detect a specified error. Constant scan 33H Designates the constant scanning time

170 9 PARAMETER LIST Default Value Setting Range Reference Section No setting Max. of 1 characters No setting Max. of 64 characters 1 ms 1 ms to 1 ms(1 ms units) Section ms.1 ms to 1. ms Section No setting X to X7FF Section Section Disabled Enabled/Disabled Section Previous status (produce the status of an output (X) before STOP Produce the status of an output (X) before STOP/Clear the output (output is 1 scan later) Section 7.4 No setting Head I/O No., head SI No., I5 to I127 Section 1.1 QJCPU: 16 points, 32 points, 64 points, 128 points, 16 points 256points Section QCPU/Q1CPU: 16 points, 32 points, 64 points, 128 Section points, 256 points, 512 points, 124 points No setting C to C1348 (Counter setting points can be set up to 128.) Section I28: 1. ms I29: 4. ms I3: 2. ms I31: 1. ms 2 to 1 ms (1 ms units) Section 1.1 The high-speed execution is disabled. Enable/Disable the high-speed execution. Section The start of an intelligent-function Yes/No to synchronize the start of an intelligent-function module is synchronized. module. Not used Not used Used Section ms 1 ms to 2 ms (1 ms units) Section 4.2 Stop Stop/Continue Section 7.14 Checked Checked/Not checked Section 7.14 No setting 1 ms to 2 ms(1 ms units) Section

171 9 PARAMETER LIST Table 9.1 Parameter List (continued) Item Parameter No. Description Device settings These settings designate the number of points for each device, the latch range, and the local device range Number of device points 2H Designates the number of device points used. Latch (1) first/last (Latch clear valid) Latch (2) first/last (Latch clear invalid) 21H 22H Set the latch range where data can be cleared by remote latch clear operation (first device number/last device number). Set the latch range where data cannot be cleared by remote latch clear operation (first device number/last device number). Boot file setting 7H Set whether boot will be performed from the standard ROM or not. SFC program start mode 82H SFC Set the SFC program start mode and start condition for use of an Start condition 83H setting SFC program and the output mode for a block stop. Output mode for block stop 86H Multiple CPU setting Make setting to configure a multiple CPU system. Number of CPUs EH Set the number of CPU modules to be used in the multiple CPU system. Operation mode E1H Set the operation of the multiple CPU system if the CPU modules No. 2, No. 3 result in a stop error. If CPU No. 1 results in a stop error, the multiple CPU system stops. (Fixed) Non-group input setting E4H Set whether the input statuses of the input modules and intelligent function modules controlled by the other CPUs will be imported or not. Non-group output setting Set whether the output statuses of the output modules controlled by the other CPUs will be imported or not. Refresh setting E2H E3H Set the device and its number of points used to write/read data by automatic refresh between the CPU modules of the multiple CPU system

172 9 PARAMETER LIST X: 8 k points Y: 8 k points M: 8 k points L: 8 k points B: 8 k points F: 2 k points SB: 2 k points V: 2 k points S: 8 k points T: 2 k points ST: k point C: 1 k point D: 12 k points W: 8 k points SW: 2 k points Default Value Setting Range Reference Section X(2 k points), Y(2 k points), S(2 k points), SB(1k points) and SW(1 k points) are fixed. Including the above points(1.5 k words), a total range of 16.4 k words is available. For one device: Max. 32 k points (There is no restriction on the total number of bit device points.) Section 1.1 Section 1.2 No setting Only 1 range is designated for each device of B, F, V, T, ST, C, D, W. Section 7.3 No setting Only 1 range is designated for each device of L, B, F, V, T, ST, C, D, W. Section 7.3 Boot not performed Boot not performed, boot performed Section Refer to the QCPU (Q mode)/qnacpu Programming Manual (SFC). 1 module 1 to 3 modules Section Error of CPU No. n stops all the CPUs. Error of CPU No. n stops/does not stop all the CPUs. Section Non-group input is not permitted. Non-group input is permitted/not permitted. Section 17.2 Non-group output is not permitted. Non-group output is permitted/not permitted. Section 17.2 No setting Send range for each CPU module: to 32 points (in units of 2 points)/module Maximum 4416/system CPU module side devices: B, M, Y, D, R, ZR The device of points set in the send range is occupied, starting from the specified device number. When the send range is 1 point, B, M or Y occupies 16 points. When the send range is 1 point, D, W, R or ZR occupies 1 point. Section

173 9 PARAMETER LIST Table 9.1 Parameter List (continued) Item Parameter No. Description I/O allocations Designates the installation status for each system module. Type Set the type of the module loaded. I/O allocation Model name Points 4H Set the model name of the module loaded. (CPU module not used. User's memo) Set the number of points of the corresponding slot. Start XY (First I/O number) Set the first I/O number of the corresponding slot. Base model name Set the model name of the main or extension base unit used. (CPU module not used. User's memo) Set the model name of the power supply module loaded on the Power model main or extension base unit. (CPU module not used. User's name Base setting 41H memo) Increase cable Set the extension cable model name. (CPU module not used. name User's memo) Slots Set the number of slots of the main or extension base unit. Set the number of slots to all base units. Switch setting 47H Set various switches of the intelligent function module. Error time output Set whether the output will be cleared or held when the control 43H module CPU results in a stop error. H/W error time Set whether the operation of the control CPU will be stopped or PLC operation 44H continued when the hardware fault of the intelligent function Detailed mode module occurs. setting I/O response time 45H Set the response times of the input, high-speed input, hybrid I/O and interrupt modules. Control CPU 46H Set the control CPU of the I/O or intelligent function module. X/Y allocation check Enables the user to check I/O assignments, MELSECNET/ETHERNET settings, and CC-Link settings. Serial communication setting Set the transmission speed, sum check, message wait time and write during RUN enable/disable when using the serial communication function of Q/Q1CPU. Use of serial communication function Using the serial communication function turns on the check box. Baudrate Set the transmission speed for data communication with the device on the other end Set whether to add the sum check code to the send and receive Sum check messages according to the specifications of the device on the 1EH other end when making data communication using the serial communication function. Set the waiting time of the CPU module when data cannot be Message wait time received immediately after the device on the other end has sent the data. Write during RUN setting Set whether data will be written or not from the other end device to the CPU module if the CPU module is during RUN

174 9 PARAMETER LIST No setting No setting Default Value Setting Range Reference Section CPU No. 2 to No. 3: No. n/empty (Set "CPU (Empty)" for the slot not mounted with a CPU module.) Input, High-speed input, Output, Intelligent, Hybrid I/O, Interrupt 16 characters No setting No setting QJCPU QCPU, Q1CPU Q JCPU QCPU, Q1CPU : points, 16 points, 32 points, 48 points, 64 points, 128 points, 256 points : points, 16 points, 32 points, 48 points, 64 points, 128 points, 256 points, 512 points, 124 points : H to FH : H to 3FH Section 5.6 No setting 16 characters No setting 16 characters Section 5.3 No setting 16 characters No setting 2, 3, 5, 8, 1, 12 No setting Refer to the manual of the intelligent function module used. Section 7.1 Clear Clear/Retain Section 7.8 Stop Stop/Continue Section 7.9 Input, I/O combined : 1ms, 5ms, 1ms, 2ms, 7ms Input, I/O combined: 1ms High-speed input, Interrupt :.1ms,.2ms,.4ms,.6ms, Section 7.7 High-speed input, Interrupt:.2ms 1ms No. 1 No. 1, No. 2, No. 3 Section kbps Yes 9.6 kbps/19.2 kbps/38.4 kbps/57.6 kbps/115.2 kbps No/Yes Section 7.17 No wait No wait/1ms to 15ms (1ms increments) Not enabled Not enabled/enabled

175 9 PARAMETER LIST Table 9.1 Parameter List (continued) Item Parameter No. Description Network parameters Set the parameters for MELSECNET/H, Ethernet or CC-Link. MELSECNET/H setting 1 2 Number of modules setting 5H Head I/O No. Network No. 5NMH Total number of link slave stations Group No. 5mnH Valid module for other station 51H access Set the network parameters of MELSECNET/H. Routing parameter 53H Network setting 5NMH Network refresh parameter 5NM1H Common parameter 5NM2H Station-specific parameter 5NM3H Common parameter 2 5NMAH Station-specific parameter 2 5NMBH Interrupt setting 5NMBH Ethernet setting 1 Number of modules setting 9H Head I/O No. Network No. 9NH Operation setting Initial setting 9N1H Open setting 9N2H Router relay parameter 9N3H Set the network parameters of Ethernet. Routing parameter 9N4H IP station number related information 9N5H FTP parameter 9N6H setting 9N7H Notification setting 9N8H Interrupt setting 9N9H CC-Link setting 3 Number of modules setting CH Remote input (RX) refresh device Remote output (RY) refresh device Remote register (RWr) refresh device Remote register (RWw) refresh CNM1H device Special relay (SB) refresh device Special register (SW) refresh device Head I/O No. Set the network parameters of CC-Link. Total number of connected stations Number of retry times Number of stations that automatically return to system Standby master station number CNM2H CPU fault designation Scan mode designation Delay time setting Station information setting Remote device station initial setting Interrupt setting CNM2H

176 9 PARAMETER LIST Table 9.1 Parameter List (continued) Default Value Setting Range Reference Section No setting Refer to the Q Corresponding MELSECNET/H Manual. No setting Refer to the Q Corresponding Ethernet Manual. No setting Refer to the CC-Link Manual

177 9 PARAMETER LIST Table 9.1 Parameter List (continued) Item Parameter No. Description Remote password Set the remote password for the Ethernet, serial communication or modem interface module. Password setting Enter the remote password. Password valid module setting Model name Head X/Y Select the module model name to be checked for the remote password set to the QCPU. Set the head address of the module to be checked for the remote password. Detailed setting User connection No. valid setting Set the user connection No. System connection valid setting Set the remote password valid port of the system connection

178 9 PARAMETER LIST Default Value Setting Range Reference Section No No 4 bytes, alphanumeric characters, special symbols QJ71E71/QJ71C26/QJ71CMO No H to 3EH No Connection No. 1 to connection No. 16 Specify the remote password valid port. Automatic open UDP port FTP communication port (TCP/IP) No GX Developer communication port (TCP/IP) GX Developer communication port (UDP/IP) HTTP port Section

179 9 PARAMETER LIST 1: N and M indicate the following. N: Indicates the serial number of the module. M: Indicates the network type. M 1H 2H 3H 4H Network Type MELSECNET/1 mode (control station), MELSECNET/H mode (control station) MELSECNET/1 mode (normal station), MELSECNET/H mode (normal station) MELSECNET/1 mode (control station) MELSECNET/1 mode (normal station) 2: m and n indicate (head I/O No. / 16). 3: N and M indicate the following. N: Indicates the serial number of the module. M: Indicates the network type. M H 1H Master station Local station Network Type

180 1 DEVICES 1 DEVICES This chapter describes all devices that can be used in Basic model QCPU. 1.1 Device List Class Type Device Name Internal user devices Internal system devices Bit devices Word devices Bit devices Word devices The names and data ranges of devices which can be used in Basic model QCPU are shown in Table 1.1 below. Input Output 1 1 Table 1.1 Device List Number of Points Default Values Range Used Parameter Designated Setting Range Reference Section 248 points X to X7FF Section points Y to Y7FF Section Internal relay 8192 points M to M8191 Section Latch relay 248 points L to L247 Section Anunciator 124 points F to F123 Section Edge relay 124 points V to V123 Section Step relay points S to S127/block Change possible Section Link relay 248 points B to B7FF for 16.4 k words or Section Special link relay points SB to SB3FF less. 3 Section Timer 2 Retentive timer Counter points T to T511 points (ST to ST511) Section points C to C511 Section Data register points D to D11135 Section Link register 248 points W to W7FF Section Link special register points SW to SW3FF Section Function input 16 points FX to FXF 3 Section Function output 16 points FY to FYF 3 Section Special relay 1 points SM to SM999 Impossible Section Function register 5 points FD to FD4 Section Special register 1 points SD to SD999 Section REMARK 1: For the inputs, outputs, step relays, special link relays and special link registers, their default values cannot be changed. 2: For the timers, retentive timers and counters, their contacts and coils are bit devices and their current values are word devices. 3: Only FX to FX4 and FY to FY4 can be used in programs

181 1 DEVICES Class Type Device Name Link direct devices Intelligent function module device Index register Bit device Word device Number of Points Default Values Range Used Link input 8192 points Jn\X to Jn\X1FFF Link output 8192 points Jn\Y to Jn\Y1FFF Link relay points Jn\B to Jn\B3FFF Link special relay 512 points Jn\SB to Jn\SB1FF Link register points Jn\W to Jn\W3FFF Link special register 512 points Jn\SW to Jn\SW1FF Word device Buffer register points Parameter Designated Setting Range Reference Section Impossible Section 1.4 Un\G to Un\G Impossible Section 1.5 Word device Index register 1 points Z to Z9 Impossible Section 1.6 File register Word device File register QCPU, Q1CPU QJCPU points 64k points R to R32767 ZR to ZR65535 Impossible Section 1.7 Nesting Nesting 15 points N to N14 Impossible Section 1.8 Pointers Other Pointer 3 points P to P299 Section 1.9 Impossible Interrupt pointer 128 points I to I127 Section 1.1 Bit device SFC block device 128 points BL to BL127 Impossible Section Constants Network No 239 points J1 to J239 Section I/O No Macro instruction argument device QJCPU QCPU, Q1CPU U to UF U to 3F Impossible Section VD to VD Impossible Section Decimal constants K to K Section Hexadecimal constants H to HFFFFFFFF Section Real number constant E to E Section Character string 5 "ABC" and "123" Section constants REMARK 4: The number of actually usable points changes depending on the intelligent function module. For the number of buffer memory points, refer to the manual of the intelligent function module used. 5: Character strings can be used with only the $MOV instruction. They cannot be used with other instructions

182 1 DEVICES 1.2 Internal User Devices Internal user devices can be used for various user applications. The "number of usable points" setting is designated in advance (default value) for internal user devices. However, this setting can be changed by PLC parameter device setting. [Device setting screen] Default value "Dev. point" can be changed at devices where a "Dev. point" value is shown in brackets. (1) Setting range in the internal user device For all Basic model QCPU internal user devices other than the input (X), output (Y), step relay (S), special link relay, and special link registers (SW) devices, the number of points used can be changed within a 16.4 k word (including 1.5k words for an internal user device) range by PLC parameter device setting. The items to consider when making such changes are discussed below. (a) Setting range 1) The number of device points is designated in 16-point units. 2) A maximum of 32 k points can be designated for one type of device. 1 point is calculated as 2 points (1 for coil, 1 for contact) for the timer, retentive timer, and counter. (2) Memory size Use the following formula to obtain the memory size of an internal user device (Bit devices size) + (Word devices size) + (Timer, retentive timer and counter size) 16.4k (a) For bit devices: For bit devices, 16 points are calculated as 1 word. (Bit device size) = (M+L+F+V+B total number of points) 16 (Word)

183 1 DEVICES (b) For timer (T) retentive timer (ST), and Counter (C): For the timer, retentive timer, and counter, 16 points are calculated as 18 words. (Timer, retentive, counter size) = (T, ST, C total number of points) (Word) (c) For word devices: For data registers (D) and link registers (W), 16 points are calculated as 16 words. (Word device size) = (D, W total number of points) (Word) POINT When the number of internal user device points used is changed in the parameter, the following files created with the previous parameter setting cannot be used as they are. Sequence program SFC program After changing the number of internal user device points used, read the sequence program and SFC program from the Basic model QCPU to GX Developer, and write them again to the Basic model QCPU

184 1 DEVICES Inputs (X) (1) Definition (a) Inputs are commands or data transmitted to the Basic model QCPU from a peripheral device by push-button switches, selector switches, limit switches, digital switches, etc. Push-button switch Selector switch Input (X) Sequence operation Digital switch (b) The input point is the Xn virtual relay inside the Basic model QCPU, with the program using the Xn's N/O contact or N/C contact. PB1 LS2 Virtual relay X X1 X X1 Programmable controller PB16 XF XF Input ladder (external device) Program Figure 1.1 Inputs(X) (c) There are no restrictions regarding the number of Xn N/O contacts and N/C contacts used in a program. No restrictions regarding the quantity used. X X Y21 X2 X1 X2 Y2 Y21 X Y23 Figure 1.2 Input(X) Used in Program

185 1 DEVICES (2) Reading the inputs (a) There are 2 types of input: "refresh inputs" and "direct access inputs". 1) Refresh inputs are ON/OFF data read from the input module using the refresh mode. 1 Basic model QCPU Read of ON/OFF data Input module Device memory by input refresh X1 These inputs are indicated as "X " in the sequence program. For example, a "1" input becomes "X1". 2) Direct access inputs are ON/OFF data read from the input module using the direct mode. 2 Basic model QCPU Read of ON/OFF data Input module Device memory at instruction execution DX1 ON/OFF data These inputs are indicated as "DX " in the sequence program. For example, a "1" input becomes "DX1". Direct access input can be made in a LD/AND/OR instruction that uses an input in units of 1 point. (b) Differences between refresh input and direct access input Since the direct access input accesses the input module directly at instruction execution, it imports an input faster than the refresh input. However, the direct access input takes longer instruction processing time than the refresh input. Moreover, direct access inputs can only be used for inputs used with the input module and intelligent/special function module which are installed at main and extension base unit. The refresh and direct input differences are shown in Table 1.2 below. Table 1.2 Differences Between Refresh Item Refresh Input Direct Access Inputs Input module installed at base/extension base unit Inputs of intelligent function module installed at base/extension base unit Usable Usable Inputs of I/O link module installed at base/extension base unit Inputs used at MELSECNET/H network system or CC-Link system Usable Unusable REMARK 1: See Section for details regarding the refresh mode

186 1 DEVICES (c) The same input number can be designated for a refresh input and a direct access input. The ON/OFF data read at the direct access input (DX) is also stored into the device memory. (Refer to Section (2).) When refresh input is used after use of the direct access input (DX), operation is performed using the ON/OFF data of the device memory (ON/OFF data read at the direct access input (DX)). X DX X Y1 Y11 Y12 Operation is performed using the ON/OFF data read at the input refresh before the operation start of the sequence program. Direct access input Operation is based on the ON/OFF data read at the input module. Operation is based on the ON/OFF data read at the direct access input. Figure 1.3 Refresh Input & Direct Access Input POINT (1) When debugging a program, an input (X) can be set to ON/OFF as described below. OUT Xn instruction OUT X1 ON/OFF command X1 Device test of GX Developer (2) With the CC-Link, an input (x) can be designated as a destination device for the RX refresh (on Basic model QCPU side) by using a CC-Link automatic refresh setting. Refresh destination (Basic model QCPU side) device of link input of MELSECNET/H

187 1 DEVICES Outputs (Y) (1) Definition (a) Outputs are program control results which are output to external destinations (solenoid, electromagnetic switch, signal lamp, digital display, etc.). Signal lamp Output (Y) Digital display Sequence operation Contact (b) (c) Outputs occur at one N/O contact or its equivalent. There are no restrictions regarding the number of output Yn N/O contacts and N/C contacts used in a program. Programmable controller X Y2 No restrictions regarding the quantity used. Y2 Load M51 X1 Y2 Y2 X3 X2 Y21 Y22 Program Out ladder (external device) Figure 1.4 Output(Y) Operation (2) Using outputs as internal relays (M) "Y" inputs corresponding to vacant slots and slots where input modules are installed can serve as internal relays (M). Power supply module CPU module Input module Input module Output module Output module Output module OUT Yn Equivalent to internal relay

188 1 DEVICES (3) Output method (a) There are 2 types of output: "refresh outputs" and "direct access outputs". 1) Refresh outputs are ON/OFF data which is output to the output module using the refresh mode. 1 Basic model QCPU Output of ON/OFF data Output module Device memory by output refresh Y1 These outputs are indicated as "Y " in the sequence program. For example, a "1" input becomes "Y1". 2) Direct access outputs are ON/OFF data which is output to the output module using the direct mode. 2 Basic model QCPU Output of ON/OFF data Output module at instruction execution Device memory DY1 ON/OFF data These outputs are indicated as "DY " in the sequence program. For example, a "1" input becomes "DY1". (b) Differences between refresh outputs and direct access outputs With direct access outputs, the output module is directly accessed by executing an instruction, and the processing speed is therefore slower than that for refresh outputs. A refresh output takes longer to process instructions than a direct access output. Moreover, direct access outputs can only be used for outputs used with the output module and intelligent function module which are installed at base unit and extension base unit. The refresh and direct output differences are shown in Table 1.3 below. Table 1.3 Differences Between Refresh Outputs & Direct Access Outputs Item Refresh Input Direct Access Outputs Output module installed at main/extension base unit Outputs of intelligent function module Usable Usable installed at base/extension base unit Outputs used at MELSECNET/H network system or CC-Link system Usable Unusable REMARK 1: See Section for details regarding the refresh mode

189 1 DEVICES Internal relays (M) (1) Definition (a) Internal relays are auxiliary relays which cannot be latched by the programmable controller's internal latch (memory backup). All internal relays are switched OFF at the following times: When power at OFF is switched ON. When reset is executed. When latch clear is executed. (b) There are no restrictions regarding the number of contacts (N/O contacts, N/C contacts) used in the program. No restrictions regarding the quantity used. M switches ON at X OFF to ON X M SET M K2 The internal relay (M) ON can only be used for internal Basic model QCPU processing, and cannot be output externally. T Y2 M ON/OFF information is output from the output module to an external destination. X1 M M1 X2 M M247 Figure 1.5 Internal Relay (2) Procedure for external outputs Outputs (Y) are used to output sequence program operation results to an external destination. REMARK 1) When latch (memory backup) is required, use the latch relays (L). Refer to Section for the latch relays

190 1 DEVICES Latch relays (L) (1) Definition (a) Latch relays are auxiliary relays which can be latched by the programmable controller's internal latch (memory backup). Latch relay operation results (ON/OFF information) are saved even in the following cases: When power at OFF is switched ON. When reset operation is performed. The latch is backed up by the Basic model QCPU battery. (b) (c) Performing remote latch clear using GX Developer turns OFF the latch relay. However, the latch relay that has been set to "Latch (2): Cannot be cleared by latch clear" in the device setting PLC parameters cannot be turned OFF if remote latch clear is performed. There are no restrictions regarding the number of contacts (N/O contacts, N/C contacts) used in the program. No restrictions regarding the quantity used. L switches ON at X OFF to ON. X L SET L K2 The latch relay (L) ON can only be used for internal Basic model QCPU processing, and cannot be output externally. T Y2 L ON/OFF information is output from the output module to an external destination. X1 L L1 X2 L L247 Figure 1.6 Latch Relay (2) Procedure for external outputs Outputs (Y) are used to output sequence program operation results to an external destination. REMARK Internal relays (M) should be used when a latch (memory backup) is not required. See Section for details regarding internal relays

191 1 DEVICES Anunciators (F) (1) Definition (a) Anunciators are internal relays used by the user in fault detection program. (b) (c) When anunciators switch ON, a special relay (SM62) switches ON, and the Nos. and quantity of anunciators which switched ON are stored at the special registers (SD62 to SD79). At this time, the "ERR." LED is lit. Special relay :SM62... Switches ON if even one anunciator switches ON. Special register:sd62... No. of first anunciator which switched ON is stored here. SD63... The number (quantity) of anunciators which are ON is stored here. SD64 to SD79... Anunciator Nos. are stored in the order in which they switched ON. (The same anunciator No. is stored at SD62 and SD64.) The anunciator No. stored at SD62 is also registered in the "fault history area". However, only one annunciator number is stored into the failure history storage area while the PLC power is ON. The use of anunciators in the fault detection program permits the user to check for the presence/absence of fault and to check the fault content (anunciator No.), by monitoring the special registers(sd62 to SD79) when the special relay(sm62) switches ON. Example The program which outputs the No. of the ON annunciator (F5) is shown below. [Fault detection program] X X1 SM62 SET F5 BCDP SD62 K4Y2 Output of annunciator No. which switched ON Annunciator ON detection SM62 SD62 SD63 SD64 SD65 SD79 OFF to ON to 5 to 1 to

192 1 DEVICES (2) Annunciator ON procedure and processing (a) Anunciator ON procedure Anunciator operation can be controlled by the SET F and OUT POINT F instructions. 1) The SET F instruction switches the anunciator ON only at the leading edge (OFF to ON) of the input condition, and keeps the anunciator ON when the input condition switches OFF. In cases where many anunciators are used, the OUT F instruction can be used to speed up the scan time. 2) The OUT F instruction can switch the anunciator ON or OFF. It takes longer to do so than the SET F instruction. If the anunciator is switched OFF by using an OUT F instruction, this will require the execution of an RST F or BKRST instruction. Use a SET F instruction to switch the anunciator ON. If switched ON by any method other than the SET F and OUT F instructions, the anunciator functions in the same way as the internal relay. (Does not switch ON at SM62, and anunciator Nos. are not stored at SD62, SD64 to SD79.) (b) Processing at anunciator ON 1) Data stored at special registers (SD62 to SD79) a) Nos. of anunciators which switched ON are stored in order at SD64 to SD79. b) The anunciator No. which was stored at SD64 is stored at SD62. c) "1" is added to the SD63 value. SET F5 SET F25 SET F123 SD62 SD63 SD64 SD65 SD66 SD Up to 16 annunciator No. can be stored. SD ) CPU LED indication When any annunciator turns ON, the "ERR." LED on the front of the Basic model QCPU is lit. 3) Setting the display priority for error occurrence to SD27 - SD29 allows you to select whether the ERR. LED is to be ON or OFF when the annunciator turns ON. (3) Anunciator OFF procedure & processing content (a) Anunciator OFF procedure An anunciator can be switched OFF by the RST F, BKRST, and OUT F instructions. 1) An anunciator No. which has been switched ON by the SET F instruction can be switched OFF by the RST F instruction. 2) Use the BKRST instruction if you want to switch all the anunciator Nos. within a specified range.

193 1 DEVICES 3) The OUT F instruction can execute ON/OFF of the anunciator No. by the same instruction. However, if an anunciator is switched OFF by the OUT F instruction, the "processing at anunciator OFF" (item (b) below) does not occur. Execute the RST F or BKRST instructions after the anunciator has been switched OFF by the OUT F instruction. 1) To switch OFF the annunciators 5 (F5) Fault detection program (Annunciator ON program) Display reset input RST F5 Program that turns OFF annunciator 5 (F5) 2) To switch OFF all anunciators which are ON: Fault detection program (Annunciator ON program) Display reset input BKRSTP F K1 F to F9 OFF program REMARK For details regarding the RST and BKRST instruction, refer to the QCPU(Q mode)/qnacpu Programming Manual(Common Instructions)

194 1 DEVICES (b) Processing at anunciator OFF 1) Special register (SD62 to SD79) data operation when an anunciator is switched OFF by the RST F instruction a) The anunciator No. which was switched OFF is deleted, and all subsequent anunciator Nos. are moved up to fill the vacant space. b) If the anunciator No. stored at SD64 was switched OFF, the new anunciator No. which is stored at SD64 is stored at SD62. c) "-1" is subtracted from the SD63 value. d) If the SD63 value is "", SM62 is switched OFF. SET F5 SET F25 SET F123 RST F5 SD62 SD63 SD64 SD65 SD66 SD SD79 2) Data stored in special registers (SD62 to SD79) when annunciator is turned OFF by execution of BKRST instruction a) The annunciator number specified in the BKRST instruction is deleted and the annunciator numbers stored after the deleted one are shifted up. b) If the annunciator number stored in SD64 is turned OFF, the annunciator number newly stored in SD64 is stored into SD62. c) The data of SD63 is decremented by the number of reset annunciators. d) If the data of SD63 is, SM62 is turned OFF. 3) LED indication When all annunciator numbers in SD64 to SD79 turn OFF, the "ERR." LED is extinguished

195 1 DEVICES Edge relay (V) (1) Definition (a) An edge relay is a device which stores the operation results (ON/OFF information) from the beginning of the ladder block. Edge relays can only be used at contacts, and cannot be used as coils. X X1 X1 V1 Edge relay Stores the X, X1 and X1 operation results (b) The same edge relay number cannot be used twice in program executed by the Basic model QCPU. (2) Edge relay applications Edge relays are used for detecting the leading edge (OFF to ON) in program configured using index qualification. [Ladder example] SM4 MOV K Z1 Index register (Z1) OFF XZ1 *1 VZ1 *1 SM4 FOR K1 MZ1 INC Z1 Repetition (1 times) designation 1 scan ON at X leading edge Increment Index Register (Z1) (+1) NEXT Return to FOR instruction [Timing chart] When Z1= X OFF V OFF M OFF ON ON ON 1 Scan When Z1=1 X1 OFF V1 OFF M1 OFF ON ON ON 1 scan ON at X1 leading edge 1 Scan REMARK 1) 1: The ON/OFF information for XZ1 is stored at the VZ1 edge relay. For example, the X ON/OFF information is stored at V, and the X1 ON/OFF information is stored at V

196 1 DEVICES Link relays (B) (1) Definition (a) A link relay is the Basic model QCPU relay used to refresh the Basic model QCPU from the MELSECNET/H network module's link relay (LB) and to refresh the MELSECNET/H network module's link relay (LB) from the Basic model QCPU data. Basic model QCPU MELSECNET/H network module Link relay Link relay B LB Link refresh Link refresh setting range Internal relays or latch relays can be used for data ranges not used by the MELSECNET/H network system. Range where no link relay latch occurs...internal relay Range where link relay latch occurs...latch relay (b) There are no restrictions regarding the number of contacts (N/O contacts, N/C contacts) used in the program. X B SET B T K2 No restrictions regarding the quantity used. B switches ON at X OFF to ON. The link relay (B) ON can only be used for internal Basic model QCPU processing, and cannot be output externally. X1 B Y2 B1 B ON/OFF information is output from the output module to an external destination. X2 B B1FFF Figure 1.7 Link Relay (2) Using link relays in the network system In order to use link relays in the network system, a network parameter setting is required. REMARK 1) For details regarding the network parameters, refer to the For Qs MELSECNET/H Network System Reference Manual. 2) The MELSECNET/H Network Module has link relay points assigned. Basic model QCPU has 8192 link relay points assigned. When using subsequent points after Point 8192, change the number of link relay points by using the Device Setting sheet of the PLC Parameter dialog box

197 1 DEVICES Special link relays (SB) (1) Definition (a) A special link relay indicates the communication status and error detection of an intelligent function module, such as the MELSECNET/1H Network Module. (b) Because special link relays are switched ON and OFF in accordance with various problems which may occur during a data link, they serve as a tool for identifying data link problems. (2) Number of special link relay points There are a total of 124 special link relay points between SB and SB3FF. Special link relays are assigned at a rate of 512 points per each intelligent function module, such as the MELSECNET/1H Network Module. REMARK 1) For details regarding special link relays used at the Basic model QCPU, refer to the QCPU (Q mode)/qnacpu Programming Manual (Common Instructions) Step relays (S) The step relays are devices designed for SFC. Refer to the following manual for the step relay using method. QCPU (Q mode)/qnacpu Programming Manual (SFC) POINT The step relays cannot be used in place of the internal relays in sequence programs since the step relays are exclusively designed for SFC programs. If the step relays are used in place of the internal relays in a sequence program, an SFC error may occur, resulting in a system fault

198 1 DEVICES Timers (T) Timers are of a forward timer type, with the time measurement beginning when the coil switches ON, and ending (time out) when the present value exceeds the setting value. The present value matches the setting value when a "time-out" occurs. There are two types of timers: a low/high-speed that allows the current value to return to "" when a timer coil switches OFF, and a retentive timer that retains the current value even when a timer coil switches OFF. Timers Timers Low-speed timers High-speed timers Retentive timers Low-speed retentive timers High-speed retentive timers With a timer setting (instruction format), a device is assigned for a low-speed timer or high-speed timer. The OUT T instruction is used to assign a device for a low -speed timer. The OUTH T instruction is used to assign a device for a high-speed timer. With a timer setting (instruction format), a device is assigned for a low-speed retentive timer or high-speed retentive timer. The OUT T instruction is used to assign a device for a low-speed retentive timer. The OUTH T instruction is used to assign a device for a high-speed retentive timer. Low-speed timers (1) Definition (a) Low-speed timers are those that are only operative while the coil is ON. (b) [Ladder example] X The time measurement begins when the timer's coil switches ON, and the contact switches ON when a "time-out" occurs. When the timer's coil switches OFF, the present value becomes "", and the contact switches OFF. K1 T When X switches ON, the T coil switches ON, and the contact switches ON 1 second later. (The low-speed timer measures time in 1 ms units.) [Time chart] X T coil OFF OFF ON ON T contact OFF 1 Sec. ON (2) Measurement units (a) The default time measurement units setting for low-speed timers is 1 ms. (b) The time measurement units setting can be designated in 1 ms units within a 1 ms to 1 ms range. This setting is designated in the "PLC system settings" in the PLC parameter setting

199 1 DEVICES High-speed timers (1) Definition (a) (b) [Ladder example] High-speed timers are timers which are only operative while the coil is ON. A high-speed timer is marked with a symbol "H". The time measurement begins when the timer's coil switches ON, and the contact switches ON when the time elapses. When the timer's coil switches OFF, the present value becomes "", and the contact switches OFF. High-speed timer display X H K2 T2 When X switches ON, the T2 coil switches ON, and the contact switches ON 2 second later. (The high-speed timer measures time in 1 ms units.) [Time chart] X T2 coil OFF OFF ON ON T2 contact OFF 2 Sec. ON (2) Measurement units (a) The default time measurement units setting for high-speed timers is 1 ms. (b) The time measurement units setting can be designated in.1ms units within a.1 ms to 1 ms range. This setting is designated in the PLC system settings in the PLC parameter setting

200 1 DEVICES Retentive timers (1) Definition (a) Retentive timers measure the "coil ON" time. (b) (c) The measurement begins when the timer coil switches ON, and the contact switches ON when a time-out (coil OFF) occurs. Even when the timer coil is OFF, the present value and the contact ON/OFF status are saved. When the coil is switched ON again, the time measurement resumes from the present value which was saved. There are 2 retentive timer types: low-speed retentive timer, and high-speed retentive timer. X1 (d) The RST T instruction is used to clear (reset) the present value and switch the contact OFF. [Ladder example] X [Time chart] RST K2 ST ST X ON time is measured as 2 seconds when the timer measures time in 1 ms units. Retentive timer display When X1 switches ON, the ST contact is reset, and the present value is cleared. X T coil OFF OFF ON ON 15 Sec. 5 Sec. T present value 1 to to 2 T contact Present value is saved when coil switches. OFF ON RST ST instruction Contact remains ON when coil switches. Instruction execution X1 OFF ON (2) Measurement units (a) REMARK The measurement units settings for retentive timers are the same as those for low-speed timers and high-speed timers. Low-speed retentive timer: Same as low-speed timer High-speed retentive timer: Same as high-speed timer In order to use retentive timers, a retentive timer "number of points used" setting must be designated in the PLC parameters device settings

201 1 DEVICES Timer Processing & accuracy (a) When an OUT T instruction is executed, the following processing occurs: timer coil ON/OFF, present value update & contact ON/OFF processing. Timer present value update and contact ON/OFF processing do not occur at END processing. [Ladder example] X K1 T [Processing at OUT T instruction] Sequence program END OUT T END Processing content Coil ON/OFF Present value update Contact ON/OFF (b) When the OUT T instruction is executed, the present value is added to the scan time measured at the END instruction. If the timer coil is OFF when the OUT T instruction is executed, the present value is not updated. [Ladder example] X H T K8 [Present value update timing] Program ON X external input OFF OUT T END processing OUT T OUT T OUT T OUT T OUT T END processing END processing END processing END processing END processing QCPU's X OFF ON T coil OFF ON T contact OFF ON 1 ms measurement Measured value at END instruction T present value +2=2 2+3=5 5+2=7 7+3=1 Input reading timing (+1 scan) Timer accuracy - (1 scan time + timer time limit setting) to 1 scan time

202 1 DEVICES (c) The timer response accuracy from the point when input (X) reading occurs, until the point when the output occurs is + (2-scan time + timer time limit setting). Precautions when using timers The following are a few precautions regarding timer use: (a) A given timer cannot be designated (by OUT T ) more than once in a single scan. If it is, the timer's present value will be updated at each OUT T instruction, resulting in a meaningless measurement. Sequence program END OUT T OUT T 1 Scan OUT T END OUT T OUT T Present value is updated. (b) (c) When a timer (for example. T1) coil is ON, the OUT T1 instruction cannot be skipped using a CJ instruction, etc. If the OUT T instruction is skipped, the timer's present value will not be updated. Timers cannot be used in interrupt program. (d) If the timer set value is "", the contact goes ON when the OUT T instruction is executed. (e) (f) If the setting value changes to a value which is higher than the present value following a timer "time-out", the "time-out" status will remain in effect, and timer operation will not occur. If two timers are used, the ON/OFF ladders should be created as shown below. T T1 T K1 T1 K1 T M 1 second measurement following T ON 1 second measurement when T1 ON ON/OFF repeated every 1 second

203 1 DEVICES Counters (C) Counters are "up counter" types, with the contact being switched ON when the count value equals the setting value (count-out condition). There are two counter types: counters which count the number of input condition startups (leading edges) in sequence program, and counters which count the number of interrupt factor occurrences. Counters (1) Definition A counter is a device which counts the number of input condition leading edges in sequence program. (2) Count processing A counter is a device which counts the number of input condition leading edges in sequence program. (a) When and OUT C instruction is executed, the following counter processing occurs: coil ON/OFF, present value update (count value + 1), and contact ON/OFF. Counter present value update and contact ON/OFF processing do not occur at END processing. [Ladder example] X K1 C [Processing at OUT C Instruction (X: OFF to ON)] Sequence program END OUT C END Processing content Coil ON/OFF Present value update Contact ON/OFF (b) The present value update (count value + 1) occurs at the leading edge (OFF to ON) of the OUT C instruction. The present value is not updated in the following OUT C instruction statuses: OFF, ON to ON, ON to OFF [Ladder example] X K1 C [Present value update timing] Sequence program X OFF END OUT C END OUT C END OUT C ON C coil OFF ON Present value update Present value update

204 1 DEVICES (c) Sequence program Multiple counters can be used within a single scan to achieve the maximum counting speed. In such cases, the direct access input (DX ) method should be used for the counter input signals. 1 END OUT C OUT C OUT C END OUT C OUT C OUT C execution intervals (3) Resetting the counter (a) Counter present values are not cleared even if the OUT C instruction switches OFF. Use the RST C instruction to clear the counter's present value and switch the contact OFF. (b) [Ladder example] X The count value is cleared and the contact is switched OFF at the point when the RST C instruction is executed. RST C [Counter reset timing] Sequence program X OFF END RST C END RST C END RST C ON RST C instruction OFF Execution Count value cleared & contact OFF Count value cleared & contact OFF (4) Maximum counting speed The counter can count only when the input condition ON/OFF time is longer than the execution interval of the corresponding OUT C instruction. The maximum counting speed is calculated by the following formula: Maximum counting speed (Cmax) REMARK = n 1 1 T [times/sec] n: Duty(%) 2 T: Execution interval of the OUT C instruction 1) 1: See Section for details regarding direct access inputs. 2) 2: The "duty" is the count input signal's ON-OFF time ratio expressed as a percentage value. When T1 T1 T2 n = T1+T2 1 T2 When T1 < T2 n = T1+T2 1 Count input signal OFF ON T1 T

205 1 DEVICES Interrupt counters (1) Definition Interrupt counters are devices which count the number of interrupt factor occurrences. (2) Count processing (a) The interrupt counter's present value is updated when an interruption occurs. It is not necessary to create a program which includes an interrupt counter function. (b) Interrupt counter operation requires more than the simple designation of a setting value. To use the interrupt counter for control purposes, comparison instructions (=, <=, etc.) must also be used to enable comparisons with the setting value, with an internal relay (M), etc., being switched ON or OFF according to the comparison result. The figure below shows a sample program in which M is switched ON after 1 interrupt inputs occur. (In this example, "C3" is the interrupt counter No. corresponding to I.) = K1 C3 M (3) Setting the interrupt counter (a) In order to use interrupt counters, at first interrupt counter No. setting must be designated in the PLC system settings in the PLC parameter setting. 256 points are then allocated for interrupt counters, beginning from the "first counter No." which is designated. If C3 is designated as the first interrupt counter No., numbers C3 to C555 will be allocated for interrupt counters. C3 C31 C32 I I1 I2 Interrupt counter (127 points) C555 I127 Values corresponding to the interrupt counter No. (b) In order to use an interrupt counter, an "interruption permitted" status must be established by E1 instruction at the main routine program

206 1 DEVICES (4) Precautions (a) One interrupt pointer is insufficient to execute interrupt counter and interrupt program operation. Moreover, an interrupt program cannot be executed by an interrupt counter setting designated in the PLC system settings in the PLC parameter setting. (b) (c) (d) If the processing items shown below are in progress when an interruption occurs, the counting operation will be delayed until processing of these items is completed. The count processing starts after the execution of program is completed. Even if the same interruption occurs again while processing of these items is in process, only one interruption will be counted. During execution of sequence program instructions During interrupt program execution During execution of a fixed scan execution type program The maximum counting speed of the interrupt timer is determined by the longest processing time of the items shown below. Instruction with the longest processing time among the instructions used in the program Interrupt program processing time The processing time of a fixed scan execution type program The use of too many interrupt counters will increase the sequence program processing time, and may cause a "WDT ERROR". If this occurs, either reduce the number of interrupt counters, or reduce the counting speed for the input pulse signal. (e) The interrupt counter's count value can be reset by using the RST C instruction in the sequence program prior to the FEND instruction. (f) The interrupt counter's count value can be read out by using the sequence program MOV instruction

207 1 DEVICES Data registers (D) (1) Definition (a) (b) Dn Data registers are memory devices which store numeric data ( to 32767, or H to FFFFH). Data registers consist of 16 bits per point, with reading and writing executed in 16-bit units. b15 b (c) If the data registers are used for 32-bit instructions, the data will be stored in registers Dn and Dn + 1. The lower 16 bits of data are stored at the data register No. (Dn) designated in the sequence program, and the higher 16 bits of data are stored in the designated register No. + 1 (Dn + 1). For example, when D12 is specified in the DMOV instruction, the lower 16 bits are stored into D12 and the upper 16 bits are stored into D13. DMOV K5 D12 Processing object: D12, D13 D13 D12 Upper 16 bits Lower 16 bits Two data registers can store a range of numeric data from to or from H to FFFFFFFFH. (d) Data stored by the sequence program is maintained until another data save operation occurs

208 1 DEVICES Link registers (W) (1) Definition (a) A link register is the Basic model QCPU memory used to refresh the Basic model QCPU with data from the link registers (LW) of intelligent function modules including MELSECNET/H network module. Link registers are used to store numeric data ( to 32767, or H to FFFFH). Basic model QCPU MELSECNET/H network module Link register Link register W Link refresh LW Link refresh setting range (b) Wn When used outside the MELSECNET/H network system's range, link registers can serve as data registers. Link registers consist of 16 bits per point, with reading and writing executed in 16-bit modules. b15 b (c) If the link registers are used for 32-bit instructions, the data is stored in registers Wn and Wn + 1. The lower 16 bits of data are stored in the link register No. (Wn) designated in the sequence program, and the higher 16 bits of data are stored in the designated register No. + 1 (Wn + 1). For example, if link register W12 is designated at the DMOV instruction, the lower 16 bits are stored in W12, and the upper 16 bits are stored in W13. DMOV K5 W12 Processing object: W12, W13 W13 W12 Upper 16 bits Lower 16 bits In two link register points, to or H to FFFFFFFFH data can be stored. (d) Data stored by the sequence program is maintained until another data save operation occurs. REMARK The MELSECNET/H network module has link register points. The Basic model QCPU has 248 link register points. When subsequent points after Point 248 are used for link registers, change a "number of points" setting of link registers on the Device sheet of the PLC Parameter dialog box

209 1 DEVICES (2) Using link registers in a network system In order to use link registers in the network system, network parameter settings must be made. Link registers not set in the network parameter settings can be used as data registers. REMARK Special link registers (SW) 1) For details regarding network parameters, refer to the Q Corresponding MELSECNET/H Network System Reference Manual. (1) Definition (a) Special link registers are used to store data on the communication status and errors of an intelligent function (b) Because the data link information is stored as numeric data, the special link registers serve as a tool for identifying the locations and causes of faults. (2) Number of special link register points There are 124 special link register points from SW to SW3FF. The special link register points are assigned at the rate of 512 points per intelligent function module, such as a MELSECNET/H network module. REMARK For details regarding special link registers used in the Basic model QCPU, refer to the QCPU(Q mode)/qnacpu Programming Manual (Common Instructions)

210 1 DEVICES 1.3 Internal System Devices Internal system devices are devices used for system operations. The allocations and sizes of internal system devices are fixed, and cannot be changed by the user Function devices (FX, FY, FD) (1) Definition (a) Function devices are used in a sub-routine program with arguments to perform write/read of data between the sub-routine call source with argument and the sub-routine program with argument. Example If FX and FD1 are used at the sub-routine program, and if M and D are designated by the sub-routine CALL instruction, the M ON/OFF data is transferred to FX, and the D data is transferred to FD1. [Sub-routine program CALL source] [Sub-routine program] X CALL P M D P FX MOV FD1 R RET (b) Because the function devices used for each sub-routine program CALL source can be set, the same sub-routine program can be used without regard to other sub-routine CALL sources. (2) Types of function devices There are 3 function device types: function input devices (FX), function output devices (FY), and function register devices (FD). (a) Function input devices (FX) These devices are used to designate inputs of ON/OFF data to a subroutine program. In the sub-routine program, these devices are used for reading and processing bit data designated by sub-routine with argument CALL instruction. All the Basic model QCPU bit data designation devices can be used. (b) Function output devices (FY) These devices are used to designate outputs of sub-routine program operation results (ON/OFF data) to the sub-routine program CALL source. At sub-routine program with arguments, the operation results are stored at the designated device. All bit data designation devices except Basic model QCPU inputs (X, DX) can be used

211 1 DEVICES (c) Function registers Function registers are used to perform write/read of data between the subroutine call source and the sub-routine program. The function register input/output condition is automatically determined by the Basic model QCPU. If the sub-routine program data is the source data, the data is designated as sub-routine input data. If the sub-routine program data is the destination data, the data is designated as sub-routine output data. 1 point occupies 4 words. The number of words used depends on an instruction in a sub-routine program. A one-word instruction requires 1 word. CALLP P D P MOV R FD A two-work instruction requires 2 words. The data is stored in one point (D). CALLP P D P DMOV R FD The data is stored in two points (D and D1). The destination of 32-bit multiplication/division operation requires 4 words. CALLP P D P D R R1 FD The data is stored in four points (D to D3). Active devices cannot be used in a sub-routine program that contains arguments. If devices assigned for function registers are used, values of the function registers will not properly be returned to a calling program. CALLP P D P D R R1 FD MOV K D3 Since the points (D to D3) are used for FD, D3 can not be used for the sub-routine program. Basic model QCPU's word data devices can be used. REMARK 1) For a procedure for using function devices, see the QCPU (Q Mode)/QnACPU Programming Manual (Common Instructions)

212 1 DEVICES Special relays (SM) (1) Definition (a) A special relay is used to store High Performance model QCPU status data. (2) Special relay classifications Special relays are classified according to their applications, as shown below. (a) For fault diagnosis : SM to SM99 (b) For serial communication function : SM1 to SM129 (c) System information (d) System clock/system counter (e) Scan information (f) Memory card information (g) Instruction related : SM2 to SM399 : SM4 to SM499 : SM5 to SM599 : SM6 to SM699 : SM7 to SM799 REMARK 1) For details regarding special relays which can be used by the Basic model QCPU, refer to Appendix

213 1 DEVICES Special registers (SD) (1) Definition (a) A special register is used to store Basic model QCPU status data (diagnosis and system information). (2) Special register classifications Special registers are classified according to their applications, as shown below. (a) For fault diagnosis : SD to SD99 (b) For serial communication function : SM1 to SM129 (c) Fuse-blown module : SD13 to SD149 (d) Check of input/output modules : SD15 to SD199 (e) System information : SD2 to SD399 (f) System clock/system counter : SD4 to SD499 (g) Scan information : SD5 to SD599 (h) Memory card information : SD6 to SD699 (i) Instruction related : SD7 to SD799 REMARK 1) For details regarding special relays which can be used by the Basic model QCPU, refer to Appendix

214 1 DEVICES 1.4 Link Direct Devices (J \ ) (1) Definition (a) (b) At END processing, a data refresh (data transfer) operation occurs between the Basic model QCPU and the MELSECNET/H network system modules. Link direct devices are used at that time to directly access the link devices in the MELSECNET/H network modules. Designation method Link direct devices are designated by network No. and device No. Designation method: J \ Device No. Input...X Output...Y Link relay... B Link register...w Link special relay...sb Link special register..sw Network No.(1 to 239) For link register 1 (W1) of network No.2, the designation would be "J2\W1" MOVP K1 J2W1 Network modules at network No.2 W W1 For a bit device (X, Y, B, SB), digit designation is necessary. Designation example : J1\K1X, J1\K4B (2) Designation range Link direct device designations are possible for all the link devices in network modules. Device outside the range specified by the network refresh parameters can also be designated. (a) Writing 1) Writing is executed within that part of the link device range set as the send range in the common parameters of the network parameters that is outside the range specified as the "refresh range" in the network refresh parameters. Basic model QCPU Network module B Refresh range LB Link range send range Writing range

215 1 DEVICES 2) Although writing is also possible in the "refresh range" portion of the link device range (specified by the refresh parameters), the link module's link device data will be rewritten when a refresh operation occurs. Therefore, when writing by link direct device, the same data should also be written to the Basic model QCPU related devices designated by the refresh parameters. [Refresh parameter settings] Network No. : 1 Basic model QCPU(W to W3F) Network module (LW to LW3F) [Sequence program] MOV K1 W1 "1" is written to link module LW1 when a refresh occurs. [Writing timing] MOV W1 Basic model QCPU J1\W1 "1" is written to link module LW1 when the MOV instruction is executed. Network module MOV K1 W1 MOV W1 J1\W1 Writing at instruction execution W W1 LW1 Writing at instruction execution Writing at refresh operation 3) When data is written to another station's writing range using a link direct device, the data which is received from that station will replace the written data. (b) Reading Reading by link direct device is possible in the entire link device range of network modules

216 1 DEVICES (3) Differences between "link direct devices" and "link refresh" The differences between "link direct devices" and "link refresh" are shown in Table 1.4 below. Table 1.4 Differences Between "Link Direct Devices" and "Link Refresh" Item Link Direct Device Link Refresh Link relay J \K4B or later B or later Program Link register J \W or later W or later notation Link special relay J \K4SB or later SB or later method Link special register J \SW or later SW or later Number of steps 2 steps 1 step Network module access range All network module link Refresh parameter devices designated range Access data guarantee range Word units (16 bits) REMARK 1) For details regarding the MELSECNET/H network system, refer to the For Q MELSECNET/H Network System Reference Manual. 2) For details regarding network parameters, common parameters, and network refresh parameters, refer to the following manuals: Detailed information : Q Corresponding MELSECNET/H Network System Reference Manual Setting procedures : GX Developer Operating Manual, Windows Version

217 1 DEVICES 1.5 Intelligent Function Module Devices (U \G ) (1) Definition (a) The intelligent function module devices allow the Basic model QCPU to directly access the buffer memories of intelligent function modules which are installed at the base unit. (b) Intelligent function module devices are designated by the intelligent function module input/ output No., and the buffer memory address. Designation method: U \G Buffer memory address (setting range: to16383 (decimal)) 1 Intelligent function module/special function module I/O No. Setting: If the input/output No. is a 3-digit value, designate the first 2 digits. For X/YF...X/Y1F Designate "1F" Setting range: QJCPU: H to FH Q/Q1CPU: H to 3FH When digital output values of channels (CH.1 to CH.4) of the Q64AD Type Analog-Digital Conversion Module (X/Y to X/YF) installed in Slot of the main base unit are stored in D to D3, the output/input number and the buffer memory address are specified as shown below. BMOV U\G11 D K4 Q64AD CH.1 Digital output value CH.2 Digital output value CH.3 Digital output value CH.4 Digital output value (2) Processing speed The processing speed for intelligent function module devices is; (a) (b) Read/write from/to the buffer memory of the intelligent function module is slightly faster than the "processing speed of FROM/TO instruction". (For example, "MOV U\G11 D") When using a single instruction to perform read from the buffer memory of the intelligent function module and another processing, use the sum of "processing speed of FROM/TO instruction" and "processing speed of instruction" as a guideline. (For example, "+ U\G11 D D1") If the same buffer memory of the same intelligent function module is used two or more times in a sequence program, the processing speed can be increased by using the FROM instruction to read that buffer memory data to a Basic model QCPU device. REMARK 1) 1: For details regarding buffer memory addresses and applications, refer to the manual for the intelligent function module in question

218 1 DEVICES 1.6 Index Registers (Z) (1) Definition (a) Index registers are used in the sequence program for indirect setting (index qualification) designations. An index register point is used for index modification. X MOVP K5 Z SM4 BCD DZ K4Y3 Index registers consist of 16 bits per point. (b) (c) There are 1 index registers (Z to Z9). Index registers consist of 16 bits per point, with reading and writing occurring in 16-bit modules. Zn b15 b (d) If the index registers are used for 32-bit instructions, the data is stored in registers Zn and Zn +1. The lower 16 bits of data are stored in the index register No. (Zn) designated in the sequence program, and the upper 16 bits of data are stored in the designated index register No For example, if register Z2 is designated in the DMOV instruction, the lower 16 bits are stored in Z2, and the upper 16 bits are stored at Z3. DMOV D Z2 Processing object: Z2, Z3 Z3 Z2 Upper 16 bits Lower 16 bits REMARK For index modification using the index register, refer to the following manual. QCPU (Q mode) / QnACPU Programming Manual (Common instructions)

219 1 DEVICES Switching between main routine/sub-routine program and interrupt program The following processing is performed at the time of switching between main routine/sub-routine program and interrupt program. Index register (Z to Z9) value is saved (protected)/restored. File register block No. is saved (protected)/restored. For the index register (Z to Z9), whether its value is saved (protected)/restored or not saved at the time of switching between the main routine/sub-routine program and interrupt program can be selected in the PLC system setting of the PLC parameter dialog box. If you do not want to write date onto index registers when using an interrupt program, turn on the "High speed execution" check box in the "Interrupt program fixed program setting" section of the PLC System sheet in the PLC Parameter dialog box. This will enable you to switch between program quickly. (1) Index register processing (a) When "High-speed execution" is not selected 1) When the main routine/sub-routine program is switched to the interrupt program, the main routine/sub-routine program's index register value is first saved, and is then transferred to the interrupt program. Executed program Index register value 2) The saved index register (Z to Z9) value is restored at the time of switching from the interrupt program to the main routine/sub-routine program. Main routine/ sub-routine program Z=1 Saved Switching Transferred Interrupt program Z=1 to Z=3 Reset Main routine/ sub-routine program Z=1 Reset Index register storage area Z= Z=1 Z=1 Z=1 Z=1 : For interrupt program, Z is changed to 3. Word devices should be used to transfer index register data from an interrupt to a main routine/sub-routine program

220 1 DEVICES (b) When the "High-speed execution" check box is ON: 1) The index register (Z to Z9) value is saved/restored at the time of switching from the main routine/sub-routine program to the interrupt program. 2) If data is written onto index registers by using an interrupt program, the values of index registers used for an main routine/sub-routine program will be corrupted. Executed program Main routine/ sub-routine program Switching Interrupt program Reset Main routine/ sub-routine program Index register value Z=1 Z=1 to Z=3 Transferred Transferred Z=3 Index register storage area Z= Z= Z= Z= Z= : For interrupt program, Z is changed to 3. (c) Before writing data onto index registers by using an interrupt program, use the ZPUSH/ZPOP instruction to save/restore the data. I SM4 ZPUSH D The points after D store the data (Z to Z9). SM4 ZPOP D IRET The data after D is stored in points (Z to Z9)

221 1 DEVICES (b) (2) File register block No. processing (a) At the time of switching from the main routine/sub-routine program to the interrupt program, the block No. of the file register in the main routine/subroutine program is saved and then transferred to the interrupt program. At the time of switching from the interrupt program to the main routine/subroutine program, the saved block No. of the file register is restored. Executed program Main routine/ sub- routine program Switching Interrupt program Restored Main routine/ sub- routine program Block No. of file register Block 1 saved Transferred [RSET K] : Block 1 Block 1 Restored Save area Block Block 1 Block 1 Block 1 Block

222 1 DEVICES 1.7 File Registers (R) (1) Definition (a) File registers are expansion devices for data registers. (b) File register data is stored in files in the CPU standard RAM. 1) The standard RAM has 32k points assigned for file registers. File registers can be used at the same processing speed as data registers. MOV K1 R2 "1" is written to R2. R R1 R2 Standard RAM File register (c) File registers consist of 16 bits per point, with reading and writing occurring in 16-bit modules. b15 b Rn (d) If the file registers are used for 32-bit instructions, the data will be stored in registers Rn and Rn + 1. The lower 16 bits of data are stored in the file register No. (Rn) designated in the sequence program, and the upper 16 bits of data are stored in the designated file register No.+ 1. For example, if file register R2 is designated in the DMOV instruction, the lower 16 bits are stored in R2, and the upper 16 bits are stored in R3. DMOV D R2 Processing object: R2, R3 R3 R2 Upper 16 bits Lower 16 bits Two file registers can be used to store numeric data from to or from H to FFFFFFFFH. (e) The content of the file register is retained even when the power is turned off or reset. (It is not initialized even if latch clear is conducted.) To initialize the file register contents, perform data clear operation in a sequence program or using GX Developer Example: To clear R - R999 FMOV K R K1 When using GX Developer, select file register all clear in the PLC memory clear of the Online dialog box to clear the data

223 1 DEVICES (2) File register specifying method (a) Block switching method In the block switching method, specify the number of used file register points in units of 32k points (R to R32767). When multiple blocks are being used, specify the file registers by switching to the block No. to be used with the RSET instruction. Specify each block as R to R RSET K1 Specifying R for block 1 Standard RAM R MOV D R Block R32767 R Block 1 R32767 (b) Serial number access method In the serial number access method, specify the file registers beyond 32k points with consecutive device numbers. The file registers of multiple blocks can be used as consecutive file registers. Use "ZR" as the device name. Standard RAM MOV D ZR32768 ZR ZR32767 ZR32768 (Block ) ZR65535 (Block 1) (3) Precautions for use of file registers Performing write/read to/from 64k or more points of file register numbers will not result in an error. However, note that undefined data will be stored when read from file registers is performed. POINT The file registers cannot be deleted by performing PLC data deletion in the Online dialog box. They cannot be formatted, either

224 1 DEVICES 1.8 Nesting (N) (1) Definition Nesting devices are used to nest MC or MCR master control instructions when programming operating conditions. (2) Designation method with master control The master control instructions are used to open and close the ladders' common bus so that switching of ladders may be executed efficiently by the sequence program. Nesting devices must be numbered in descending order (from N to N7) of nested relation. For details on how to use master control, refer to the QCPU(Q mode)/qnacpu Programming Manual (Common Instructions). N M15 A MC N M15 Designated in ascending No. order N1 M16 B MC N1 M16 Executed when condition "A" is satisfied. N nesting control range N1 nesting control range N2 nesting control range N2 M17 C MC N2 MCR M17 N2 Executed when conditions "A" and "B" are satisfied. Designated in descending No. order Executed when condition " A", "B" and "C" are satisfied. MC2 to 7 are reset. MCR N1 Executed when conditions "A" and "B" are satisfied. MC1 to 7 are reset. MC N Executed when condition "A" is satisfied. MC to 7 are reset. Executed regardless of A, B, C condition statuses

225 1 DEVICES 1.9 Pointers (1) Definition Pointer devices are used in jump instructions (CJ, SCJ, JUMP) or sub-routine call instructions (CALL, ECALL). A total of 3 pointers can be used. (2) Pointer applications (a) Pointers are used in jump instructions (CJ, SCJ, JMP) to designate jump destinations and labels (jump destination beginning). (b) Pointers are used in sub-routine CALL instructions (CALL, CALLP) to designate the CALL destination and label (sub-routine beginning). MAIN CALL P FEND P RET END REMARK For further information on jump instructions and sub-routine call instructions, see the QCPU (Q Mode)/QnACPU Programming Manual (Common Instructions)

226 1 DEVICES 1.1 Interrupt Pointers (I) (1) Definition (a) Interrupt pointers are used as labels at the beginning of interrupt program. Interrupt pointer (interrupt program label) I IRET Interrupt program (b) A total of 128 interrupt points (I to I127) can be used. (2) Interrupt pointer No. and interrupt factor (a) As shown below, there are two types of interrupt factor. I to I15...Interrupt input from the QI6 interrupt module. I28 to I31...Fixed cycle interruption by the internal timer of the Basic model QCPU. I5 to I127...Interruption from the intelligent function module/interrupt module. 1 REMARK 1: To use the interruption from the intelligent function module/interrupt module, the intelligent function module setting (interrupt pointer setting) must be made in the PLC system setting of the PLC parameter dialog box. (Refer to Section for the interruption from the intelligent function module.)

227 1 DEVICES (b) A list of interrupt pointer Nos. and interrupt factors is given in Table 1.5 below. Table 1.5 List of Interrupt Pointer Nos. and Interrupt Factors I No. Interrupt Factors Priority I 1st point 5 I1 2nd point 6 I2 3rd point 7 I3 4th point 8 I4 5th point 9 I5 6th point 1 I6 7th point 11 I7 QI6 interrupt 8th point 12 I8 module factor 9th point 13 I9 1th point 14 I1 11th point 15 I11 12th point 16 I12 13th point 17 I13 14th point 18 I14 15th point 19 I15 I16 to I27 16th point 2 Unusable I28 1ms 4 I29 4ms 3 Internal timer factor I3 2ms 2 I31 1ms 1 I32 to I49 Unusable I5 to I127 2 Interruption by intelligent function module/qi6 Set in the parameter which intelligent function module/interrupt module (QI6) will be used. 21 to 98 REMARK 1 : The internal times shown are the default setting times. These times can be designated in 1 ms units through a 2 ms to 1 ms range by the PLC system settings in the PLC parameter setting. 2 : The intelligent function module setting (interrupt pointer setting) must be made in the PLC system setting of the PLC parameter dialog box. (Refer to Section for the interruption from the intelligent function module.)

228 1 DEVICES 1.11 Other Devices SFC block device (BL) The SFC block device is used to check whether the specified block of an SFC program is active or not. Refer to the following manual for the SFC block device using method. QCPU (Q mode)/qnacpu Programming Manual (SFC) Network No. designation device (J) (1) Definition The network No. designation device is used to designate the network No. in data link instructions. (2) Designating network No. designation device The network No. designation device is designated in the data link instruction as shown below. JP.READ Jn S1 S2 S3 D Network No. designation device (n: network No.) Instruction name Network No. designation instruction REMARK I/O No. designation device (U) For details regarding data link instructions, refer to the Q Corresponding MELSECNET/H Network System Reference Manual. (1) Definition I/O No. designation devices are used with intelligent function module instruction module instructions to designate I/O numbers. (2) Designating the I/O No. designation device I/O No. designation devices are designated with the intelligent function module instructions as shown below. GP.READ Un S1 S2 S3 D I/O No. designation device (n: I/O No.) Instruction name I/O No. designation instruction REMARK For details regarding intelligent function module instructions, refer to the corresponding manual for the intelligent function module to be used

229 1 DEVICES Macro instruction argument device (VD) (1) Definition Macro instruction argument devices are used with ladders registered as macros. When a VD setting is designated for a ladder registered as a macro, conversion to the designated device occurs when the macro instruction is executed. (2) Designating macro instruction argument devices Macro instruction argument devices are designated for those devices set as VD in ladders registered as macro instructions in macro registration at a peripheral device. When using macro instructions in a sequence program, designate devices to correspond to the instruction argument devices used with the ladders registered as macros, in ascending order. Sequence program Ladder registered as a macro (registration name: MAX) M.MAX D D1 R Transfer to VD2 > VD VD1 MOV VD VD2 Transfer to VD1 Transfer to VD Name of ladder registered as a macro <= VD VD1 MOV VD1 VD2 Actual sequence program executed at QCPU > D D1 MOV D R <= D D1 MOV D1 R REMARK 1) : With the macro instruction argument device, VD to VD9 can be used in one ladder registered as a macro instruction. 2) The GX Developer read mode provides an option to view a program in macro instruction format. (Choose "View" - "Macro Instruction format display" to view macro instructions.) Change of macro instruction display

230 1 DEVICES 1.12 Constants Decimal constants (K) Hexadecimal constants (H) Real number (E) (1) Definition Decimal constants are devices which designate decimal data in sequence program. They are designated as "K "settings (e.g. K1234), and are stored in the Basic model QCPU in binary (BIN) code. See Section for details regarding binary code. (2) Designation range The designation ranges for decimal constants are as follows. For word data (16 bits)...k to K32767 For 2-word data (32 bits)...k to K (1) Definition Hexadecimal constants are devices which designate hexadecimal or BCD data in sequence program. (For BCD data designations, to 9 digit designations are used.) Hexadecimal constants are designated as "H " settings (e.g. H1234). See Section for details regarding hexadecimal code. (2) Designation range The designation ranges for hexadecimal constants are as follows. For word data (16 bits)... H to HFFFF (H to H9999 for BCD) For 2-word data (32 bits)... H to HFFFFFFFF (H to H for BCD) (1) Definition Real numbers are devices that designate real numbers in a sequence program. Specify it in the form of E (example: E1.234). X1 EMOVP E1.234 D Refer to Section for details of the real numbers. (2) Designation range The setting ranges for real numbers are absolute value

231 1 DEVICES (3) Designation method In a sequence program, real numbers can be designated in two ways: "normal representation" and "exponential representation". Normal representation...designate the value to be set unchanged. For example, specify as E Exponential representation...designate the value to be set in the form of (value) 1 n. For example, specify 1234 as E REMARK 1: +3 in E indicates Character string ( " " ) (1) Definition Character string constants are devices used to designate character strings in sequence program. They are designated by quotation marks (e.g. "ABCD1234"). (2) Usable characters All ASCII code characters can be used in character strings. The Basic model QCPU is sensitive to uppercase and lowercase characters. (3) Number of designated characters Character strings extend from the designated character to the NUL code (H). You can use up to 32 characters for a character string in an instruction such as $MOV. POINT Character strings may be used with only the $MOV instruction

232 1 DEVICES 1.13 Useful Method of Using the Devices Device initial value Using the device initial value, the Basic model QCPU can set data to the devices and intelligent function module without any program. (1) Definition (a) The device initial value is a method of registering the data used in a program to the device or intelligent function module buffer memory without any program. Use of the device initial value allows omission of the program that will set data to devices in the initial processing program. [Data setting by initial program] SM42 MOV H1 MOV H22 D D1 Power ON/STOP/ RESET RUN Device memory Device initial value At power ON, at reset, at STOP RUN Device memory (b) To use the device initial value, the device initial value data created beforehand using GX Developer must have been stored into the program memory of the Basic model QCPU as a device initial value file. The Basic model QCPU writes the data of the specified device initial value file to the specified device or intelligent function module buffer memory at power on or at the time of switching from the STOP status to the RUN status. Basic model QCPU GX Developer Program memory Device initial value range setting Device initial value write Device initial value file Device initial value write (At power ON, at reset, at STOP RUN) Specified device Device initial value data setting Intelligent function module

233 1 DEVICES (c) The following devices can use the device initial value. 1) Timer's current value (T) 7) Special link register (SW) 2) Retentive timer's current value (ST) 8) File register (R to R32767) 3) Counter's current value (C) 9) File register (ZR to ZR65535) 4) Data register (D) 5) Special register (SD) 1) Intelligent function module device (U \G ) 6) Link register (W) 11) Link direct device (J \W, J \SW ) (2) Procedure for using the device initial value (a) (b) [Device initial value range setting screen] Set the device initial value ranges on the "Device initial value range setting screen". Set the device initial value data in the device initial value ranges on the "Device memory editing screen". [Device memory editing screen] (c) Set "Use" for the device initial value in the PLC file setting of the PLC parameter dialog box. [PLC file setting screen] (d) Write to the Basic model QCPU the device initial values and parameter set using GX Developer

234 1 DEVICES (3) Precautions for use of the device initial value (a) (b) (c) When the device initial value and latch range overlap, the device initial value has priority. Hence, the data in the latch range are also changed into the device initial value data at power on. The device initial value cannot be used for the area that is not desired to be set at switching from STOP to RUN (data that will be set at power on and changed in the program). In the main routine program, create a program that will set data to the specified device with the MOV instruction, etc. For the intelligent function module, use the TO instruction to write data to the buffer memory. When specifying the following devices in the device initial value range setting, make "Module synchronization setting" in the PLC system setting of the PLC parameter dialog box. If the module synchronization setting is not made, the device initial values may not be set to the target module properly. Intelligent function module device (U\G) Link direct device (J\W, J\SW) REMARK Refer to the GX Developer Operating Manual for the device initial value range setting, the device initial value data setting operation, and the operation for writing the device initial values to the Basic model QCPU

235 11 PROCESSING TIMES OF THE BASIC MODEL QCPU PROCESSING TIMES OF THE BASIC MODEL QCPU This chapter describes the concept of the processing times of the Basic model QCPU Scan Time Structure In the RUN status, the Basic model QCPU performs the following processings cyclically. Processing in RUN status Sequence program check I/O refresh (1) I/O refresh time END processing of DUTY instruction (No processing when the DUTY instruction is not executed) (2) Processing time for instruction processed at END Sequence program execution (3) Instruction execution time Has the sequence program ended? NO YES MELSECNET/H refresh CC-Link refresh (4) Module refresh time Refresh based on the intelligent function module parameters set using GX Configurator Scan time Calendar update processing (No processing when the update command is not given) Error cancel (No processing when the cancel command is not given) (5) Execution times of various functions processed at END Service processing (6) Service processing time Constant wait processing (No processing when there is no setting) STOP/PAUSE status STOP/PAUSE processing WDT reset Scan time calculation Operating status judgment RUN status Hardware, system information check (update) (7) Common processing time Numerals in parentheses indicate the item numbers in Section

236 11 PROCESSING TIMES OF THE BASIC MODEL QCPU 11.2 Concept of Scan Time The scan time varies with the following elements. Number of I/O points Processing times of all instructions executed within one scan Sum of processing times of user interrupt program executed within one scan Processing for instruction processed at END Execution of various functions processed at END Module refreshes (e.g. refreshes made by MELSECNET/H, CC-Link, etc.) Service processing Constant scan setting (parameter setting) 11 The scan time is the sum of the following processing times. (1) I/O refresh time (a) Refresh time of I/O data transferred from/to the following modules installed on the main base unit, slim type main base unit or extension base unit of the Basic model QCPU. Input module Output module Intelligent function module (b) Calculate the I/O refresh time with the following expression. (I/O refresh time) = (number of input refresh points) N1 + (number of output refresh points) N2 Refer to the following table for N1 and N2. N1 Main base unit Main base unit CPU Module Extension base Extension base /slim type main /slim type main unit unit base unit base unit QJCPU 2.5 s 2.95 s 1.25 s 2.2 s QCPU 2. s 2.75 s 1.2 s 2.5 s Q1CPU 1.95 s 2.7 s 1.15 s 2. s (2) Processing time for instruction processed at END (a) DUTY instruction Time when the user timing clock (SM42 to SM424) specified for the DUTY instruction is turned on/off at END processing CPU Type N2 END Processing Time (ms) QJCPU QCPU Q1CPU

237 11 PROCESSING TIMES OF THE BASIC MODEL QCPU (3) Instruction execution time (a) Sum of the processing times of the instructions used in the program executed by the Basic model QCPU. Refer to the following manual for the processing times of the corresponding instructions. QCPU (Q Mode)/QnACPU Programming Manual (Common Instructions) QCPU (Q Mode)/QnACPU Programming Manual (SFC) (b) An interrupt program has an overhead time at the start of interrupt program and an overhead time at the end of interrupt program. Add an overhead time at the start of interrupt program and an overhead time at the end of interrupt program to the instruction execution time. 1) Overhead time at the start of interrupt program (B1) Cyclic Interrupt (I28 to I31) Interrupt Processing from QI6 CPU Type Processing (I to I15) 1 Without rapid start With rapid start Without rapid start With rapid start QJCPU QCPU Q1CPU : The values assume that the QI6 is installed on slot of the main base unit. 2) Overhead time at the end of interrupt program (B2) CPU Type Without rapid start With rapid start QJCPU QCPU Q1CPU (4) Module refresh time (a) Refresh of MELSECNET/H Refresh time between the Basic model QCPU and MELSECNET/H network module. Refer to the following manual for the refresh time of the MELSECNET/H. Q Corresponding MELSECNET/H Network System Reference Manual (b) Automatic refresh of CC-Link Refresh time between the Basic model QCPU and CC-Link master/local module. Refer to the following manual for the automatic refresh time of CC-Link. Control & Communication Link System Master/Local Module User's Manual (c) Intelligent utility package (Intelligent automatic refresh) 1) Refresh time between the intelligent function module and CPU module, which is designated on Auto refresh setting screen of the utility package for the intelligent function module. 2) Calculate the intelligent automatic refresh time with the following expression. (Refresh time) = KN1 + KN2 (number of refresh points)

238 11 PROCESSING TIMES OF THE BASIC MODEL QCPU 3) As KN1 and KN2, use the values in the following table. When the intelligent module is installed on the main base unit CPU Type KN1 ( 1-3 ms) KN2 ( 1-3 ms) QJCPU QCPU Q1CPU When the intelligent module is installed on the expansion base unit CPU Type KN1 ( 1-3 ms) KN2 ( 1-3 ms) QJCPU QCPU Q1CPU (Example) When the number of automatic refresh points is 4 for the analog-digital converter module (Q64AD) (when installed on the main base unit of Q1CPU).249 (ms) = (5) Execution times of various functions processed at END (a) Calendar update processing time 1) Time to write the clock data stored in SD21 to SD213 to the clock element at END processing when a clock data set request is given (SM21 turns from OFF to ON). 2) Time to read the clock data to SD21 to SD213 at END processing when a clock data read request is given (SM213 turns ON). CPU Type At clock data set request END Processing Time (ms) At clock data read request QJCPU.12.4 QCPU.11.3 Q1CPU.1.2 (b) Error cancel processing Time to cancel the continuation error stored in SD5 on the leading edge of SM5 (error cancel) (when it turns from OFF to ON). CPU Type Common Processing Time (ms) Annunciator Other error QJCPU.17.1 QCPU.14.9 Q1CPU

239 11 PROCESSING TIMES OF THE BASIC MODEL QCPU (6) Service processing time (a) Monitoring using GX Developer Processing time (unit: ms) for monitoring using GX Developer. Added when monitoring is performed on GX Developer. When Connected to RS-232 of Host CPU Function Module When Connected to Other Station 4 QJCPU QCPU Q1CPU QJCPU QCPU Q1CPU Read of program from PLC Device monitor Online program correction : Time taken to read an 8k-step program from program memory 2: Time taken when 32 points have been set in registration monitor 3: Time taken when a 1-step ladder has been added 4: Indicates that access is made via MELSECNET/H, Ethernet, CC-Link or serial communication module Other Processing Times CPU Type (b) Communication with serial communication module or Ethernet interface module Time to make communication with the serial communication module or Ethernet interface module. Refer to the following manual for communication time with the corresponding module. Q-Corresponding MELSEC Communication Protocol Reference Manual (7) Common processing time Common processing time of the CPU module processed in the system. The common processing times are the values in the following table. CPU Type QJCPU QCPU Q1CPU Common processing time (ms) The processing times in the above table assume that the constant scan function is not used. When the constant scan function is used, wait processing is performed for the period of constant scan setting shortage. (1) Constant scan accuracy Without Monitor, With Monitor, Without Without User Interrupt User Interrupt QJCPU.2.9 QCPU.12.6 Q1CPU.1.5 Without Monitor, With User Interrupt Interrupt program execution time (Refer to (b) in Section 11.2 (3).) With Monitor, With User Interrupt Sum of the following times 1) Time indicated in "With Monitor, Without User Interrupt" field on the left 2) Sum of interrupt program execution times Unit: ms With monitor: Indicates the status in which monitor is being performed with GX Developer connected or communication with the external device is being made using the serial communication function. Without monitor: Indicates the status in which communication using GX Developer or the serial communication function is not being made

240 12 PROCEDURE FOR WRITING PROGRAMS TO BASIC MODEL QCPU 12 PROCEDURE FOR WRITING PROGRAM TO BASIC MODEL QCPU This chapter describes the procedure for writing program created at the GX Developer to the Basic model QCPU Items to Consider when Creating Program To create a program with the Basic model QCPU, the program capacity, the number of device points used, etc. must be determined in advance. 12 (1) Program size considerations Examine whether programs and parameters can be stored within the program capacity executable in the used CPU module. The program capacities of the CPUs are shown below: QJCPU : 8 k steps QCPU : 8 k steps Q1CPU : 14 k steps (2) Applications of devices and setting of their numbers of points Consider the applications of the devices used in a program and their number of points. Refer to Chapter 1 for the devices usable with the Basic model QCPU. (3) ROM operation considerations When performing ROM operation, make the boot file setting of PLC parameter. (4) Device initial value setting Set the data necessary as initial values to the device memory of the Basic model QCPU and the buffer memory of the intelligent function module. Refer to Section for details

241 12 PROCEDURE FOR WRITING PROGRAMS TO BASIC MODEL QCPU 12.2 Procedure for writing program to the Basic model QCPU The procedure for writing program and parameter created at the GX Developer to the Basic model QCPU standard ROM is shown below. 12 Procedural steps shown in boxes are performed at the GX Developer, and those shown in boxes are performed in the Basic model QCPU. START Start GX Developer. Refer to the GX Developer manual. Set the project. NO Do you change the number of device points used? YES Refer to Section 1.2. Device setting screen Change the number of device points in device setting of PLC parameter. NO Do you perform boot operation? YES Boot file setting screen Select "boot from standard ROM" in boot file setting of PLC parameter. Create a program to be executed in the CPU module. Ladder setting screen 1) When the parameters and program are to be written to the program memory of the Basic model QCPU, the operation marked " " in the above procedure is unnecessary

242 12 PROCEDURE FOR WRITING PROGRAMS TO BASIC MODEL QCPU 1) NO Is device initial value used? Refer to Section YES Set device memory. Set device initial value ranges. Connect GX Developer and CPU module. Refer to the GX Developer manual. Move the RUN/STOP/RESET switch of the CPU module to the STOP position and switch power on. ERR. LED is lit. Write to PLC screen Select "Program memory" in write to PLC of the Online dialog box on GX Developer, and write parameters, created program and device initial values to program memory. Write the program memory to ROM in online write to PLC (flash ROM) of GX Developer to write the program memory data to the standard ROM. Write program memory to ROM screen Make a reset with the RUN/ STOP/RESET switch of the CPU module. Refer to the following manual and make a reset. QCPU (Q Mode) User's Manual (Hardware) Basic Model QCPU (Q Mode) User's Manual (Hardware Setting, Maintenance and Inspection) END When the parameters and program are to be written to the program memory of the Basic model QCPU, the operation marked " " in the above procedure is unnecessary

243 13 OUTLINE OF MULTIPLE CPU SYSTEMS 13 OUTLINE OF MULTIPLE CPU SYSTEMS 13.1 Features 13 (1) Multi control The optimum system can be configured to meet the control target by using the three CPU modules of Basic model QCPU, Motion CPU and PC CPU module in any of the following combinations as indicated below. Basic model QCPU + Motion CPU Basic model QCPU + PC CPU Basic model QCPU + Motion CPU + PC CPU Basic model QCPU Sequence control Motion CPU Motion control PC CPU Data processing Data communication (2) Configuration of high-level motion control system In a Multiple CPU System consisting of the Basic model QCPU and Motion CPU, sequence control and motion control can be merged to achieve a high-level motion system. Sequence control Management Motion control Servo amplifier Servo amplifier Servo motor Servo motor

244 13 OUTLINE OF MULTIPLE CPU SYSTEMS (3) Data communication and large-volume data processing In a Multiple CPU System consisting of the Basic model QCPU and PC CPU module, sequence control and PC application program can be connected, e.g. machine control is processed by the Basic model QCPU and data communication and large-volume data are processed by the PC CPU module, to achieve a fast and highly flexible system. Host computer Data management Data communication Data base 13 PC CPU (4) Communication between CPU modules in Multiple CPU System The following data communication can be made between CPU modules in a Multiple CPU System. (a) (b) (c) Data can be transferred between the CPU modules by merely making automatic refresh setting. The Basic model QCPU can read data from the CPU shared memory of the other CPU when necessary using the intelligent function module device or FROM instruction. Instructions dedicated to Motion can be used to issue control commands from the Basic model QCPU to the Motion CPU. 1 (d) The Basic model QCPU can issue instructions dedicated to communication between multiple CPUs, to read or write device data from/to the Motion CPU or PC CPU module. The Basic model QCPU can issue events to the PC CPU module. 2 REMARK 1: Refer to the manual of the Motion CPU for instructions dedicated to Motion. 2: Refer to the manuals of Motion CPU and PC CPU module for instructions dedicated to the communication between multiple CPUs

245 13 OUTLINE OF MULTIPLE CPU SYSTEMS 13.2 Outline of Multiple CPU Systems (1) What is a Multiple CPU System? (a) A multiple CPU System is a system in which multiple (up to three*1) CPU modules are mounted on the main base unit or slim type main base unit to control the I/O modules and intelligent function modules by the corresponding CPU modules. Basic model QCPU Motion CPU PC CPU module Basic model QCPU Motion CPU PLC CPU PC CPU module The allowable CPU modules are shown in the table below. (Refer to Section for the compatible version of each module.) Motion CPU QCPU,Q1CPU Q172CPU, Q173CPU,Q172CPUN,Q173CPUN PC CPU module CONTEC Co.,Ltd.*2 Choose the CPU modules suitable to the system size and application to configure the system. It is necessary to set (control PLC setup) which High Performance model QCPU and motion CPUs are to control which I/O modules and intelligent function modules with a Multiple CPU System. CPU Power supply Basic model QCPU Motion CPU 1 2 Input module 1 Input module Output module 1 1 Intelligent function module Input module Intelligent function module Output module Setup of the controlling CPU module 3 Control performed with the Basic model QCPU (b) Control performed with the Motion CPU The CPU module that controls the I/O modules and intelligent function modules is known as the "Control CPU". The I/O modules and intelligent function modules controlled by the control CPU are known "controled modules". Other modules not controlled by the control CPU are known as "noncontrolled modules". REMARK 1: Refer to Section 14.2 for the combinations of applicable CPU modules. 2: For further information on PC CPU module, consult CONTEC Co.,Ltd. Tel: : Indicates the grouping configuration on the GX Developer. "1" under the Basic model QCPU indicates "CPU No. 1", and "1" under the I/O module or intelligent function module indicates that the control CPU is CPU No

246 13 OUTLINE OF MULTIPLE CPU SYSTEMS (2) Multiple CPU System setup When performing control in a Multiple CPU System, it is necessary to set the "Number of mounted CPU modules" and "Control CPU" for all the CPU modules mounted on the main base unit or slim type main base unit. (Refer to Chapter 9.) (3) Multiple CPU System access range (a) (b) It is possible for a Multiple CPU System's control CPU to perform the I/O refresh procedure on control modules and write in the buffer memory of intelligent function modules in the same way as a Single CPU System. It is possible to access non-control modules in the following ways. Refresh the input for input modules, hybrid I/O modules and intelligent function modules. (the PLC parameter Multiple CPU setup is necessary.) Read the intelligent function module's buffer memory. Read the output data from the output modules, hybrid I/O modules and intelligent function modules. However, it is not possible to access non-control modules in the following ways. Output data to the output modules, hybrid I/O modules and intelligent function modules. Writing data into the intelligent function module's buffer memory. CPU Power supply Basic model QCPU Motion CPU Input module Input module Output module Intelligent function module Input module Intelligent function module Output module Possible to read with the Motion CPU (c) Possible to read with the Basic model QCPU CPU module access range Access can be made to the other CPUs via the network module of the controlled modules. For the access device range, refer to the user's manual of the corresponding network module. (4) GX Developer access range (a) (b) (c) It is possible to perform parameter/program read/write, monitor and test for the Basic model QCPU connected to the personal computer. GX Developer can make access to the modules of the Basic model QCPU connected to the personal computer, independently of whether they are controlled or non-controlled modules. It can also make access to the Basic model QCPU of another station on the same network, such as MELSECNET/H or Ethernet. It is possible for all Basic model QCPUs on a Multiple CPU System to be accessed from a GX Developer that is connected to other stations on the same network

247 13 OUTLINE OF MULTIPLE CPU SYSTEMS 13.3 Differences with Single CPU Systems The differences between Single CPU Systems and Multiple CPU Systems are explained below. (1) Function versions (see Sections to ) (a) (b) (c) The Basic model QCPU of function version B is compatible with a Multiple CPU System. (The QJCPU is not compatible with a Multiple CPU System.) In a Multiple CPU System, the Basic model QCPU of function version A cannot be used. All I/O modules can be used on a Multiple CPU System. In a Multiple CPU System, use intelligent function modules that are compatible with a Multiple CPU System. The intelligent function modules that are incompatible with a Multiple CPU System can be used when CPU No. 1 is set as the control CPU. (2) Mounting position of CPU module (see Section ) Mount the Basic model QCPU on the CPU slot (on the right-hand side of the power supply module). Mount the Motion CPU on the slot on the right-hand side of the Basic model QCPU. Mount the PC CPU module at the right end of the CPU modules in a Multiple CPU System. Only one module of each of the Basic model QCPU, Motion CPU and PC CPU module can be used. (3) Multiple CPU System parameters (see Section ) In comparison with independent CPU systems, there are more PLC parameter items on a Multiple CPU System. Of the PC parameters that have been added to the Multiple CPU System, the parameters that must be set are listed below. Number of CPUs: Sets the number of mounted Basic model QCPUs, Motion CPUs and PC CPU module that are in use. Control CPU settings: Sets which Basic model QCPU, Motion CPU and PC CPU module controls while modules. (4) Sameness check (see Section ) The Multiple CPU System parameters, such as the number of CPUs and control CPU settings, have items that must be the same for the used CPU modules. The CPU modules check whether the Multiple CPU System parameters are the same (matching check) when the PLC is powered on or when the Basic model QCPU is reset or switched from STOP to RUN. If an error occurs in the matching check, the Multiple CPU System will not start up. (5) Concept of the I/O number (see Section 15.1) The right side of the installed CPU module is I/O number "H" in the Multiple CPU System. For this reason, the position of I/O number "H" varies according to the number of installed CPUs. However, because each PC CPU module occupies two slots (one slot for CPU and one empty slot), the I/O number deviates by the number of points set to the empty slot. (Default: empty 16 points)

248 13 OUTLINE OF MULTIPLE CPU SYSTEMS (6) Communication with non-controlled module (see Chapter 17) (a) (b) It is possible to control I/O modules and intelligent function modules controlled by the host CPU in the same way as on an Single CPU System. It is not possible to output ON.OFF data to modules that are not controlled by the host CPU or write in the buffer memory of intelligent function modules. It is possible to read I/O data from non-control modules with PLC parameter settings. It is possible to confirm the status of modules controlled by other CPUs, the control status of other CPUs, and control the host PLC. (7) Interactive transmission between each CPU modules on a Multiple CPU System (see Chapter 16) It is possible to perform the following interactive transmission between each CPU modules with a Multiple CPU System. (a) Automatically refreshing the device data between each CPU modules with Multiple CPU System parameter settings. (b) Data send/receive to/from the PC CPU module via the CPU shared memory using the multiple CPU instructions (FROM, TO, S.TO instructions) (c) Reading CPU shared memory of Motion CPU from Basic model QCPU with Multiple CPU instructions (FROM instruction). (d) Control instruction from the Basic model QCPU to the Motion CPU with motion dedicated CPU instructions. (e) Writing and reading of the device data from the Basic model QCPU to the Motion CPU/PC CPU module with communication dedicated instructions between multiple CPUs. (f) Event issuance from Basic model QCPU to PC CPU module using instructions dedicated to multiple CPU communication (8) Processing during resets and errors (see Sections and ) The reset and error-time processings differ between CPU No. 1, No. 2 and No.3 of the Multiple CPU System. (a) (b) In the Multiple CPU System, the whole system can be reset by resetting CPU No. 1. Only the CPU module No. 2 or No. 3 cannot be reset. When a stop error occurs in the Basic model QCPU as CPU No. 1, the Multiple CPU System stops. When CPU module No. 2 or No. 3 results in a stop error, whether the Multiple CPU System will be stopped or kept operated can be selected. (9) Clock function An intelligent function module with which the error code and time of occurrence is stored in the buffer memory when an error is triggered is available. The CPU No.1 time data will be stored as the time that the error occurred regardless of whether the module concerned is a control CPU or a non-control CPU

249 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM 14.1 System Configuration This chapter explains the system configuration of Multiple CPU Systems, and the precautions for Multiple CPU System configuration. This section explains the equipment configuration of Multiple CPU Systems, the connections with peripheral device, and an output of the system's configuration. (1) Equipment configuration of Multiple CPU System (a) When main base unit (Q3 B) is used MITSUBISHI LITHIUM BATTERY 14 Basic model QCPU (QCPU,Q1CPU) Motion CPU PC CPU module 1 Battery (Q6BAT) Main base unit (Q33B,Q35B,Q38B,Q312B) Power supply module 2, I/O module,intelligent function module of the Q Series Motion only module Q5 B extension base unit (Q52B,Q55B) Extension cable (QC5B, QC6B,QC12B, QC3B,QC5B,QC1B) Q6 B extension base unit (Q63B,Q65B,Q68B,Q612B) I/O module, lntelligent function module Motion only module Power supply module 2, I/O module,intelligent function module Motion only module POINT (1) 1: For further information on PC CPU module, consult CONTEC Co., Ltd Tel: (2) 2: As a power supply module, use the Q61P-A1, Q61P-A2, Q62P or Q64P. Make the power consumption within the rated output current value of the power supply module. The slim type power supply module (Q61SP) cannot be used

250 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM (b) When slim type main base unit (Q3 SB) is used MITSUBISHI LITHIUM BATTERY Basic model QCPU (QCPU,Q1CPU) Battery (Q6BAT) Slim type main base unit (Q32SB,Q33SB,Q35SB) Slim type power supply, I/O, intelligent function modules 14 POINT (1) 1: As a power supply module, use the slim type power supply module (Q61SP). The Q61P-A1, Q61P-A2, Q62P or Q64P cannot be used. (2) The slim type main base unit does not have an extension cable connector. The extension base or GOT cannot be connected

251 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM (2) Configuration of peripheral device for Basic model QCPU Basic model QCPU (QCPU,Q1CPU) RS-232 cable (QC3R2) Personal computer GX Developer Version 8 or later POINT (1) Refer to the Motion Controller User s Manual for connection between the Motion CPU and peripheral modules. (2) The GX Developer installed in a Personal computer connected to the Motion CPU is not used to communicate with the Basic model QCPU. (3) Refer to the manual of the PC CPU module for the connection between the PC CPU module and peripheral modules. (4) Both the motion CPU and PC CPU module have restrictions depending on the version. When making connection with a peripheral device, always refer to the manual of the Motion CPU or PC CPU module

252 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM (3) Outline of system configuration (when Basic model QCPU, Motion CPU and PC CPU module are mounted) (a) When main base unit (Q3 B) is used (a) System where extension base units are connected (b) System where extension base units and GOT are connected Main base unit (Q38B) Slot No. Main base unit (Q38B) Slot No. Extension cable OUT Power supply module C P U 1 C P U 2 C P U 3 Empty, 16 points F 4F 6F 8F AF Extension cable OUT Power supply module C P U 1 C P U 2 C P U 3 Empty, 16 points F 4F 6F 8F AF 1 extension stages IN OUT Power supply module PC CPU occupies 2 slots. Extension base unit (Q65B) B D F CF EF 1F 12F 14F 1 extension stages IN OUT Power supply module PC CPU occupies 2 slots. Extension base unit (Q65B) B D F CF EF 1F 12F 14F System configuration 2 extension stages IN OUT Power supply module Extension base unit (Q65B) extension stages B1D 16F 18F1AF1CF1EF IN OUT Power supply module Extension base unit (Q65B) B 1D 16F 18F1AF1CF1EF 3 extension stages IN OUT Power supply module Extension base unit (Q65B) F F 22F24F 26F 28F 3 extension stages IN OUT Power supply module Extension base unit (Q65B) F F 22F24F 26F 28F 4 extension stages IN OUT Power supply module Extension base unit (Q65B) AF Must not be used. Must not be used. Must not be used. Must not be used. When each slot is mounted with 32-point module GOT Number of extension units: 4 Slot No.: CPU number Maximum number of extension units CPU1: CPU No. 1 (Basic model QCPU), CPU2: CPU No. 2 (Motion CPU), CPU3: CPU No. 3 (PC CPU module) 4 extension units Number of CPUs setting in Maximum number Multiple CPU setting of mounted I/O modules Number of mounted modules 24 modules 23 modules 21 modules Maximum number 124 (maximum number of I/O points of CPU module. 124 points per module when CC-Link/LT is used.) of I/O points Main base unit Q33B, Q35B, Q38B, Q312B model name Extension base Q52B, Q55B, Q63B, Q65B, Q68B, Q612B unit model name Extension cable QC5B, QC6B, QC12B, QC3B, QC5B, QC1B model name (1) Use the extension cables within the overall distance of 13.2m. (2) When using the extension cable, do not bundle it with, or run it close to, the main circuit (high voltage, large current) line. (3) Set the extension unit numbers in ascending order so that the same number is not used for different extension base units. (4) The QA1S6_B/QA65B cannot be connected as the extension base unit. Notes (5) Connect the extension cable from OUT of the extension cable connector of the base unit to IN of the next extension base unit. (6) An error occurs if modules are mounted on 26 or more slots. (Number of mounted modules including PLC No. 1) (7) When mounting a Motion CPU, refer to the Basic Model QCPU User's Manual (Function Explanation, Program Fundamentals). (8) Refer to Section for the I/O numbers in a Multiple CPU System configuration other than the above. (9) The PC CPU occupies two slots

253 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM (b) When slim type main base unit (Q3 SB) is used Slim type main base unit (Q35SB) Slot No. System configuration Power supply module C P U 1 C P U 2 C P U 3 Empty, 16 points 1 3 2F 4F PC CPU occupies 2 slots. Shows a system where each slot is mounted with 32-point module. CPU number Maximum number of extension units CPU1: cpu No. 1 (Basic model QCPU), CPU2: CPU No. 2 (Motion CPU), CPU3: No. 3 (PC CPU module) Extension not allowed Number of CPUs setting in Maximum number Multiple CPU setting of mounted I/O modules Number of mounted modules 5 modules 4 modules 2 modules Maximum number 124 (maximum number of I/O points of CPU module. 124 points per module when CC-Link/LT is used.) of I/O points Slim type main base unit model Q32SB, Q33SB, Q35SB name Extension base Cannot be connected. unit model name Extension cable Cannot be connected. model name (1) The Q61P-A1, Q61P-A2, Q62P or Q64P cannot be used as a power supply module. Use the Q61SP as a power supply module. Notes (2) The slim type main base unit does not have an extension cable connector. The extension base or GOT cannot be connected

254 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM 14.2 Precautions For Multiple CPU System Configuration Function versions of Basic model QCPU, Motion CPU and PC CPU module that can be used, and their mounting positions (1) Versions applicable to Multiple CPU System (a) Basic model QCPU Use the function version B. Refer to Section 2.3 for how to confirm the function version. (b) Motion CPU Confirm the applicable version of the Motion CPU in the programming manual of the Motion CPU. (c) PC CPU module Use Version 1.7 or later of the PC CPU module bus interface driver software package (PPC-DRV-1). For details, confirm the version in the manual of the PC CPU module

255 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM (2) Basic model QCPU, Motion CPU and PC CPU module mounting positions (a) One Basic model QCPU can be mounted on the CPU slot (slot on the righthand side of the power supply module) of the main base unit. Mount only one PC CPU module at the right end of CPU modules. (No CPU module can be mounted on the right side of the PC CPU module.) Table 14.2 Installation positions of CPU modules Number of CPUs 1 Mounting positions of CPU modules CPU Power supply Basic model QCPU CPU 1 2 CPU 1 2 CPU Power supply Basic model QCPU Motion CPU Power supply Basic model QCPU PC CPU module 2 Power supply Basic model QCPU Empty CPU 1 2 CPU 1 2 CPU Power supply Basic model QCPU Motion CPU PC CPU module 2 CPU 1 2 Power supply Basic model QCPU Motion CPU Empty Power supply Basic model QCPU Empty PC CPU module 2 Power supply Basic model QCPU Empty Empty 1: The number of CPUs indicated is the value set in the Multiple CPU setting of the PLC parameter dialog box. 2: The PC CPU module occupies two slots

256 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM (b) The Motion CPU cannot be mounted on other than Slot. Also, any CPU module cannot be mounted on the right side of the PC CPU module. CPU 1 2 Power supply Basic model QCPU PC CPU module Motion CPU (c) An empty slot is secured for future addition of a CPU module. Set the number of CPU modules including the empty slot in the number of CPUs setting, and set the type of the slot to be emptied as "CPU (Empty)". POINT When adding a Motion CPU in the future to the system that uses the Basic model QCPU and PC CPU module, mount the PC CPU module on Slot 1 and set Slot as "CPU (Empty)". (3) Basic model QCPU, Motion CPU and PC CPU module PLC numbers The CPU numbers are allocated to differentiate between the Basic model QCPU, Motion CPU and PC CPU module mounted in the Multiple CPU System. The Basic model QCPU on the CPU slot is set as CPU No. 1, and the CPUs are allocated in order of No. 1, No. 2 and No. 3 from left to right. CPU slot: CPU No Basic model QCPU (fixed) Slot : CPU No Motion CPU Slot 1 : CPU No PC CPU module Power supply Basic model QCPU Motion CPU PC CPU module These CPU numbers are used to set the control CPUs in I/O assignment, for example

257 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM Precautions when using Q Series I/O modules and intelligent function modules (1) Compatible I/O modules All I/O modules (QX, QY ) are compatible with to Multiple CPU System. They can be used by setting any of CPU No.1 to No.3 as a control CPU. (2) Compatible intelligent function modules (a) (b) (c) (d) The intelligent function modules compatible with the Multiple CPU System are those of function version B or later. They can be used by setting any of CPU No.1 to No.3 as a control CPU. Q Series high speed count modules (QD62, QD62D, QD62E) are compatible with by Multiple CPU System are those of function version A or later. They can be used by setting any of CPU No.1 to No.3 as a control CPU. Q Series interruption modules (QI6) do not have a function version, but are supported by Multiple CPU Systems. CPUs No.1 to No.4 can be set up as control CPUs. The intelligent function module of function version A can be used in a Multiple CPU System when CPU No. 1 is set as the control CPU. However, only the control CPU can be accessed from the serial communication module, etc. externally. (The MELSECNET/H, serial communication module, etc. cannot make external access to non-control CPUs.) If CPU No. 2 or No. 3 is set as a control CPU, "SP. UNIT VER. ERR (error code: 215)" will occur and the Multiple CPU System will not start up. (3) Ranges of access to control and non-control modules In a Multiple CPU System, non-control modules can be accessed by setting "I/O setting outside of the group" at the "Multiple CPU settings" dialog box in "PLC Parameter". The following table indicates accessibility to the control and noncontrol modules in the Multiple CPU System. Access target Input (X) Read Output (Y) Write Buffer Read memory Write Control module Accessibility Non-control module (I/O setting outside of the group) Disabled Enabled : Accessible : Inaccessible REMARK The function version of intelligent function modules can be confirmed at the rated name plate of the intelligent function module and with the GX Developer's "System monitor product information list window" (see Section 2.3.) See Section for details on restrictions on the number that can be used with intelligent function modules

258 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM Modules that have mounting restrictions Product Q series MELSECNET/H network modules Q series Ethernet interface modules The following table indicates restrictions on the number of modules that can be mounted in Multiple CPU Systems. Ensure that the number of modules mounted is within these ranges. Model QJ71LP21 QJ71BR11 QJ71LP21-25 QJ71LP21G QJ71LP21GE QJ71E71 QJ71E71-B2 QJ71E71-1 Number of modules that can be mounted per system A total of up to four modules on the inter-plc network. (However, the module that can be controlled by the Basic model QCPU is only one module on the inter-plc network) Up to one module Number of modules that can be mounted on Basic model QCPU Up to one module on the inter- PLC network Up to one module Q series CC-Link system QJ61BT11 Up to six modules master/local modules Up to two modules Interruption modules QI6 Up to three modules Only one module : Indicates the number of interrupt modules to which the interrupt pointer setting has not been made. When the interrupt pointer setting has been made, the number of modules that can be used is as follows. QCPU, Q1CPU: 24 modules Compatible GX Developers and GX Configurators (1) Compatible GX Developers GX Developer Version 8 (SW8D5C-GPPW-E) or later are compatible with on Multiple CPU Systems. GX Developer Version 7 (SW7D5C-GPPW-E) or earlier are not compatible with Multiple CPU System. (2) Compatible GX Configurators The GX Configurator version that can be used in a Single CPU System can be used in a Multiple CPU System without modifications

259 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM Parameters that enable the use of Multiple CPU System (1) Parameters that enable the use of Multiple CPU System Compared with the Single CPU System, the Multiple CPU System includes the "No. of CPU", "control CPU", "refresh setting (automatic refresh setting)" of PLC parameters. The PLC parameters must be set to the same for all the CPU modules used in the Multiple CPU System, except some modules. Make similar settings to the PC CPU module, if one is included, using the PC CPU module setting utility. For the setting method, refer to the manual of the PC CPU module. (2) The PLC parameter settings for use with Multiple CPU System The PLC parameters, necessity of setup, and descriptions that are required for using Multiple CPU System are listed in table Table 14.3 Setting list for the Multiple CPU and I/O Assignment I/O Assignment PLC system settings Multiple CPU settings PC parameter I/O Assignment Type Necessity of 1 Description setup Model name Points Start Standard setting Base model name Power model name Extension cable Points Switch settings Detailed settings Error time output made H/W error time CPU operation made I/O response time Control CPU Number of empty slots No. of CPU Operation mode Online module change The input condition outside of the group is taken The output condition outside of the group is taken Refresh setting Send range for each CPU PLC side devices 1: Necessity of setup column : Items that must be set up for Multiple CPU System (operations not possible if not set up.) : Items that may be set up when required for Multiple CPU System (Operations carried out with the default values when not set up.) : Items that are the same as Single CPU Systems. 2: Descriptions : Items that have the same settings for all CPU modules on the Multiple CPU System. : Items that have the same settings for all Basic model QCPUs and PC CPU module on the Multiple CPU System (items that do not have settings for Motion CPUs). : Items that can be setup up individually for each CPU modules on the Multiple CPU system

260 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM After changing the parameter setting such as the Multiple CPU setting, match the settings of all CPUs in the Multiple CPU System, and then reset CPU No. 1 or power the PLC OFF, the ON. It is possible to transfer across and use the CPU settings and I/O Assignments set up for other projects with GX Developer. (See section for details on transferring and using Multiple CPU settings and I/O Assignments.) (a) Number of CPUs setting (setup necessary) 1) The number of CPU modules to be used on a Multiple CPU System are set at the PLC parameter's "Multiple CPU settings" screen in the (PLC) Parameter dialog (indicated with the "A" arrow.) A 2) Ensure that the No. of CPU set for the Multiple CPU System is the same as the number of CPUs actually mounted. To secure the "empty slot" where a CPU module will be mounted in the future, set "CPU (Empty)" in the I/O assignment setting of the Parameter dialog box. For example, when setting the number of CPUs to three in the Multiple CPU setting and securing a slot for the Motion CPU, set CPU No. 2 to "CPU (Empty)". (Arrow B) B 3) In the following cases, "CPU LAY ERROR (error code: 731)" occurs in the mounted CPU modules. When the number of mounted CPU modules exceeds the number set as the number of CPUs. When no CPU module is mounted on any of the slots set for CPU No. 1 to No

261 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM (b) (c) (d) (e) Operation mode setting (optional) This is set to continue operation of other CPUs where a stopping error has not occurred when an error occurs at any of CPUs No.2 and No.3. The operation mode for the CPU No.1 cannot be changed (all CPUs will suspend operations when a stop error is triggered for the CPU No.1.) See Section for further details. I/O settings outside of the group (optional) This is set when the input and output (X, Y) for I/O modules and intelligent function modules being controlled by other CPUs is to be downloaded to the host CPU. See Section 17.2 for further details. Refresh setting (optional) This is set up to automatically refresh the device data on the Multiple CPU System. See Section 16.1 for further details. Control CPU settings (optional) Sets up the control CPUs for the I/O modules and intelligent function modules mounted on the base units on the Multiple CPU System (indicated by the "C" arrow.) All default settings are set for the CPU No.1. C

262 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM (3) Multiple CPU setting and I/O Assignment checks Checks, as shown in table 14.4, will be run to ascertain that all CPU modules have the same settings (sameness check) when the description column in table 14.3 has been set with the "O" symbol and the power to the sequence is switched on, the Basic model QCPU is reset, or the status is changed from STOP to RUN. (a) (b) The Multiple CPU System will be started up if all CPUs have the same settings. The operations described in table 14.4 will be performed when all CPUs do not have the same settings. In this event, check the Multiple CPU settings and I/O Assignment, and set all CPUs with the same settings. To start the Multiple CPU System, reset the Basic model QCPU for CPU No.1 or turn off and on the CPU (power ON OFF ON). (For the action after the Basic model is reset, see Section ) Table List of sameness check contents Item PLC No.1 PLC No.2, 3 When the power to the CPU is switched on When CPU No.1 is reset A comparison check will be run on the Multiple CPU settings and I/O No sameness check will be run Assignments for CPU No.1. A "PARAMETER ERROR (error code: 312)" will occur in the host CPU if they do not match. A comparison check will be run on the Multiple CPU settings and I/O Assignments for When CPUs in the RUN mode exist the CPU in the RUN mode with the lowest number. A "PARAMETER ERROR (error code: 312)" will occur in the host CPU if they do not match. When the RUN/STOP A comparison check will be run on the A comparison check will be run on the switch has been changed Multiple CPU settings and I/O Multiple CPU settings and I/O from STOP to RUN. When CPUs in the Assignments for CPU No.2. Assignments for CPU No.1. When parameters are RUN mode do not A "PARAMETER ERROR (error code: A "PARAMETER ERROR (error code: written with the GX exist 312)" will occur in the host CPU if they 312)" will occur in the host CPU if they Developer do not match. do not match. STOP RUN is not allowed as a When a stop error "MULTIPLE CPU DOWN (error code: occurs at CPU No.1 7)" error will occur in the host CPU. POINT After Multiple CPU System parameters unavailable with the Motion CPU are changed for the Basic model QCPU or PC CPU module in a Multiple CPU System including a Motion CPU, be sure to reset the Basic model QCPU for CPU No.1 or turn off and on the CPU. (Otherwise the Basic model QCPU or PC CPU module checks consistency with Multiple CPU System parameters of the Motion CPU, causing a "PARAMETER ERROR (error code: 312)."

263 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM Resetting the Multiple CPU System In the Multiple CPU System, the whole system can be reset by resetting the Basic model QCPU. Resetting the Basic model QCPU resets all the CPU modules No. 2, No. 3, I/O modules and intelligent function modules. To restore the Multiple CPU System when any of the CPUs in the system is in a stop error, reset the Basic model QCPU or power on the CPU again (power ON OFF ON). (Recovery is not allowed by resetting the CPU modules for CPU No.2 and No.3 for which stop errors have occurred.) PLC No.1 PLC No.2 PLC No.3 Power supply Basic model QCPU Motion CPU PC CPU module Reset is not allowed with the Multiple CPU System. If a reset is attempted all CPUs on the Multiple CPU System will assume the "MULTIPLE CPU DOWN" status. The entire multiple PLC system can be reset. POINT (1) It is not possible to reset the CPU modules for CPU No.2 and No.3 individually in the Multiple CPU System. If an attempt to reset any of the CPU modules for CPU No.2 and No.3 during operation of the Multiple CPU System, a "MULTIPLE CPU DOWN (error code: 7)" error will occur for the other CPUs, and the entire Multiple CPU System will be halted. However, depending on the timing in which the CPU modules have been reset, there are cases where errors other than the "MULTIPLE CPU DOWN" error will halt the other CPUs. (2) A "MULTIPLE CPU DOWN (error code: 7)" error will occur regardless of the operation mode set at the "Multiple CPU settings" screen within the (PLC) Parameter dialog box. (stop/continue all other CPUs on the CPU modules for CPU No.2 and No.3 error) when the CPU modules for CPU No.2 and No.3 are reset (See Section for details on the Multiple CPU setting operation modes.)

264 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM Processing when stop errors occur In the Multiple CPU System, the operation of the whole system differs between when the Basic model QCPU results in a stop error and when the CPU module No. 2 or No. 3 results in a stop error. (1) When the Basic model QCPU results in a stop error (a) (b) When the Basic model QCPU results in a stop error, the CPU modules No. 2, No. 3 all result in "MULTI CPU DOWN (error code: 7)" and the Multiple CPU System stops. (Refer to POINT on the next page for details.) Restore the system in the following procedure. 1) Confirm the error cause of the Basic model QCPU with the PLC diagnosis function. 2) Remove the error cause. 3) Reset the Basic model QCPU or power on the PLC again. By resetting the Basic model QCPU or powering on the PLC again, all the CPUs in the Multiple CPU System are reset and the system is restored. (2) When the CPU module No. 2 or No. 3 results in a stop error When the CPU module No. 2 or No. 3 results in a stop error, set in the "Operation Mode" in the Multiple CPU setting whether the whole system will be stopped or not. The default setting is to stop all CPUs at occurrence of a stop error in all CPUs. When it is not desired to stop all CPUs at occurrence of a stop error in any of the CPU modules, click the checked check boxes of CPU No. 2 and No. 3. (Arrow D) D (a) (b) A "MULTIPLE CPU DOWN (error code: 7)" error occurs for the CPU modules and the Multiple CPU System will be halted when a stop error is occurs in CPU modules for which the "All station stop by stop error of CPU 'n' " has been set. (See POINT on the next page for details.) A "MULTIPLE CPU ERROR (error code: 71)" error occurs for all other CPUs but operations will continue when a stop error occurs in CPU modules for which the " All station stop by stop error of CPU 'n' " has not been set

265 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM POINT A "MULTIPLE CPU DOWN" stop error will be occur for the CPU on which the error was detected when a stop error occurs. There are cases where the timing of error detection will search for the CPU on which the stop error that has caused the "MULTIPLE CPU DOWN" error occurs, not the first CPU on which a stop error occurs, and the entire system will assume the "MULTIPLE CPU DOWN" status. For example, if a stop error occurs in the CPU No.2 and the CPU No.3 is halted as a direct consequence of this, there are cases where the CPU No.1 will be halted because of the stop error on CPU No.3 depending on the timing of error detection. Halted with an "WDT ERROR" Power supply Basic model QCPU No.1 Motion CPU No.2 PC CPU module No.3 Halted with stop error detection on PLC No.2 (becomes "MULTIPLE PLC DOWN") There are cases where the system will be halted with stop error detected on the PLC No.3 depending on the timing of error detection. (becomes "MULTIPLE PLC DOWN") Owing to this, there are cases where a different CPU No. to the CPU that initially caused the stop error will be stored in the error data's common information category. In this event, remove the reason for the error on the CPU that caused the stop error in addition to the "MULTIPLE CPU DOWN" error when restoring the system. (c) Observe the following procedures to restore the system. 1) Confirm the cause of the CPU No.1 error with the PLC diagnostics function. 2) Remove the cause of the error. 3) Reset the Basic model QCPU or power on the PLC again. By resetting the Basic model QCPU or powering on the PLC again, all the CPUs in the Multiple CPU System are reset and the system is restored

266 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM Reducing the time required for Multiple CPU System processing (1) Multiple CPU System processing A bus (base unit pattern, extension cable) is used by the CPU module when accessing the I/O module and intelligent function module, and this bus cannot be used by plural CPU module at the same time. The CPU modules that attempted buss access afterwards when plural CPU module use the bus simultaneously will assume the "Standby" status until processing for the CPU module that executed the procedure first has been completed. This "Standby" status (the amount of time the CPU module must wait) will cause delays in input and output on the Multiple CPU System, and result in extended scan times. See Chapter 18 for details on extended scan times. (2) Maximum standby time The host CPU will reach the maximum standby time in the following cases with a Multiple CPU System. When three CPU modules are used on the Multiple CPU System. When additional base units are in use. When intelligent function modules that possess vast quantities of data are mounted onto additional base units. When three CPU modules simultaneously access modules mounted onto additional base units. (3) Reducing the time required for Multiple CPU System processing The following methods are available for reducing the amount of time required for Multiple CPU System processing. Combine modules with many access points, such as MELSECNET/H and CC- LINK refresh, etc., together into a main base unit. Set modules with many access points, such as MELSECNET/H and CC-LINK refresh, etc., as control module on a single CPU module, and ensure that simultaneous access does not occur. Reduce the number of MELSECNET/H and CC-LINK refresh access points. Reduce the number of automatic refresh points between CPU modules

267 15 ALLOCATING MULTIPLE CPU SYSTEM I/O NUMBERS 15 ALLOCATING MULTIPLE CPU SYSTEM I/O NUMBERS 15.1 Concept behind Allocating I/O Numbers Multiple CPU Systems possess I/O numbers to enable interactive transmission between the CPU modules and the I/O modules and intelligent function modules, and I/O numbers to enable interactive transmission between the CPU modules I/O modules and Intelligent function module I/O numbers 15 The difference with Single CPU Systems is the H position (slot) of the I/O number with Multiple CPU Systems. However, the concept behind the sequence for allocating I/O numbers, the I/O numbers for each slot, and the I/O numbers for empty slots is the same for both types of system. See Chapter 5 (Allocating I/O Numbers) for details on the concept behind the sequence for allocating I/O numbers, the I/O numbers for each slot, and the I/O numbers for empty slots. (1) "H" position for I/O numbers (a) (b) (c) The number of slots set with the PLC parameters' Multiple CPU settings are occupied by the CPU modules on the Multiple CPU System. The I/O modules and intelligent function modules are mounted from the right of the slots occupied by the CPU modules. I/O number of a system without PC CPU module The I/O number for the I/O modules and intelligent function modules mounted from the right of the slots occupied by the CPU modules is set as "H" and consecutive numbers are then allocated sequentially to the right. 1) Example: Two modules are mounted Power supply Basic model QCPU Motion CPU I/O number : H 2) Example: Three modules are mounted and one empty slot exists Power supply Basic model QCPU Motion CPU Empty (d) I/O number : H Input/output number of a system with PC CPU module The PC CPU module occupies two slots. The one on the right side among the two slots is handled as an empty slot. (16 empty points are occupied with default setting.) Therefore the I/O number of the slot on the right side of the PC CPU module is "1H." (Set the empty slot at zero point using I/O allocation of PLC Parameters dialog box, to assign "H" to the first I/O number.) 1) Example of setting the number of CPUs to Power supply Basic model QCPU PC CPU module Empty slot (H to FH occupied) Number of CPUs (2 modules)

268 15 ALLOCATING MULTIPLE CPU SYSTEM I/O NUMBERS 2) Example of setting the number of CPUs to Power supply Basic model QCPU Motion CPU PC CPU module Number of CPUs (3 modules) Empty slot (H to FH occupied) Power supply Basic model QCPU 1 2 No CPU PC CPU module Number of CPUs (3 modules) Empty slot (H to FH occupied) REMARK 1) If the number of CPU modules mounted on the main base unit is less than the number set in the Multiple CPU setting, set the empty slot to "CPU (Empty)". The I/O number for the Multiple CPU System can be confirmed with the system monitor

269 15 ALLOCATING MULTIPLE CPU SYSTEM I/O NUMBERS I/O number of Basic model QCPU, Motion CPU and PC CPU module I/O numbers are allocated to the CPU modules with the Multiple CPU System in order to allow interactive communications between the CPU modules with the following commands. Multiple CPU commands Motion dedicated commands Dedicated communication commands between multiple CPUs The I/O numbers for the CPU modules are fixed for the slots on which they are mounted and cannot be amended. The table below shows the I/O number allocated to each CPU module when the multiple CPU system is composed. CPU module mounting position CPU slot Slot Slot 1 First I/O number 3EH 3E1H 3E2H The CPU modules I/O numbers are used in the following cases. When writing data to the CPU shared memory with the TO or S.TO instruction 1 When reading the data of the CPU shared memory with the FROM instruction 1 When reading or writing data from or to the CPU shared memory with the intelligent function module device (U \G ) 1 When specifying the CPU module to be accessed with the Ethernet module. 2 When specifying the CPU module to be accessed with the serial communication module. 2 REMARK 1: See Chapter 16 for details on among Basic model QCPU, Motion CPU and PC CPU module. 2: For access to the Basic model QCPU by the Ethernet module or serial communication module, refer to the "Q Corresponding MELSEC Communication Protocol Reference Manual"

270 15 ALLOCATING MULTIPLE CPU SYSTEM I/O NUMBERS 15.2 Setting of Control CPUs with GX Developer Sets up the Basic model QCPU/motion CPU/PC CPU module that are to control the Multiple CPU System's I/O modules and intelligent function modules. (a) Q38B I/O modules and intelligent function modules can be selected as control CPUs for each slot. Power supply Basic model QCPU Motion CPU PC CPU model Q68B Power supply Control CPUs can be selected for each slot. Q68B Power supply

271 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM It is possible to perform the following interactive transmission between each CPU modules with a Multiple CPU System. Write/read of data between the CPU modules by automatic refresh of the CPU shared memory Write/read of data to/from the PC CPU module with the Multiple CPU instruction, or read of the CPU shared memory data of the Motion CPU from the Basic model QCPU Control command from the Basic model QCPU to the Motion CPU with the communication dedicated instruction Write/read of device data from the Basic model QCPU to the Motion CPU with the communication dedicated instruction between multiple CPUs Also, event issuance from the Basic model QCPU to the Motion CPU or PC CPU module can be performed. (1) Automatic refresh of CPU shared memory In the automatic refresh of the CPU shared memory, the systems of the CPU modules perform the write/read of data between the CPU modules in the Multiple CPU System automatically at the time of END processing. Since use of the automatic refresh reads the device memory data of the other CPUs automatically, the device data of the other CPUs can also be used as the device data of the host CPU. CPU No.1(Basic model QCPU) CPU No.2(Motion CPU) 16 CPU shared memory Host CPU's operation information area System area Automatic refresh area for writing in the CPU No.1 User's free area Writing performed with the CPU No.1 END process Device memory For use of the CPU No.1 For use of the CPU No.2 Automatic read by main cycle processing of CPU No. 2 Automatic read by END processing of CPU No. 1 CPU shared memory Host CPU's operation information area System area Automatic refresh area for writing in the CPU No.2 User's free area Automatic write by main cycle processing of CPU No. 2 Device memory For use of the CPU No.1 For use of the CPU No.2 (2) Exchanging data with multiple CPU instructions and instructions that use Intelligent function module device (U \G ) The Basic model QCPU of the Multiple CPU System uses the TO instruction, S.TO instruction, FROM instruction or U \G to make access to the CPU shared memory. The data written to the CPU shared memory of the host CPU with the TO instruction, S.TO instruction or U \G is read by the other CPU modules. Non-linked device data also read directly when the command is executed. CPU No.1(Basic model QCPU) CPU No.2(Motion CPU) CPU shared memory Host CPU's operation information area System area Data written with TO instruction, S.TO instruction or U \G Read performed with read instruction CPU shared memory Host CPU's operation information area System area Write performed with TO instruction, S.TO instruction or U \G Sequence program Execution of TO instruction, S.TO instruction or U \G Program Execution of read instruction

272 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM 16.1 Automatic Refresh of CPU Shared Memory (1) Automatic refresh of CPU shared memory (a) In the automatic refresh of the CPU shared memory, the CPU modules perform the write/read of data between the CPU modules in the Multiple CPU System automatically. (The Basic model QCPU as CPU No. 1 performs automatic refresh processing at END processing or COM instruction execution.) Since use of the automatic refresh reads the device memory data of the other CPUs automatically, the device data of the other CPUs can also be used as the device data of the host CPU. The automatic refresh of the CPU shared memory enables write/read of data: Between Basic model QCPU and Motion CPU Between Basic model QCPU and PC CPU module Between motion CPU and PC CPU module The following diagram shows the general operation performed when the Basic model QCPU as CPU No. 1 performs the automatic refresh of 32 points, B to B1F, and the Motion CPU as CPU No. 2 performs that of 32 points, B2 to B3F. CPU No.1(Basic model QCPU) CPU No.2(Motion CPU) CPU shared memory Host CPU's operation information area System area Automatic refresh area for writing in the No.1 machine 3) Automatic read by main cycle processing of CPU No. 2 CPU shared memory Host CPU's operation information area System area Automatic refresh area for writing in the No.2 machine User's free area User's free area 1) Automatic write by END processing or COM instruction execution of CPU No. 1 Device memory B to B1F (For use of the CPU No.1) B2 to B3F (For use of the CPU No.1) 4) Automatic read by CPU No. 1 (at END processing) 2) Automatic write by main cycle processing of CPU No. 2 Device memory B to B1F (For use of the CPU No.1) B2 to B3F (For use of the CPU No.1) 16 (b) (c) Automatic refresh processing of CPU No. 1 (at END processing or COM instruction execution) 1): The B to B1F transmission device data for the CPU No.1 is transferred across to the host CPU shared memory automatic refresh area. 4): The data in the CPU No.2 CPU shared memory automatic refresh area is transferred across to B2 to B3F in the host CPU. Automatic refresh processing of CPU No. 2 2): The B2 to B3F transmission device data for the CPU No.2 is transferred across to the host CPU shared memory automatic refresh area. 3): The data in the CPU No.1 CPU shared memory automatic refresh area is transferred across to B to B1F in the host CPU. Executing automatic refresh Automatic refresh is executed when the CPU module is in RUN status, STOP status or PAUSE status. Automatic refresh cannot be performed when a stop error has been triggered in the CPU module. If a stop error occurs on one module, the other modules for which an error has not occurred will save the data prior to the stop error being triggered. For example, if a stop error occurs in the CPU No.2 when B2 is ON, the B2 in the CPU No.1 will remain at ON, as shown in the operation outline in fig. (a). When automatic refresh is carried out, it is necessary to set the points to be transmitted by each CPU module and the device in which the data is to be stored (the device that will perform automatic refresh) with the PLC parameter multiple CPU settings

273 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM (2) Automatic refresh settings Set the points to be transmitted by each CPU and the device in which the data is to be stored with the PLC parameter multiple CPU settings for when automatic refresh is to performed. Range of transmission setting for each CPU module Switching between setting numbers Sets the header number of the device for which automatic refresh is to be performed (uses consecutive numbers from the setup device number to the number of specified points) (a) Setting switch/range of transmission for each CPU (refresh range) 1): It is possible to set four ranges from Setting 1 to Setting 4 for the refresh setting with the setting switch. For example, it is possible to set the refresh function to divide ON/OFF data into bit devices with Setting 1 and other data into word devices with Setting 2. 2): The transmission range for each CPU is set in units of two CPU shared memory points (two words.) (Becomes 2 points when specifying the word device with the CPU device, and 32 points when specifying the bit device.) PLC data for which the point is set at "" with the range of transmission for each CPU will not be refreshed. As the bit device becomes 16 points at one point of the CPU shared memory when refreshing is performed with 32 points between B and B1F on the CPU No.1 and with 32 points between B2 and B3F on the CPU No.2, the number of transmission points is two for the CPU No.1 and two for the CPU No.2. 3): The numbers of transmission points are 32 points for the Basic model QCPU and 248 points for the motion CPU/PC CPU module, making a total of 4416 points (4416 words) for all CPU modules. Basic model QCPU: 32 points Motion CPU: 248 points PC CPU module: 248 points All CPU modules: 4416 points (4416 words) Setting is in units of 2 points (2 words). The CPU shared memory (PLC share memory) is set in two points, and the bit device becomes 32 points when bit device is specified on the CPU device. Not refreshed as the number of points for CPU No. 3 is

274 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM 4): The CPU shared memory occupied with automatic refresh refreshing becomes the total of setting 1 to setting 4. When the number of transmission points is set, the first and last offset values of the used CPU shared memory are displayed in hexadecimal. The PLC where the transmission points have been set in Setting 1 and Setting 2 becomes the last address in the CPU shared memory of Setting 2. (In the following figure, up to 11H is used by PLC No. 1 and up to 23H by CPU No. 3.) The PLC that transmits only Setting 1 becomes the last address in the CPU shared memory of Setting 1. (In the following figure, up to the address of Setting 1 is used by CPU No. 2.) CPU No.1 transmission range Last CPU device Last address of each CPU share memory (PLC shared memory) 5): The same number of transmission points must be set for all CPUs on the Multiple CPU System. A "PARAMETER ERROR" occurs if the number of transmission points for one CPU is different. (b) CPU devices The following devices can be used for automatic refresh purposes (other devices cannot be set up with the GX Developer.) Settable devices Data register (D) Link register (W) File register (R, ZR) Link relay (B) Internal relay (M) Output (Y) Caution None Multiples of or 16 are specified for the first number. The device in the left column occupies one point for every transmission point. 1) CPU devices use the total amount of transmission point devices consecutively from the specified device number to the CPU No.1 to No.3 in the first set range. Set a device number so that the amount of transmission point devices can be secured. Sixteen times the number of transmission points will be set if a bit device is specified in the CPU device. For example, If the total number of transmission points for CPU No.1 to No.3 is eight, then 128 points will be set between B and B7F when the B link relay is specified

275 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM Setting 1: In the case of link relays 2) The CPU devices are set as follows. It is possible to change the device and set up settings 1 to 4. The same devices can also be specified as long as the device range for settings 1 to 4 are not duplicated. It is possible to change the device and set up settings 1 to 4. Setting 2: In the case of link registers Setting 3: In the case of link relays The same devices can be specified for settings 1 to 4. However, as setting 1 in the illustration on the left uses 128 points between B and B7F, B8 and higher can be used for setting 3. No part of a device number can be duplicated, as shown with B to B7F on setting 1 and B7 to BEF on setting 3. The first and last will be calculated automatically with the GX Developer

276 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM Each of the setting 1 to setting 4 devices can be set up independently. For example, the Basic model QCPU as CPU No. 1 can be set to the link relay, and the Motion CPU as CPU No. 2 to the internal relay. Refresh setting for Basic model QCPU When the Basic model QCPU and Motion CPU devices have been set up with different devices Set the same point for all the CPU. Refresh setting for Motion CPU When the Basic model QCPU and Motion CPU devices have been set up with the same device

277 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM 3) An outline of the operations when the automatic refresh function is divided into four ranges (Setting 1: Link relay (B), Setting 2: Link register (W), Setting 3: Data register (D), Setting 4: Internal relay (M)) and then performed is shown in the illustration below. CPU No.1 CPU No.2 Maximum 248 words CPU No.3 Maximum 248 words Other CPU's shared memory CPU No.2 transmission data (No.1) CPU No.2 transmission data (No.2) CPU No.2 transmission data (No.3) CPU No.2 transmission data (No.4) CPU No.3 transmission data (No.1) CPU No.3 transmission data (No.2) CPU No.3 transmission data (No.3) CPU No.3 transmission data (No.4) Reading performed with the CPU No.1 END process Setting 1 B to Setting 2 W Setting 3 D Device CPU No.1 transmission data (No.1) CPU No.2 reception data (No.1) CPU No.3 reception data (No.1) CPU No.1 transmission data (No.2) CPU No.2 reception data (No.2) CPU No.3 reception data (No.2) CPU No.1 transmission data (No.3) CPU No.2 reception data (No.3) Maximum 32 words Writing during the END process Writing during the END process Writing during the END process Writing during the END process CPU shared memory CPU No.1 transmission data (No.1) CPU No.1 transmission data (No.2) CPU No.1 transmission data (No.3) CPU No.1 transmission data (No.4) User's free area Maximum 32 words CPU No.3 reception data (No.3) Setting 4 M CPU No.1 transmission data (No.4) CPU No.2 reception data (No.4) CPU No.3 reception data (No.4)

278 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM (c) There are cases where old data and new data will become mixed up for each PLC depending on the timing of refreshing the host CPU and reading data from other CPUs. When performing automatic refresh, create an interlock program that uses the first refresh device of each CPU, and do not use the data of the other CPUs when old and new data exist together. The following example gives the programs of the Basic model QCPU and Motion CPU where the refresh settings in the Multiple CPU setting are as indicated below. <Parameter setting> CPU Shared Memory CPU Side Device Setting No. CPU No. Number of points First Last First Last Setting 1 CPU No. 1 2 C C1 M M31 CPU No M32 M63 Setting 2 CPU No. 1 1 C2 CB D D9 CPU No. 2 Send side program: Ladder Receive side program: Motion SFC X 6) M32 1) Send data processing (D to D9) 2) [ SET M ] [ RST M ] [ RST X ] 3) 4) [G] M [F] Data receive processing (D to D9) 5) [F1] SET M32 1) CPU No. 1 creates send data. 2) CPU No. 1 sets the data setting completion bit. <Automatic refresh execution between multiple CPUs> 3) CPU No. 2 detects the completion of send data setting. 4) CPU No. 2 performs receive data processing. 5) CPU No. 2 sets the completion of receive data processing. <Automatic refresh execution between multiple CPUs> 6) CPU No. 1 detects the completion of the receive data processing and proceeds to the next processing

279 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM 16.2 Communication with Multiple CPU Instructions and Intelligent Function Module Devices (1) Communication with Multiple CPU instructions (TO instruction / S. TO instruction / FROM instruction) and intelligent function module device (U \G ) The Basic model QCPU of a Multiple CPU System can use an TO instruction, S. TO instruction, FROM instruction and intelligent function module device (U \G ) to access the CPU shared memory of the Basic model QCPU, Motion CPU and PC CPU module. The data written to the CPU shared memory of the host CPU with the TO instruction, S.TO instruction or U \G can be read by the other CPU modules. Unlike the automatic refresh of the CPU shared memory, the data at the time of instruction execution can be read directly. The following diagram shows the general operation performed when the data written to the CPU shared memory by the Basic model QCPU as CPU No. 1 with the TO instruction, S.TO instruction or U \G is read by the CPU module No. 2 with the read instruction. CPU No.1(Basic model QCPU) CPU shared memory Host CPU's operation information area System area Data written with TO instruction, S.TO instruction or U \G 1) Write performed with TO instruction, S.TO instruction or U \G Sequence program Execution of TO instruction, S.TO instruction or U \G 2) Read performed with read instruction CPU No.2(Motion CPU) CPU shared memory Host CPU's operation information area System area Program Execution of read instruction Processing of CPU No. 1 1): Data is written to the free user area of CPU No. 1 with the TO instruction, S.TO instruction or U \G Processing of CPU No. 2 2): The data of the free user area of CPU No. 1 is read to the specified device with the read instruction

280 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM CPU No.1(Basic model QCPU) CPU shared memory Host CPU's operation information area System area Sequence program FROM instruction execution 2) Read performed with FROM instruction or U \G CPU No.2(Motion CPU) CPU shared memory Host CPU's operation information area System area Data written with write instruction 1) Write performed with write instruction Program Write instruction execution POINT Processing of CPU No. 2 1): Data is written to the free user area of CPU No. 2 with the write instruction. Processing of CPU No. 1 2): The data of the free user area of CPU No. 1 is read to the specified device with the FROM instruction or intelligent function module device (U \G ). Refer to the following manual for details of the TO instruction, S.TO instruction and FROM instruction. QCPU (Q mode)/qnacpu Programming Manual (Common Instructions) The Motion CPU and PC CPU module cannot use the TO instruction, S.TO instruction, FROM instruction and intelligent function module device (U \G ). Refer to the manuals of the corresponding CPU modules for how to make access from the Motion CPU and PC CPU module to the CPU shared memory

281 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM (2) Precautions (a) The following values are set in the CPU module's first I/O number with the FROM instruction, the TO instruction, the S. TO instruction and instructions that use U \G. CPU No. CPU No.1 CPU No.2 CPU No.3 Value set in the first I/O number 3EH 3E1H 3E2H (b) (c) (d) Do not perform writing as reading in the system area or automatic refresh area for the CPU shared memory (see Section 16.4). An error will not occur when CPUs accessed with the FROM instruction, the S. TO instruction and instructions that use U \G are reset. Establish an interlock to prevent simultaneous access during interactive data communication with the FROM instruction, the TO instruction, the S. TO instruction and instructions that use U \G. There are cases where old data and new data will be mixed together if simultaneous access is carried out. (e) The instruction that uses the TO instruction/ S. TO instruction/u \G cannot be used to write data to the CPU shared memory of other CPUs. "SP. UNIT ERROR (error code: 2115)" occurs if data is written to the CPU shared memory of other CPUs with the instruction that uses U \G. "SP. UNIT ERROR (error code: 2117)" occurs if data is written to the CPU shared memory of other PLCs with the instruction that uses the S. TO instruction. (f) The data of the CPU shared memory can be read with the FROM instruction or the instruction that uses U \G. (g) The instruction that uses U \G cannot be used to make access to a CPU not yet mounted. "SP UNIT ERROR (error code: 211)" occurs if access is made to a CPU not yet mounted with the instruction that uses U \G

282 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM 16.3 Interactive Communications between The Basic model QCPU and Motion CPU Control commands from the Basic model QCPU to the Motion CPU (Motion dedicated instructions) It is possible to issue control commands from the Basic model QCPU to the Motion CPU, and read and write device data with the Motion dedicated PLC instructions listed below. Instruction name S.SFCS SP.SFCS S.SVST SP.SVST S.CHGV SP.CHGV S.CHGT SP.CHGV S.CHGA SP.CHGA Description Requests startup of the motion SFC program. Requests the start of operations for the servo program. Changes the speed of the axes during positioning and JOG operations. Changes the torque control value during operation and suspension when in the real mode. Changes the current values of the halted axes, the synchronized encoder, and the cam axes. For example, it is possible to start up the Motion CPU's motion SFC from the Basic model QCPU with the S (P).SFCS instruction. Basic model QCPU Startup request Motion SFC Motion SFC S.SFCS instruction POINT The Basic model QCPU can execute up to 32 instructions of the "motion dedicated instructions" and "communication dedicated instructions between multiple CPUs except S(P).GINT instruction" simultaneously. However, if the Motion dedicated PLC instructions and communication dedicated instructions between multiple CPUs (omitting S (P).GINT instruction) are made at the same time, the instructions will be executed in order from the first instruction accepted. If there are 33 or more unexecuted instructions, an "OPERATION ERROR (error code: 417)" will be triggered. REMARK Refer to the Motion CPU Programming manual for details on and the necessity of use of the motion only instructions

283 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM Reading and writing device data(between Multiple CPU communication dedicated instruction) It is possible to read and write device data into the Motion CPU/PC CPU module from the Basic model QCPU with the the communication dedicated instructions between multiple CPUs listed in the table below. (Write/read from the motion CPU to the Basic model QCPU or from the PC CPU module to the Basic model QCPU cannot be performed.) Instruction name Description Motion CPU S.DDWR SP.DDWR Writes host CPU device data into other CPU devices. S.DDRD SP.DDRD S.GINT SP.GINT Reads other CPU device data into the host CPU. Requests start up of other CPU interruption programs. CPU module PC CPU module For example, Basic model QCPU device data can be written into the Motion CPU's device data with the S.DDWR instruction of the communication dedicated instruction between multiple CPUs. Basic model QCPU Motion CPU Reads the device memory S.DDWR instruction Device memory Writes in the device memory Device memory POINT The Basic model QCPU can execute up to 32 instructions of the "motion dedicated instructions" and "communication dedicated instructions between multiple CPUs except S(P).GINT instruction" simultaneously. However, if the Motion dedicated PLC instructions and communication dedicated instructions between multiple CPUs (omitting S (P).GINT instruction) are made at the same time, the instructions will be executed in order from the first instruction accepted. If there are 33 or more unexecuted instructions, an "OPERATION ERROR (error code: 417)" will be triggered. REMARK Refer to the Motion CPU Programming Manual for details on and the necessity of use of the communication dedicated instructions between multiple CPUs

284 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM 16.4 CPU Shared Memory The CPU shared memory is for exchanging data between CPU modules, and consists of 4,96 words between H and FFFH. The CPU shared memory consists of four areas; the host CPU operation information area, the system area, the automatic refresh area, and the user's free area. An area consisting of the number of automatic refresh points from CH is used as the automatic refresh area when the automatic refresh of device data is set up. The beginning of the user's free area starts from the address immediately after the end of the automatic refresh area. CH to D1H becomes the automatic refresh area if the number of automatic refresh points is 18 (12H points,) and the area after D2H becomes the user's free area. The configuration of the CPU shared memory and the necessity of accessing sequence programs are shown in the illustration below. H to 5FH 6H to BFH CH CPU shared memory Host CPU operation information area System area Automatic refresh area Writing Disable Host CPU Other CPUs 1 Reading Writing Reading 2 Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable to User's free area Enable Enable Disable Enable 1FFH REMARK 1: Use the TO instruction, S.TO instruction or intelligent function module device (/U \G ) to perform write from the Basic QCPU to the free user area of the host CPU. Refer to the manual of the Motion CPU for write to the free user area of the host PLC by the Motion CPU. Refer to the manual of the PC CPU module for write to the free user area of the host CPU by the PC CPU module. 2: Refer to the manuals of the corresponding CPU modules for read from the Motion CPU and PC CPU module

285 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM (1) Host CPU operation information area (H to 5FH) (a) The following information is stored in the host CPU with Multiple CPU Systems. These will all remain as and will not change in the case of Single CPU Systems. 1 CPU shared memory address H 1H 2H 3H 4H 5H 6H to 1H 11H to 1BH Information availability Table 16.1 List of host CPU operation information area Name Detail Description 2 Diagnostic error Time the diagnosis error occurred Error information identification code Common error information Individual error information Information availability flag Diagnostic error number Time the diagnosis error occurred Error information identification code Common error information Individual error information The area to confirm if information is stored in the host CPU's operation information area (1H to 1FH,) or not. : Information not stored in the host CPU's operation information area 1: Information stored in the host CPU's operation information area The numbers of errors during diagnostics is stored with BIN. The year and month that the error number was stored in the CPU shared memory's 1H address is stored with two digits of the BCD code. The day and time that the error number was stored in the CPU shared memory's 1H address is stored with two digits of the BCD code. The minutes and seconds that the error number was stored in the CPU shared memory's 1H address is stored with two digits of the BCD code. Stores an identification code to determine what error information has been stored in the common error information and individual error information. The common information corresponding with the number of the error during diagnostic is stored. The individual information corresponding with the number of the error during diagnostic is stored. Corresponding special register SD SD1 SD2 SD3 SD4 SD5 to SD15 SD16 to SD26 1CH Empty Cannot be used 1DH Switch status CPU switch status Stores the CPU module switch status. SD2 1EH LED status CPU-LED status Stores the CPU module's LED bit pattern. SD21 1FH CPU operation status CPU operation status Stores the CPU module's operation status. SD23 (b) The other CPU can read the data of the host CPU operation information area with the read instruction. However, since there is a delay in data update, use the read data for monitoring. REMARK 1: For the Motion CPU, 5H to 1CH of the host CPU's operation information area is not used. If 5H to 1CH of the host PLC's operation information area is read from the Motion CPU, it will be read as "." 2: Refer to the corresponding special registers for further details

286 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM (2) System area (6H to BFH) Area used by the system (OS) of the Basic model QCPU. (3) Automatic refresh area Area used for the automatic refresh of the Multiple CPU System. Write using the TO instruction, S.TO instruction or intelligent function module device (U \G ) cannot be performed. (4) User's free area Area to make communication between the CPU modules with the FROM instruction, TO instruction, S.TO instruction and/or instruction that uses intelligent function module device (U \G ) in the Multiple CPU System. The area later than the points set for the automatic refresh area is used. (When automatic refresh is not made, CH to 1FFH of the Basic model QCPU can be used as the free user area.)

287 17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES 17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES 17.1 Range of Control CPU Communications The relationship between control CPUs and control modules (I/O modules, intelligent function modules, special function modules) is the same as with independent CPU systems. There is no restriction to control the control module with the control CPU Range of Non-control CPU Communications It is possible for non-control CPUs to read the contents of the intelligent function module's buffer memory. It is also possible to load non-control module input (X) ON/OFF data and another CPU module output (Y) ON/OFF data with the PLC parameters. The ON/OFF data of the input modules/hybrid I/O modules controlled by the other CPUs can be used as interlocks of the host CPU, or the output statuses to the external devices controlled by the other CPUs can be checked, for example. However, the non-control CPUs cannot output ON/OFF data to the output modules/hybrid I/O modules/intelligent function modules acting as the non-controlled modules, and cannot perform write to the buffer memory of the intelligent function modules

288 17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES (1) Loading of input (X) from input modules, hybrid I/O modules and intelligent function modules The "Out of group input/output settings" in the Multiple CPU setting of the PLC parameter dialog box determine whether input can be loaded from the input modules, hybrid I/O modules and intelligent function modules being controlled by the other CPUs. Out of group input/output settings The input condition outside the group is taken: The output condition outside the group is taken: (a) When "Load input condition outside of group" has been set 1) Loads ON/OFF data from the input, hybrid I/O and intelligent function modules being controlled by the other CPUs by performing input refresh before a sequence program calculation starts. 2) Input (X) loading is performed for the modules mounted onto the following additional base unit slots. I/O allocation type Mounted module Remarks None Input module Intelligent function module Input module Input Output module Loads OFF data Hybrid I/O module Intelli. Intelligent function module 17 (b) 3) It is possible to load ON/OFF data from the input modules, hybrid I/O modules and intelligent function modules by direct access input. 4) Remote station input, such as empty slots, MELSECNET/H and CC- Link, cannot be loaded. Use automatic refresh of device data to use the ON/OFF input data for MELSECNET/H, CC-Link and other remote stations in other PLCs. When "Do not load input condition outside of group" has been set It is not possible to load ON/OFF data from the input modules, hybrid I/O modules and intelligent function modules being controlled by the other CPUs (remains at OFF)

289 17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES (2) Loading output (Y) The "Out of group input/output settings" in the Multiple CPU setting of the PLC parameter dialog box determine whether output can be loaded to the output modules, hybrid I/O modules and intelligent function modules being controlled by the other CPUs. Out of group input/output settings The input condition outside the group is taken: The output condition outside the group is taken: (a) When "Load output condition outside of group" has been set 1) Loads to the output (Y) of the host CPU the ON/OFF data that is output to the output, hybrid I/O and intelligent function modules by the other CPUs by performing output refresh before a sequence program calculation starts. 2) Output (Y) loading is performed for the modules mounted onto the following additional base unit slots. I/O allocation type None Output Intelli. Mounted module Output module Intelligent function module Input module Output module Hybrid I/O module Intelligent function module 3) The output of an empty slot or the CC-Link or other remote station cannot be loaded. When the ON/OFF data of the output to the CC-Link or other remote stations is to be used by the other CPUs, use the automatic refresh of the CPU shared memory to send to the other CPUs the ON/OFF data of the output to the remote stations. (b) When "Do not load output condition outside of group" has been set It is not possible to load the ON/OFF data output to the output modules, hybrid I/O modules and intelligent function modules by the other CPUs into the output (Y) of the host CPU (remains at OFF)

290 17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES (3) Output to output modules, hybrid I/O modules and intelligent function modules It is not possible to output ON/OFF data to non-controlled modules. ON/OFF will be performed within the Basic model QCPU when the output from the output modules, hybrid I/O modules and intelligent function modules controlled by the other CPUs with sequence programs, etc. have been set to ON/OFF, but this will not be output to the output modules, hybrid I/O modules or intelligent function modules. (4) Accessing the intelligent function module buffer memory (a) It is possible to read data from the buffer memory of intelligent function modules being controlled by other CPUs with the commands listed below. FROM command Commands that use intelligent function module devices (U \G ) Slot No. PLC No.1 Power supply Input module Output module Intelligent function module PLC No.1 PLC No.1 PLC No.1 PLC No.2 PLC No.2 PLC No.2 Basic model QCPU No.1 Motion CPU No.2 Intelligent function module Input module Output module Intelligent function module Control CPU settings Read from buffer memory can be performed. (b) Readable from the buffer memory with the FROM command and U \G The following instructions cannot be used to perform write to the buffer memory of the intelligent function modules being controlled by the other CPUs. TO instruction S.TO instruction Intelligent function module device (U \G ) Intelligent function module dedicated instruction An "SP UNIT ERROR (error code: 2116)" will be triggered if an attempt to write in the intelligent function module controlled by other CPUs is carried out Slot No. Power supply Basic model QCPU No.1 Motion CPU No.2 Input module PLC No.1 Output module PLC No.1 Intelligent function module PLC No.1 Intelligent function module PLC No.1 Input module PLC No.2 Output module PLC No.2 Intelligent function module PLC No.2 Control CPU settings Write to buffer memory cannot be performed. Not writable write in the buffer memory with the TO command and U \G

291 17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O MODULES AND INTELLIGENT FUNCTION MODULES (5) Accessing MELSECNET/H modules Only control CPUs can access MELSECNET/H modules. Link direct devices cannot be used in MELSECNET/H modules being controlled by other CPUs. "OPERATION ERROR (error code: 412)" occurs if a program that uses link direct devices is used in MELSECNET/H modules being controlled by other CPUs

292 18 PROCESSING TIME FOR MULTIPLE CPU SYSTEM BASIC MODEL QCPUs 18 PROCESSING TIME FOR MULTIPLE CPU SYSTEM BASIC MODEL QCPUs 18.1 Concept behind Scan Time The concept behind Multiple CPU System scanning time is the same as the Single CPU System. See Section 11.1 for details of the scan time concept. This chapter provides explanations on the factors to be added to the scan time calculated as explained in Section 11.1 and the method of calculating processing time when configuring Multiple CPU Systems. (1) I/O refresh time Input refresh time is calculated in accordance with the equation explained in Section The I/O refresh time for the following values only are prolonged when bus access overlaps with other CPUs. (Prolonged time) = (input points + output points) 16 N3 (number of other CPUs) ( s) Use the following values for N3 QCPU Q1CPU CPU type N3 Systems with only a main base Systems that include additional unit base units 8.7 s 21 s (2) Total value of command execution time Refer to the following manual for details on the processing time of special Multiple CPU commands, and the processing time for commands that have different processing times with Multiple CPU Systems. QCPU (Q mode)/qnacpu Programming Manual (Common Instructions) 18 (3) END process The following tables shows the END processing time. CPU type END processing time QCPU (.5 to.13) (number of other CPUs)ms Q1CPU (.5 to.13) (number of other CPUs)ms

293 18 PROCESSING TIME FOR MULTIPLE CPU SYSTEM BASIC MODEL QCPUs 18.2 Factor to Prolong the Scan Time The processing time for Multiple CPU Systems is prolonged in comparison with Single CPU Systems when the following functions are used. Add the following values to the values calculated in Sections 11.1 and 18.a to acquire the amount of time used by these functions. Multiple CPU System automatic refresh MELSECNET/H refreshing CC-Link automatic refresh (1) Automatic refresh of CPU shared memory (a) (b) The amount of time required to perform the refresh function set up with the Multiple CPU settings. This value is the total amount of time required for writing into the host CPU's CPU shared memory, and the amount of time required to read from other CPUs' CPU shared memories. These values are added when setting up the refresh settings with the PLC parameter Multiple CPU settings. The automatic refresh period of the CPU shared memory is calculated in the following equation. (Automatic refresh time) = (N1 + (transmitted word points) N2) + (N3 + (number of other CPUs) N4+ (received word points) N5) ( s) The number of received word points is the sum of the numbers of word points transmitted by the other CPUs. For example, when the host PLC is CPU No. 1, this value is the sum of the numbers of word points transmitted by CPU No. 2 and No. 3. For N1 to N5, use the values in the following table. CPU type N1 N2 N3 N4 N5 QCPU 63 s 1.13 s 63 s 161 s.88 s 18 Q1CPU 57 s 1.3 s 57 s 146 s.8 s (c) The amount of time required for the automatic refresh process will be prolonged by the following amount of time when processing is duplicated with the automatic refresh function on other CPUs. (Prolonged time) = 4 (transmitted word points) N6 (number of other CPUs) ( s) For N6, use the value in the following table. QCPU Q1CPU CPU type N6 Systems with only a main base Systems that include additional unit base units.54 s 1.3 s

294 18 PROCESSING TIME FOR MULTIPLE CPU SYSTEM BASIC MODEL QCPUs (2) MELSECNET/H refresh (a) (b) Refresh time between the Basic model QCPU and MELSECNET/H network module. Refer to the following manual for details on the refresh time for MELSECNET/H. Q Corresponding MESLECNET/H Network System Refresh Manual The amount of time required for the automatic refresh process will be prolonged only by the following amount of time when requests for refreshing are issued by other MELSECNET/H modules at the same time on a Multiple CPU System. (Prolonged time) = 4 (transmitted word points) N6 (number of other CPUs) ( s) The number of words transmitted/received is the total value of the following transferal data. Link refresh data (LB + LX + LY + SB) : + LW+ SW 16 Data transferred to the memory card's file register Transferal between data links Refer to the following table for N6 (LB + LX + LY + SB) : + LW+ SW 16 LB : ( + LW) 2 16 QCPU Q1CPU CPU type N6 Systems with only a Systems that include main base unit additional base units.54 s 1.3 s

295 19 STARTING UP THE MULTIPLE CPU SYSTEM 19 STARTING UP THE MULTIPLE CPU SYSTEM This Chapter explains the standard procedures for starting up the Multiple CPU System Flow-chart for Starting Up the Multiple CPU System Start Clarification of function sharing in Multiple CPU System Clarify the control and functions executed by each CPU. Purpose of each device and allocation Selection of module to be used To use automatic refresh of PLC share memory, reserve continuous refresh points. For automatic refresh of PLC share memory, see section Select the modules for realizing the functions executed in the Multiple CPU System. Installation of module Install the selected module to the main base unit and expansion base units. GX Developer startup Multiple CPU setting, control CPU setting and other parameter settings. Creation of sequence programs Parameter setting and program creation of Motion CPU Start the GX Developer Version 6 or later. For the starting method, refer to the GX Developer operating manual. Create parameters and sequence programs for CPU No.1 to No.4. For Multiple CPU settings and control CPU settings, see sections 16.1 and For automatic refresh of device data, see section Refer to the manual of the Motion CPU. Parameter setting and program creation of PC CPU module Refer to the manual of the PC CPU module. CPU power-on Select STOP at the RUN/STOP switch of the QCPU and turn off the RESET/L.CLR switch and turn on the PLC. 19 Connection of personal computer and Basic model QCPU (CPU No. 1) 1 Parameter and program writing Connect the personal computer where GX Developer has been started and the Basic model QCPU with the RS-232 cable. Write the parameters and programs. CPU No.1 QCPU resetting Set the RESET/L. CLR switch of the QCPU of the PLC No.1 in the RESET position. 1) 1: When the PC CPU module is used, installing GX Developer Version 8 or later into the PC CPU module enables the Basic model QCPU and GX Developer to be connected via the bus. For details, refer to the operating manual of GX Developer Version 8 or later

296 19 STARTING UP THE MULTIPLE CPU SYSTEM 1) Write of parameters and programs to Motion CPU Refer to the manual of the Motion CPU. Write of parameters and programs to PC CPU module Refer to the manual of the PC CPU module. Reset of Basic model QCPU as CPU No. 1 Move the RUN/STOP/RESET switch of the Basic model QCPU to the RESET position. RUN/STOP switch setting of all CPUs Cancellation of resetting of QCPU of CPU No.1 Status confirmation of all CPUs Confirmation and recovery of errors Select RUN at the RUN/STOP switch of the QCPU for PLC No.1 to No.3. Set the RESET/L. CLR switch of the QCPU for the PLC No.1 in the OFF position to cancel resetting. Check to see if a RUN status error has occurred with all PLCs on the Mulitple CPU System when the reset status for the CPU No.1 is canceled. If errors occurs, confirm the details and recover the situation with the GX Developer's system monitor. All CPUs debugged CPU No.1 to CPU No.3 on the Multiple CPU System debugged individually. Start of actual operations End

297 19 STARTING UP THE MULTIPLE CPU SYSTEM 19.2 Setting Up the Multiple CPU System Parameters (Multiple CPU Settings, Control CPU Settings) System configuration This section explains the procedures for setting up the Multiple CPU System parameters with GX Developer. Refer to the GX Developer's operation manual for details on setting up all other parameters. The following shows an example procedures for setting up the Multiple CPU System parameters. GX Developer Power supply Input module/plc No. 1 Output module/plc No. 2 Input module/plc No. 1 Output module/plc No. 2 Power supply Basic model QCPU/PLC No. 1 Intelligent function module/plc No. 2 Motion CPU/PLC No. 2 No CPU/PLC No. 3 Input module/plc No. 1 Input module/plc No. 1 Output module/plc No. 1 Intelligent function module/plc No. 1 Input module/plc No. 2 Output module/plc No

298 19 STARTING UP THE MULTIPLE CPU SYSTEM Creating new systems Start GX Developer started up Refer to GX Developer operating manual PC parameter window on the GX Developer opened Refer to GX Developer operating manual Select "Multiple CPU Settings" to display the Multiple CPU setup window. Setting the number of CPUs (required item) Sets the number of CPU modules to be mounted onto the main base unit with the Multiple CPU System. 1)

299 19 STARTING UP THE MULTIPLE CPU SYSTEM 1) Setting the operating mode (optional) Selects whether to halt operations for all CPUs or continue with operations when a stop error occurs. Default: Stop all CPUs upon a stop error of either CPU No.2 or No. 3. (Checked) For example, if the tick beside the "All station stop by stop error of CPU2" is removed, the operations for all other CPUs will continue even when an error occurs in the CPU No.2. The operation mode for the CPU No.1 cannot be changed. Out of the group input/output settings (optional) Sets whether or not the I/O status of non-control CPUs are acquired. Default:Default: Do not acquire. (No check) Refresh setting (option) Set the device that will make data communication by automatic refresh between the CPU modules and the number of points of the automatic refresh area. The number of points of the automatic refresh area, starting from the device number set as the first device are used consecutively. One point of the automatic refresh area occupies the number of points in the following table. Device B, M, Y D, W, R, ZR Occupied Points 16 points 1 point 2)

300 19 STARTING UP THE MULTIPLE CPU SYSTEM 2) Selects "CPU (Empty)" for the slots on which CPU modules are not to be mounted by type. Select "Detailed Settings" on the I/O assignment window to display the detail settings window. Control CPU settings (required item) Select the control CPU (CPU No. 1 to No. 3) for each slot. For the intelligent function module of function version A, set PLC No. 1 as the control CPU. Setup of parameters other than the Multiple CPU System settings. Set parameters written onto the hard disk or floppy disk. End

301 19 STARTING UP THE MULTIPLE CPU SYSTEM Using existing preset Multiple CPU settings and I/O allocations Start GX Developer started up Refer to the GX Developer's operation manual Opens the GX Developer's PC parameter setup window. Select "Multiple CPU settings" to display the Multiple CPU setup window. Transferring Multiple CPU settings Click on "Diversion Multiple CPU parameters." Setting up transferred projects Select the project into which existing Multiple CPU settings and I/O allocations are to be transferred. Click on "Open." 1)

302 19 STARTING UP THE MULTIPLE CPU SYSTEM 1) The Multiple CPU settings and I/O Assignment Setting data are read and written into the specified project when "OK" is selected. Confirming the Multiple CPU settings When changing the CPU devices in the "Refresh settings", enter the device number after it has been changed. (" " indicates the item can be changed.) Confirm the I/O Assignment and standard settings on the I/O Allocation Window. Select "Detailed Settings" to display the detailed setting window. Confirm the control CPU settings. 2)

303 19 STARTING UP THE MULTIPLE CPU SYSTEM 2) Setup of parameters other than the Multiple CPU System settings. Set parameters written onto the hard disk or floppy disk. End

304 APPENDICES APPENDICES APPENDIX 1 Special Relay List Special relays, SM, are internal relays whose applications are fixed in the programmable controller. For this reason, they cannot be used by sequence programs in the same way as the normal internal relays. However, they can be turned ON or OFF as needed in order to control the CPU and remote I/O modules. Item Number Name Meaning Explanation Set by (When set) The headings in the table that follows have the following meanings. Function of Item Indicates the number of the special relay. Indicates the name of the special relay. Indicates the nature of the special relay. Contains detailed information about the nature of the special relay. Indicates whether the relay is set by the system or user, and, if it is set by the system, when setting is performed. <Set by> S : Set by system U : Set by user (in sequence program or test operation at a peripheral device) S/U : Set by both system and user <When set> indicated only if setting is done by system. Each END : Set during each END processing Initial : Set only during initial processing (when power supply is turned ON, or when going from STOP to RUN) Status change : Set only when there is a change in status Error : Set when error is generated Instruction execution : Set when instruction is executed Request : Set only when there is a user request (through SM, etc.) For details on the following items, see these manuals: Networks Far Q MELSECNET/H Network System Reference Manual (PLC to PLC network) APP App - 1 App - 1

305 APPENDICES APP (1) Diagnostic Information Special Relay List Number Name Meaning Explanation SM SM1 SM5 SM16 Diagnostic errors Self-diagnosis error Error common information Error individual information OFF : No error ON : Error OFF : No self-diagnosis errors ON : Self-diagnosis OFF : No error common information ON : Error common information OFF : No error common information ON : Error common information SM5 Error reset OFF ON : Error reset SM51 SM52 SM53 SM56 SM6 SM61 Battery low latch Battery low AC/DC DOWN detection Operation Errors Blown fuse detection I/O module verification error Annunciator SM62 detection Serial communication SM1 function using flag Communication SM11 protocol status flag SM11 Protocol error SM111 SM112 Communication status Error information clear SM113 Overrun error SM114 Parity error SM115 Framing error OFF : Normal ON : Battery low OFF : Normal ON : Battery low OFF : AC/DC DOWN not detected ON : AC/DC DOWN detected OFF : Normal ON : Operation error OFF : Normal ON : Module with blown fuse OFF : Normal ON : Error Turns ON if an error occurs as a result of diagnosis. (Includes when an annunciator is ON) Remains ON if the condition is restored to normal thereafter. Turns ON if an error occurs as a result of diagnosis. (Does not include when an annunciator is ON) Remains ON if the condition is restored to normal thereafter. When SM is ON, ON if there is error common information When SM is ON, ON if there is error individual information Conducts error reset operation See Section 11.3 for further information ON if battery voltage at CPU module drops below rated value. Remains ON if the battery voltage returns to normal thereafter. Synchronizes with the ERR. LED. Same as SM51, but goes OFF subsequently when battery voltage returns to normal. Turns ON if an instantaneous power failure of within 2ms occurs during use of the AC power supply module. Reset when power is switched OFF, then ON. Turns ON if an instantaneous power failure of within 1ms occurs during use of the DC power supply module. Reset when power is switched OFF, then ON. ON when operation error is generated Remains ON if the condition is restored to normal thereafter. Turns ON if there is at least one output module whose fuse has blown. Remains ON if the condition is restored to normal thereafter. Turns ON if the I/O module differs from the status registered at power on. Remains ON if the condition is restored to normal thereafter. OFF : Not detected Goes ON if even one annunciator (F) goes ON. ON : Detected OFF : Serial communication function is not used. ON : Serial communication function is used. OFF : GX Developer ON : MC protocol communication device OFF : Normal ON : Abnormal OFF : Normal ON : Abnormal ON : Cleared OFF : Normal ON : Abnormal OFF : Normal ON : Abnormal OFF : Normal ON : Abnormal Stores the setting of whether the serial communication function is used or not in the serial communication setting parameter. Stores whether the device that is communicating via the RS-232 interface is GX Developer or MC protocol communication device. Turns ON when an abnormal protocol was used to make communication in the serial communication function. Remains ON if the condition is restored to normal thereafter. Turns ON when the mode used to make communication was different from the setting in the serial communication function. Remains ON if the condition is restored to normal thereafter. Turns ON when the error codes stored in SM11, SM111, SD11 and SD111 are cleared. (Activated when turned from OFF to ON) Turns ON when an overrun error occurred in the serial communication error. Turns ON when a parity error occurred in the serial communication error. Turns ON when a framing error occurred in the serial communication error. Set by (When Set) S (Error) S (Error) S (Error) S (Error) U S (Error) S (Error) S (Error) S (Error) S (Error) S (Error) S (Instruction execution) S (Power-on or reset) S (RS232 communication) S (Error) S (Error) U S (Error) S (Error) S (Error) Corresponding CPU App - 2 App - 2

306 APPENDICES (2) System information Number Name Meaning Explanation SM23 STOP contact STOP status Goes ON at STOP status SM24 PAUSE contact PAUSE status Goes ON at PAUSE status PAUSE enable coil Device test SM26 request acceptance status SM21 Clock data set request SM211 Clock data error SM213 SM24 SM241 SM242 SM244 SM245 SM246 SM315 SM32 SM321 SM322 SM323 SM324 Clock data read request No. 1 CPU reset flag No. 2 CPU reset flag No. 3 CPU reset flag No. 1 CPU error flag No. 2 CPU error flag No. 3 CPU error flag Communication reserved time delay enable/disable flag Presence/ absence of SFC program Start/stop of SFC program Starting status of SFC program Presence/ absence of continuous transition of all blocks Continuous transition inhibit flag OFF : PAUSE disabled ON : PAUSE enabled OFF : Device test not yet executed ON : Device test executed OFF : Ignored ON : Set request OFF : No error ON : Error OFF : Ignored ON : Read request OFF : No. 1 CPU reset cancel ON : No. 1 CPU resetting OFF : No. 2 CPU reset cancel ON : No. 2 CPU resetting OFF : No. 3 CPU reset cancel ON : No. 3 CPU resetting OFF : No. 1 CPU normal ON : No. 1 CPU during stop error OFF : No. 2 CPU normal ON : No. 2 CPU during stop error OFF : No. 3 CPU normal ON : No. 3 CPU during stop error OFF : Without delay ON : With delay OFF: SFC program absence ON : SFC program presence OFF: SFC program nonexecution (stop) ON : SFC program execution (start) OFF: Initial start ON : Continued start OFF: Without continuous transition ON : With continuous transition OFF: When transition is executed ON : When transition is not executed PAUSE status is entered if this relay is ON when the remote PAUSE contact goes ON Comes ON when the device test mode is executed on GX Developer. When this relay goes from OFF to ON, clock data being stored from SD21 through SD213 after execution of END instruction for changed scan is written to the clock device. ON when error is generated in clock data (SD21 through SD213) value, and OFF if no error is detected. When this relay is ON, clock data is read to SD21 through SD213 as BCD values. Goes OFF when reset of the No. 1 CPU is canceled. Comes ON when the No. 1 CPU is resetting (including the case where the CPU is removed from the base). The other CPUs are also put in reset status. Goes OFF when reset of the No. 2 CPU is canceled. Comes ON when the No. 2 CPU is resetting (including the case where the CPU is removed from the base). The other CPUs result in "MULTI CPU DOWN" (error code: 7). Goes OFF when reset of the No. 3 CPU is canceled. Comes ON when the No. 3 CPU is resetting (including the case where the CPU is removed from the base). The other CPUs result in "MULTI CPU DOWN" (error code: 7). Goes OFF when the No. 1 CPU is normal (including a continuation error). Comes ON when the No. 1 CPU is during a stop error. Goes OFF when the No. 2 CPU is normal (including a continuation error). Comes ON when the No. 2 CPU is during a stop error. Goes OFF when the No. 3 CPU is normal (including a continuation error). Comes ON when the No. 3 CPU is during a stop error. This flag is enabled when the time reserved for communication processing is set in SD315. Turns ON to delay the END processing by the time set in SD315 in order to perform communication processing. (The scan time increases by the period set in SD315.) Turns OFF to perform the END processing without a delay of the time set in SD315 when there is no communication processing. (Defaults to OFF) Turns ON when an SFC program is registered. OFF when an SFC program is not registered. The same value as in SM32 is set as the initial value. (Automatically turns ON when the SFC program is present.) When this relay is turned from ON to OFF, the execution of the SFC program is stopped. When this relay is turned from OFF to ON, the execution of the SFC program is resumed. The SFC program starting mode in the SFC setting of the PLC parameter dialog box is set as the initial value. At initial start: OFF At continued start: ON Set the presence/absence of continuous transition for the block where "Continuous transition bit" of the SFC data device has not been set. OFF during operation in the continuous transition mode or during continuous transition, and ON when continuous transition is not executed. Always ON during operation in the no continuous transition mode. Set by (When Set) S (Status change) S (Status change) U S (Request) U S (Request) U S (Status change) U S (Initial) S (Initial) U S (Initial) U U S (Status change) Applicable CPU Serial No or later Serial No or later App - 3 App - 3

307 APPENDICES Number Name Meaning Explanation SM325 SM326 SM327 SM328 Block stop-time output mode SFC device clear mode Output at execution of end step Clear processing mode when end step is reached OFF: OFF ON : Held OFF: Device cleared ON : Device held OFF: Held step output OFF ON : Held step output held OFF: Clear processing is performed. ON : Clear processing is not performed. Select whether the coil outputs of the active steps are held or not at the time of a block stop. As the initial value, the output mode at a block stop in the parameter is OFF when the coil outputs are OFF, and ON when the coil outputs are held. When this relay turns OFF, the coil outputs are all turned OFF. When this relay turns ON, the coil outputs are held. Select the device status at the time of switching from STOP to program write to RUN. (All devices except the step relay) When this relay turns OFF, the coil outputs of the steps (SC, SE, ST) being held when transition is established are turned OFF when the end step is reached. Select whether clear processing will be performed or not if active steps other than the ones being held exist in the block when the end step is reached. When this relay turns OFF, all active steps are forcibly terminated to terminate the block. When this relay is ON, the execution of the block is continued asis. If active steps other than the ones being held do not exist when the end step is reached, the steps being held are terminated to terminate the block. Set by (When Set) S (Initial) U U U U Applicable CPU Serial No or later (3) System clocks/counters Number Name Meaning Explanation SM4 SM41 SM42 SM43 Always ON Always OFF ON for 1 scan only after RUN After RUN, OFF for 1 scan only SM41.1 second clock SM411.2 second clock SM412 1 second clock SM413 2 second clock SM414 2n second clock SM42 User timing clock No. SM421 User timing clock No.1 SM422 User timing clock No.2 SM423 User timing clock No.3 SM424 User timing clock No.4 ON OFF ON OFF ON OFF ON OFF.5 sec..1sec..5 sec. 1 sec. n sec. n2 scan.5 sec..1sec..5 sec. 1 sec. n sec. n1 scan 1 scan 1 scan n2 scan Normally is ON Normally is OFF After RUN, ON for 1 scan only. This connection can be used for scan execution type programs only. After RUN, OFF for 1 scan only. This connection can be used for scan execution type programs only. Repeatedly changes between ON and OFF at each designated time interval. When power supply is turned OFF, or reset is performed, goes from OFF to start. Note that the ON-OFF status changes when the designated time has elapsed during the execution of the program. This relay alternates between ON and OFF at intervals of the time (unit: s) specified in SD414. Starts from OFF when the PLC is powered ON or the CPU module is reset. Note that when the specified time is reached, the ON/OFF status changes even during program execution. Relay repeats ON/OFF switching at fixed scan intervals. When power supply is turned ON, or reset is performed, goes from OFF to start. The ON/OFF intervals are set with the DUTY instruction. DUTY n1 n2 SM42 Set by (When Set) S (Every END processing) S (Every END processing) S (Every END processing) S (Every END processing) S (Status change) S (Status change) S (Every END processing) Applicable CPU App - 4 App - 4

308 APPENDICES (4) I/O refresh Number Name Meaning Explanation SM58 Program to program I/O refresh OFF: Not refreshed ON : Refreshed When this special relay is turned ON, I/O refresh is performed after execution of the first program, and the next program is then executed. When a sequence program and an SFC program are to be executed, the sequence program is executed, I/O refresh is performed, and the SFC program is then executed. Set by (When Set) U Corresponding CPU Serial No or later (5) Memory cards Number Name Meaning Explanation SM62 SM621 Drive 3/4 usable flags Drive 3/4 protect flag SM622 Drive 3 flag SM623 Drive 4 flag SM64 File register use SM66 Boot operation OFF : Unusable ON : Use enabled OFF : No protect ON : Protect OFF : No drive 3 ON : Drive 3 present OFF : No drive 4 ON : Drive 4 present OFF : File register not in use ON : File register in use OFF : Program memory execution ON : Boot operation in progress Always ON Always OFF Always ON Always ON Goes ON when file register is in use (QCPU, Q1CPU only) Goes ON while boot operation is in process Set by (When Set) S (Initial) S (Initial) S (Initial) S (Initial) S (Status change) S (Status change) Applicable CPU (6) Instruction-Related Special Relays Number Name Meaning Explanation SM7 SM72 SM73 SM74 SM715 SM721 SM722 SM774 SM775 SM794 OFF : Carry OFF Carry flag ON : Carry ON OFF : Search next Search method ON : 2-part search OFF : Ascending order Sort order ON : Descending order OFF : Non-match found Block comparison ON : All match : During DI EI flag 1 : During EI File being OFF : File not accessed accessed ON : File being accessed BIN/DBIN instruction error disabling flag PID bumpless processing (for exact differential) Selection of link refresh processing during COM instruction execution PID bumpless processing (for inexact differential) OFF : Error detection performed ON : Error detection not performed OFF: Matched ON : Not matched OFF : Performs link refresh ON : No link refresh performed OFF: All refresh processings are executed. ON : Refresh set in SD778 is performed. OFF: Matched ON : Not matched Carry flag used in application instruction Designates method to be used by search instruction. Data must be arranged for 2-part search. The sort instruction is used to designate whether data should be sorted in ascending order or in descending order. Goes ON when all data conditions have been met for the BKCMP instruction. ON when EI instruction is being executed. Switches ON while a file is being accessed by the S.FWRITE, S.FREAD, COMRD, PRC, or LEDC instruction. Turned ON when "OPERATION ERROR" is suppressed for BIN or DBIN instruction. Specify whether the set value (SV) will be matched with the process value (PV) or not in the manual mode. Select whether or not to perform link refresh processing in cases where only general data processing will be conducted during the execution of the COM instruction. Select whether all refresh processings or the refresh processing set in SD778 will be performed when the COM instruction is executed. Specify whether the set value (SV) will be matched with the process value (PV) or not in the manual mode. Set by (When Set) S (Instruction execution) U U S (Instruction execution) S (Instruction execution) S (Status change) U U U U U Applicable CPU Serial No or later Serial No or later Serial No or later App - 5 App - 5

309 APPENDICES APPENDIX 2 Special Register List The special registers, SD, are internal registers with fixed applications in the programmable controller. For this reason, it is not possible to use these registers in sequence programs in the same way that normal registers are used. However, data can be written as needed in order to control the CPU module. Data stored in the special registers are stored as BIN values if no special designation has been made to it. The headings in the table that follows have the following meanings. Item Number Name Meaning Explanation Set by (When set) Function of Item Indicates special register number Indicates name of special register Indicates contents of special register Discusses contents of special register in more detail Indicates whether the relay is set by the system or user, and, if it is set by the system, when setting is performed. <Set by> S : Set by system U : Set by user (sequence program or test operation from GX Developer or the like) S/U : Set by both system and user <When set> Indicated only for registers set by system Each END : Set during each END processing Initial : Set only during initial processing (when power supply is turned ON, or when going from STOP to RUN) Status change : Set only when there is a change in status Error : Set when error occurs Instruction execution : Set when instruction is executed Request : Set only when there is a user request (through SM, etc.) For details on the following items, see these manuals: Networks For Q MELSECNET/H Network System Reference Manual (PLC to PLC network) App - 6 App - 6

310 APPENDICES (1) Diagnostic Information Special Register List Number Name Meaning Explanation SD SD1 SD2 SD3 SD4 Diagnostic errors Clock time for diagnosis error occurrence Error information categories Diagnosis error code Clock time for diagnosis error occurrence Error information category code Error codes for errors found by diagnosis are stored as BIN data. Contents identical to latest fault history information. Year (last two digits) and month that SD data was updated is stored as BCD 2- digit code. (Example) b15 to b8 b7 to b : October, 1995 Year ( to 99) Month (1 to 12) H951 The day and hour that SD was updated is stored as BCD 2-digit code. b15 to b8 b7 to b (Example) : 1 p.m. on 25th Day (1 to 31) Hour ( to 23) H251 The minute and second that SD data was updated is stored as BCD 2-digit code. (Example) b15 to b8 b7 to b : 35 min. 48 sec. Minutes ( to 59) Seconds ( to 59) (past the hour) H3548 Category codes which help indicate what type of information is being stored in the common information areas (SD5 through SD15) and the individual information areas (SD16 through SD26) are stored here. b15 to b8 b7 to b Individual information category codes Common information category codes The common information category codes store the following codes: : No error 1 : Unit/module No./ PLC No./Base No. 2 : File name/drive name 3 : Time (value set) 4 : Program error location The individual information category codes store the following codes: : No error 1 : (Open) 2 : File name/drive name 3 : Time (value actually measured) 4 : Program error location 5 : Parameter number 6 : Annunciator number Set by (When set) S (Error) S (Error) S (Error) Corresponding CPU App - 7 App - 7

311 APPENDICES Special Register List (Continued) Number Name Meaning Explanation SD5 SD6 SD7 SD8 SD9 SD1 SD11 SD12 SD13 SD14 SD15 Error common information Error common information Error common information Error common information Common information corresponding to the error codes (SD) is stored here. The following four types of information are stored here: 1 Slot No. Number SD5 Meaning Slot No./Base No. 1 2 SD6 SD7 SD8 SD9 SD1 SD11 SD12 SD13 SD14 SD15 I/O No. (Vacant) 3 (Not used for base No.) 1: In a multiple CPU system, the slot No. or CPU No. is stored depending on the error that occurred. Slot in the multiple CPU system indicates the slot on the right-hand side of the CPU module at the right end. (Refer to the error code to check which No. is stored.) No. 1 CPU: 1, No. 2 CPU: 2, No. 3 CPU: 3 2: When 255 is stored into SD5, it indicates that an instruction, etc. has been executed for the module later than the one on the last slot where a module can be mounted. 3: When FFFFH is stored in SD6 (I/O No.), the I/O No. may not be identified due to I/O No. overlapping or like in the I/O assignment parameter. Use SD5 to identify the error location. 2 File name/drive name Number SD5 SD6 SD7 SD8 SD9 SD1 SD11 SD12 SD13 SD14 SD15 4: For the extension, refer to REMARKS on the next page. Meaning Drive File name (ASCII code: 8 characters) Extension 4 2EH(.) (ASCII code: 3 characters) (Vacant) 3 Time (value set) Number Meaning SD5 Time : 1 µs units ( to 999 µs) SD6 Time : 1 ms units ( to ms) SD7 SD8 SD9 SD1 SD11 (Vacant) SD12 SD13 SD14 SD15 4 Program error location Number Meaning SD5 SD6 SD7 SD8 SD9 SD1 Extension 4 SD11 Pattern SD12 SD13 SD14 SD15 5: Pattern data File name (ASCII code: 8 characters) 2EH(.) (ASCII code: 3 characters) 5 Block No. Step No./transition No. Sequence step No. (L) Sequence step No. (H) to to (Not used) (Bit number) (Example) File name= MAIN. QPG b15 to b8 b7 to b 41H(A) 4DH(M) 4EH(N) 49H(I) 2H(SP) 2H(SP) 2H(SP) 2H(SP) 51H(Q) 2EH(.) 47H(G) 5H(P) SFC block specified (1)/not specified () SFC step specified (1)/not specified () SFC transition specified (1)/not specified () Set by (When set) S (Error) Corresponding CPU App - 8 App - 8

312 APPENDICES Special Register List (Continued) Number Name Meaning Explanation SD16 SD17 SD18 SD19 SD2 SD21 SD22 SD23 SD24 SD25 SD26 Error individual information Error individual information Individual information corresponding to error codes (SD) is stored here. 1 File name/drive name (Example) File name= MAIN. QPG Number SD16 SD17 SD18 SD19 SD2 SD21 SD22 SD23 SD24 SD25 SD26 Meaning Drive File name (ASCII code: 8 characters) Extension 4 2EH(.) (ASCII code: 3 characters) (Vacant) 2 Time (value actu1ally measured) Number SD16 SD17 Meaning Time : 1 µs units ( to 999 µs) Time : 1 ms units ( to ms) SD18 SD19 SD2 SD21 SD22 (Vacant) SD23 SD24 SD25 SD26 3 Program error location Number Meaning SD16 SD17 SD18 File name (ASCII code: 8 characters) SD19 SD2 Extension 4 2EH(.) SD21 (ASCII code: 3 characters) SD22 SD23 Pattern Block No. 5 SD24 SD25 SD26 Step No./transition No. Sequence step No. (L) Sequence step No. (H) 5: Pattern data to to (Bit number) b15 to b8 b7 to b 41H(A) 4DH(M) 4EH(N) 49H(I) 2H(SP) 2H(SP) 2H(SP) 2H(SP) 51H(Q) 2EH(.) 47H(G) 5H(P) (Not used) SFC block specified (1)/not specified () SFC step specified (1)/not specified () SFC transition specified (1)/not specified () 4 Parameter number 5 Annunciator number 6 Intelligent function module parameter error Number Meaning Number Meaning Number Meaning SD16 Parameter No. 6 SD16 No. SD16 Parameter No. 6 SD17 SD17 SD17 Error code for intelligent SD18 SD18 function module SD19 SD19 SD18 SD2 SD2 SD19 SD21 SD21 SD2 (Vacant) (Vacant) SD22 SD22 SD21 SD23 SD23 SD22 (Vacant) SD24 SD24 SD23 SD25 SD25 SD24 SD26 SD26 SD25 SD26 6 For details of the parameter numbers, refer to the user's manual (Functions Exlanation, Proguramming fundamentals) of the CPU module used. Set by (When set) S (Error) Corresponding CPU REMARK 4 Extensions are shown below. SD1 SD11 Higher8 bits Lower8 bits Higher8 bits Extension name File type 51H 5H 41H QPA Parameters 51H 5H 47H QPG Sequence program/sfc program 51H 43H 44H QCD Device comment 51H 44H 52H QDR File register App - 9 App - 9

313 APPENDICES Special Register List (Continued) Number Name Meaning Explanation SD5 SD51 SD52 SD53 SD6 SD61 SD62 SD63 Error reset Battery low latch Battery low AC/DC DOWN detection Blown fuse number I/O module verification error number Annunciator number Number of annunciators Error number that performs error reset Bit pattern indicating where battery voltage drop occurred Bit pattern indicating where battery voltage drop occurred Number of times for AC/DC DOWN Number of module with blown fuse I/O module verification error module number Annunciator number Number of annunciators Stores error number that performs error reset Set by (When set) When battery low occurs, the corresponding bit turns to 1 (ON). Remains 1 if the battery voltage returns to normal thereafter. b15 to b S (Error) < > CPU error Same configuration as SD51 above Turns to (OFF) when the battery voltage returns to normal thereafter. Every time the input voltage falls to or below 85% (AC power)/65% (DC power) of the rating during calculation of the CPU module, the value is incremented by one and stored in BIN. Value stored here is the lowest station I/O number of the module with the blown fuse. The lowest I/O number of the module (F number) where the I/O module verification number took place. The first annunciator number to be detected is stored here. Stores the number of annunciators searched. U S (Error) S (Error) S (Error) S (Error) Corresponding CPU SD64 SD65 SD66 SD67 SD68 SD69 When F goes ON due to OUT F or SET F, the F numbers which go progressively ON from SD64 through SD79 are registered. The F numbers turned OFF by RST F are deleted from SD64 - SD79, and the F numbers stored after the deleted F numbers are shifted to the preceding registers. After 16 annunciators have been detected, detection of the 17th will not be stored from SD64 through SD79. SET F5 SET F25 SET F99 RST F25 SET F15 SET F7 SET F65 SET SET SET SET RST F38 F11F151F21F5 SD7 SD71 SD72 SD73 SD74 SD75 SD76 SD77 SD78 Table of detected annunciator numbers Annunciator detection number SD (Number detected) SD (Number of annunciators detected) SD64 SD65 SD66 SD67 SD68 SD SD SD SD72 SD73 SD74 SD75 SD76 SD77 SD78 SD79 21 (Number detected) S (Instruction execution) SD79 App - 1 App - 1

314 APPENDICES Special Register List (Continued) Number Name Meaning Explanation SD1 Transmission speed storage area Stores the transmission speed specified in the serial communication setting. K96: 9.6kbps, K192: 19.2kbps, K384: 38.4kbps, K576: 57.6kbps, K1152: 115.2kbps b15 to b6 b5 b4 b3 to b Set by (When set) S (Poweron or reset) Corresponding CPU SD11 Communicatio n setting storage area Stores the communication setting specified in the serial communication setting. Sumcheck yes/no Online program correction setting : No : Disabled 1: Yes 1: Enabled S (Poweron or reset) SD12 SD11 SD111 SD13 SD131 SD132 SD133 SD134 SD135 SD136 SD137 SD15 SD151 SD152 SD153 SD154 SD155 Message waiting time storage area Data sending result storage area Data receiving result storage area Fuse blown module I/O module verification error Stores the message waiting time specified in the serial communication setting. Stores the data sending result when the serial communication function is used. Stores the data receiving result when the serial communication function is used. Bit pattern in units of 16 points, indicating the modules whose fuses have blown : No blown fuse 1: Blown fuse present Bit pattern, in units of 16 points, indicating the modules with verification errors. : No I/O verification errors 1: I/O verification error present : Since the data is used by the system, it is undefined. : No waiting time 1 to FH: Waiting time (unit: 1ms) Defaults to. The error code at data transmission is stored. Stores the error code at the time of data receiving. The numbers of output modules whose fuses have blown are input as a bit pattern (in units of 16 points). (If the module numbers are set by parameter, the parameter-set numbers are stored.) Also detects blown fuse condition at remote station output modules b15 b14 b13 b12 b11b1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b SD13 1 (YC) 1 (Y8) SD131 1 (Y1F) 1 (Y1A) SD137 1 (Y1F 1 (Y1F B) Indicates a blown fuse Not cleared even if the blown fuse is replaced with a new one. This flag is cleared by error resetting operation When the power is turned on, the module numbers of the I/O modules whose information differs from the registered I/O module information are set in this register (in units of 16 points). (If the I/O numbers are set by parameter, the parameter-set numbers are stored.) Also detects I/O module information b15 b14 b13 b12 b11b1 b9 b8 b7 b6 b5 b4 b3 b2 b1 b 1 SD15 X Y ( ) 1 SD151 X Y ( 19) 1 SD157 X Y ( 1FE) 3) S (Poweron or reset) S (Error) S (Error) S (Error) S (Error) SD156 SD157 Indicates an I/O module verification error Not cleared even if the blown fuse is replaced with a new one. This flag is cleared by error resetting operation App - 11 App - 11

315 APPENDICES (2) System information Special Register List Number Name Meaning Explanation The CPU module switch status is stored in the following format: b15 to b8 b7 to b4 b3 to b Set by (When set) Corresponding CPU SD2 Status of switch Status of CPU switch Vacant : CPU switch status : RUN 1: STOP S(Every END processing) 2 : Memory card switch Always OFF SD21 LED status Status of CPU-LED The following bit patterns are used to store the statuses of the LEDs on the CPU module: b15 to b4 b3 to b Vacant 2 1 S (Status change) 1 : RUN 2 : ERR. The CPU module operating status is stored as indicated in the following figure: b15 to b12b11 to b8 b7 to b4 b3 to b 2 1 SD23 Operating status of CPU Operating status of CPU 1 : Operating status of CPU :RUN 1 :Vacant 2 :STOP 3 :PAUSE 2 : STOP/PAUSE cause :RUN/STOP/RESET switch 1 :Remote contact 2 :GX Developer/Serial Communication Module from some other remote source 3 :Internal program instruction Note: Priority is earliest first 4 :Errors S (Every END processing) SD27 Priorities 1 to 4 Set the ON (flicker) priorities of the LED display section at error occurrence with error item Nos. Applicable to only the annunciator (error item No. 7). The priority setting area is as shown below. SD28 Priorities 5 to 8 SD29 LED display priority Priorities 9 to 1 b15 to b12b11 to b8 b7 to b4 b3 to b SD27 SD28 SD29 Priority 4 Priority 3 Priority 2 Priority 1 Priority 8 Priority 7 Priority 6 Priority 5 Priority 1 Priority 9 Default Value SD27 = H SD28 = 7H SD29 = H U Serial number 4122 or later With "7" set to any of priorities 1 to 1, the ERR. LED turns ON when the annunciator turns ON. Without "7" being set to any of priorities 1 to 1, the ERR. LED will not turn ON if the annunciator turns ON. App - 12 App - 12

316 APPENDICES Special Register List (Continued) Number Name Meaning Explanation SD21 Clock data SD211 Clock data SD212 Clock data Clock data (year, month) Clock data (day, hour) Clock data (minute, second) The year (last two digits) and month are stored as BCD code at SD21 as shown below: b15 to b12b11 to b8 b7 to b4 b3 to b Example : July H Year Month The day and hour are stored as BCD code at SD211 as shown below: b15 to b12b11 to b8 b7 to b4 b3 to b Example : 31st, 1 a.m. 311H Day Hour The minutes and seconds (after the hour) are stored as BCD code at SD212 as shown below: b15 to b12b11 to b8 b7 to b4 b3 to b Example : 35 min., 48 sec. 3548H Minute Second Stores the year (two digits) and the day of the week in SD213 in the BCD code format as shown below: b15 to b12b11 to b8 b7 to b4 b3 to b Example : 1993,Friday 195H Set by (When set) S/U (Request) Corresponding CPU SD213 Clock data Clock data (day of week) Higher digits of year ( to 99) Day of week Sunday 1 Monday 2 Tuesday 3 Wednesday S/U (Request) 4 Thursday 5 Friday 6 Saturday SD22 SD221 SD222 SD223 SD224 SD225 SD226 SD227 LED display data Display indicator data Stores the message (16 characters of ASCII data) at error occurrence (including annunciator ON). b15 to b8 b7 to b SD22 SD221 SD222 15th character from the right 16th character from the right 13th character from the right 14th character from the right 11th character from the right 12th character from the right SD223 SD224 SD225 SD226 SD227 9th character from the right 7th character from the right 5th character from the right 3rd character from the right 1st character from the right 1th character from the right 8th character from the right 6th character from the right 4th character from the right 2nd character from the right The display device data at PRG CHK is not stored. S (When changed) SD24 Base mode SD241 SD242 SD243 SD244 No. of expansion bases : Automatic mode 1: Detail mode : Basic only 1 to 4: No. of expansion bases Base type Installed Q differentiation base presence/ : Base not installed absence 1: Q B is installed No. of base slots (Operation status) No. of base slots Stores the base mode. Stores the maximum number of the expansion bases being installed. Fixed to b4 to b2 b1 b Main base 1st expansion base 2nd expansion base to 4th expansion base b15 to b12 b11 to b8 b7 to b4 b3 to b SD243 Expansion 3 Expansion 2 Expansion 1 Main SD244 Fixed to Expansion 4 As shown above, each area stores the number of slots being installed. (Number of set slots when parameter setting has been made) S (Initial) S (Initial) S (Initial) S (Initial) App - 13 App - 13

317 APPENDICES Special Register List (Continued) Number Name Meaning Explanation SD245 SD246 SD25 SD254 No. of base slots (Mounting No. of base slots status) Loaded maximum I/O Loaded maximum I/O No. Number of modules installed b15 to b12 b11 to b8 b7 to b4 b3 to b SD245 Expansion 3 Expansion 2 Expansion 1 Main SD246 Fixed to Expansion 4 As shown above, each area stores the number of module-mounted slots of the base unit (actual number of slots of the installed base unit). When SM25 goes from OFF to ON, the upper 2 digits of the final I/O number plus 1 of the modules loaded are stored as BIN values. Indicates the number of modules installed on MELSECNET/H. SD255 I/O No. MELSECNET/H I/O number of first module installed SD256 SD257 SD258 SD29 SD291 SD292 SD293 SD294 SD295 SD296 SD297 SD298 SD299 SD3 SD31 SD32 SD33 SD34 SD315 SD34 MELSECNET/ H information Device allocation (Same as parameter contents) Device allocation (Same as parameter contents) Device allocation (Same as parameter contents) Time reserved for communication processing Information from 1st module Network No. Group number Station No. Number of points allocated for X Number of points allocated for Y Number of points allocated for M Number of points allocated for L Number of points allocated for B Number of points allocated for F Number of points allocated for SB Number of points allocated for V Number of points allocated for S Number of points allocated for T Number of points allocated for ST Number of points allocated for C Number of points allocated for D Number of points allocated for W Number of points allocated for SW Time reserved for communication processing No. of modules installed MELSECNET/H network number of first module installed MELSECNET/H group number of first module installed MELSECNET/H station number of first module installed Stores the number of points currently set for X devices Stores the number of points currently set for Y devices Stores the number of points currently set for M devices Stores the number of points currently set for L devices Stores the number of points currently set for B devices Stores the number of points currently set for F devices Stores the number of points currently set for SB devices Stores the number of points currently set for V devices Stores the number of points currently set for S devices Stores the number of points currently set for T device Stores the number of points currently set for ST devices Stores the number of points currently set for C devices Stores the number of points currently set for D devices Stores the number of points currently set for W devices Stores the number of points currently set for SW devices Reserves the designated time for communication processing with GX Developer or other units. The greater the value is designated, the shorter the response time for communication with other devices (GX Developer, serial communication units) becomes. Setting range: 1 to 1 ms If the designated value is out of the range above, it is assumed to no setting. The scan time becomes longer by the designated time. Indicates the number of modules installed on Ethernet. SD341 Ethernet I/O No. Indicates the I/O number of the installed Ethernet module. SD342 information Network No. Indicates the network No. of the installed Ethernet module. SD343 Group No. Indicates the group No. of the installed Ethernet module. SD344 Station No. Indicates the station No. of the installed Ethernet module. Set by (When set) S (Initial) S (Initial) S (Initial) S (Initial) S (Initial) S (Initial) END processing S (Initial) Corresponding CPU Serial number 4122 or later App - 14 App - 14

318 APPENDICES Special Register List (Continued) Number Name Meaning Explanation SD393 Number of multiple PLCs The number of CPU modules that comprise the multiple PLC system is stored. (1 to 3, Empty also included) The CPU module types of No. 1 CPU to 3 and whether the CPU modules are mounted or not are stored. b15 to b12 b11 to b8 b7 to b4 b3 to b SD394 Empty () PLC No. 3 PLC No. 2 PLC No. 1 Set by (When set) Corresponding CPU SD394 CPU mounting information S (Initial) SD395 SD396 SD397 SD398 Multiple PLC system information Multiple PLC No. No. 1 CPU operation status No. 2 CPU operation status No. 3 CPU operation status CPU module mounted or not mounted : Not mounted 1: Mounted CPU module type : PLC CPU 1: Motion CPU 2: PC CPU In a multiple PLC configuration, the PLC No. of the host PLC is stored. No. 1 CPU: 1, No. 2 CPU: 2, No. 3 CPU: 3 The operation information of each PLC No. is stored. (The information on the number of multiple PLCs indicated in SD393 is stored.) b15b14 to b8 b7 to b4 b3 to b Empty Classification Operation status Mounted or not mounted : Not mounted 1: Mounted : Normal 1: Minor fault 2: Medium fault 3: Major fault FH: Reset : RUN 1: STEP RUN 2: STOP 3: PAUSE 4: Initial FH: Reset S (When END processing error occurs) Serial number 4122 or later (3) System clocks/counters Number Name Meaning Explanation SD412 SD414 1 second counter 2n second clock setting SD42 Scan counter Number of counts in 1-second units 2n second clock units Number of counts in each scan Following programmable controller CPU module RUN, 1 is added each second Count repeats from to to to Stores value n of 2n second clock (Default is 3) Setting can be made between 1 and Incremented by 1 for each scan execution after the CPU module is set to RUN. Count repeats from to to to Set by (When set) S (Status change) U S(Every END processing) Corresponding CPU (4) Scan information Number Name Meaning Explanation SD52 Current scan time SD521 SD524 Minimum scan time SD525 SD526 SD527 Maximum scan time Current scan time (in 1 ms units) Current scan time (in 1 µs units) Minimum scan time (in 1 ms units) Minimum scan time (in 1 µs units) Maximum scan time (in 1 ms units) Maximum scan time (in 1 µs units) Stores current scan time (in 1 ms units) Range from to Stores current scan time (in 1 µs units) Range from to 9 (Example) A current scan of 23.6 ms would be stored as follows: D52=23 D521=6 Stores minimum value of scan time (in 1 ms units) Range from to Stores minimum value of scan time (in 1 µs units) Range of to 9 Stores maximum value of scan time, excepting the first scan. (in 1 ms units) Range from to Stores maximum value of scan time, excepting the first scan. (in 1 µs units) Range of to 9 Set by (When set) S (Every END processing) S (Every END processing) S (Every END processing) S (Every END processing) S (Every END processing) Corresponding CPU App - 15 App - 15

319 APPENDICES Special Register List (Continued) Number Name Meaning Explanation SD54 SD541 SD542 SD543 SD548 SD549 END processing time Constant scan wait time Scan program execution time END processing time (in 1 ms units) END processing time (in 1 µs units) Constant scan wait time (in 1 ms units) Constant scan wait time (in 1 µs units) Scan program execution time (in 1 ms units) Scan program execution time (in 1 µs units) Stores time from completion of scan program to start of next scan. (in 1 ms units) Range from to Stores time from completion of scan program to start of next scan. (in 1 µs units) Range of to 9 Stores wait time when constant scan time has been set. (in 1 ms units) Range from to Stores wait time when constant scan time has been set. (in 1 µs units) Range of to 9 Stores execution time for scan execution type program during 1 scan (in 1 ms units) Range from to Stores each scan Stores execution time for scan execution type program during 1 scan (in 1 µs units) Range of to 9 Stores each scan Set by (When set) S (Every END processing) S (First END processing) S (Every END processing) Corresponding CPU (5) Drive information Number Name Meaning Explanation Indicates the drive 3/4 models. b15 to b8 b7 to b4 b3 to b Set by (When set) Corresponding CPU SD62 SD622 SD623 SD624 Drive 3/4 models Drive 3 (Standard RAM) capacity Drive 4 (Standard ROM) capacity Drive 3 use conditions File register SD64 drive SD641 SD642 SD643 SD644 SD645 SD646 SD647 SD648 File register file name File register capacity File register block number Drive 3/4 models Drive 3 capacity Drive 3 : Absent (Standard RAM) 1: Present Drive 4 (Standrd ROM) Drive 4 is fixed to "3" because it has built-in Flash ROM. Drive 3 capacity is stored in 1kbyte units. (Fixed to "61" because it has 61kbyte RAM built-in.) Fixed at "3". S (Initial) S (Initial) Drive 4 capacity Drive 4 capacity is stored in 1kbyte units. S (Initial) Drive 3 use conditions Drive number: File register file name Drive 3 use conditions are stored in bit pattern. b15 to b4 to b Stores drive number being used by file register File register (R) 1: In use : Not used Stores file register file name (with extension) selected at parameters as ASCII code. b15 to b8 b7 to b SD641 Second character (A) SD642 Fourth character (N) SD643 Sixth character ( ) SD644 Eighth character ( ) SD645 First character of extension (Q) SD646 Third character of extension (R) First character (M) Third character (I) Fifth character ( ) Seventh character ( ) 2EH(.) Second character of extension (D) File register capacity Stores the data capacity of the currently selected file register in 1 k word units. File register block number Stores the currently selected file register block number. 1: The data is set when the CPU is stopped and then RUN or the RSET instruction is executed after parameter execution. S (Status change) S (Status change) 1 S (Initial) S (Initial) S (Status change) 1 App - 16 App - 16

320 APPENDICES (6) Instruction-Related Registers Number Name Meaning Explanation SD715 IMASK SD716 instruction mask pattern SD717 Mask pattern Patterns masked by use of the IMASK instruction are stored in the following manner: b15 to b1 b SD715 l15 to l1 l SD716 SD717 l31 l47 to to l17 l33 l16 l32 Set by (When set) S (During execution) Corresponding CPU SD718 SD719 SD774 SD778 Accumulator Accumulator For use as replacement for accumulators used in A-series programs. S/U PID limit setting (for exact differential) Refresh processing selection at COM instruction execution : With limit 1: Without limit b to b4 (Default: ) : Refresh not executed 1: Refresh executed b15 : General data processing executed 1: General data processing not executed Specify the limit of each PID loop as shown below. b15 to b8 b7 to b1 b SD774 Loop 8 to Loop 2 Loop 1 Select whether each refresh processing will be executed or not when the COM instruction is executed. Designation of SD778 is made valid when SM775 turns ON. b15 b14 to b5 b4 b3 b2 b1 b SD778 1/ 1/ 1/ 1/ 1/1/ I/O refresh CC-Link refresh MELSECNET/H refresh Automatic refresh of intelligent function modules Automatic refresh of CPU shared memory Execution/non-execution of general data processing U U Serial number 4122 or later SD781 TO SD785 Mask pattern of IMASK instruction Mask pattern Stores the mask patterns masked by the IMASK instruction as follows: b15 to b1 b SD781 l63 SD782 l79 to to l49 l65 l48 l64 to to S (During execution) SD785 l127 to l113 l112 SD794 PID limit setting (for inexact differential) : With limit 1: Without limit Specify the limit of each PID loop as shown below.z b15 to b8 b7 to b1 b SD794 Loop 8 to Loop 2 Loop 1 U Serial number 4122 or later App - 17 App - 17

321 APPENDICES APPENDIX 3 List of Interrupt Pointer Nos. and Interrupt Factors I No. Interrupt Factors Priority Ranking I 1st point 5 I1 2nd point 6 I2 3rd point 7 I3 4th point 8 I4 5th point 9 I5 6th point 1 I6 7th point 11 I7 8th point 12 QI6 interrupt module factor I8 9th point 13 I9 1th point 14 I1 11th point 15 I11 12th point 16 I12 13th point 17 I13 14th point 18 I14 15th point 19 I15 16th point 2 I16 to I27 Unusable I28 1ms 4 I29 4ms 3 Internal timer factor 1 I3 2ms 2 I31 1ms 1 I32 to I49 Unusable I5 to I127 2 Interrupt by intelligent function Set in the parameter which intelligent module module/qi6 function/interrupt module (QI6) will be used. 21 to 98 REMARK 1 : The internal times shown are the default setting times. These times can be designated in 1 ms units through a 2 ms to 1 ms range by the PLC system settings in the PLC parameter setting. 2 : Intelligent function module setting (interrupt pointer setting) must be made in the PLC system setting of the PLC parameter dialog box. (Refer to Section for the interruption from the intelligent function module.) App - 18 App - 18

322 APPENDICES APPENDIX 4 Enhancement of the Basic Model QCPU Functions Appendix 4.1 Specification Comparison The Basic model QCPU has been updated to add functions and change the specifications. The functions and specifications that can be used with the Basic model QCPU change depending on the function version. Function Version of CPU Module Specifications Standard RAM capacity QJCPU Function Version A Function Version B QCPU 64k bytes 128k bytes Q1CPU 64k bytes 128k bytes Shared memory : Usable/compatible, : Unusable/incompatible Appendix 4.2 Added Functions Added Function SFC(MELSAP3) Function block Structured text (ST) PID operation function Real number operation Function Version of CPU Module Intelligent function module event interruption Device initial value Remote password setting function parameter Write during RUN using pointer Increased file register R capacity (32k points to 64k points) Multiple CPU System compatibility Compatibility of Multiple CPU System with PC CPU module Function Version B App - 19 App - 19

323 APPENDICES MEMO App - 2 App - 2

324 INDEX [A] [B] Accuracy of scan time Annunciator (F) ASCII code Auto mode Base mode BCD (Binary coded decimal) BIN (Binary code) Boot Run [C] C (Counter) Character string Clock function Precision Concept of I/O assignment Constant scan Constants Counter (C) Count processing Maximum counting speed [D] D (Data register) Data register (D) Decimal constants (K) Device list Direct access input(dx) Direct access output(dy) Direct mode Drive Number Duty [G] GX Configurator GX Developer... A-17 [H] H (Hexadecimal constants) HEX (Hexadecimal) Hexadecimal constants (H) High-speed retentive timer (ST) High-speed timer (T) [I] I (Interrupt pointer) I/O No. designation device (Un) Index register (Z) Input response time Intelligent function module device (U \G ) Internal relay (M) Internal system device Internal user device Interrupt pointer (I) Interrupt program [J] J (Network designation device) J \B (Link relay) J \SB (Link special relay) J \SW (Link special register) J \W (Link register) J \X (Link input) J \Y (Link output) [K] K (Decimal constants) Ind [E] Edge relay(v) END processing [F] F (Anunciator) FD (Function register) File register File size Function device (FX, FY, FD) FX (Function input) FY (Function output) [L] L (Latch relay) Latch function Latch relay (L) LED display Link direct device Link register (W) Link relay (B) List of Interrupt factors App-1 Low-speed retentive timer (ST) Index - 1 Index - 1

325 Ind Low-speed timer (T) [M] M (Internal relay) Macro instruction argument device (VD) Main routine program [N] N (Nesting) [O] Output (Y) [P] P (Pointer) Password Pointer (P) Precautions when using timers Processing at annunciator OFF Processing at annunciator ON Program memory Purpose of I/O assignment Purpose of I/O assignment using [Q] QI [R] R (File register) Reading from the time data Refresh input Refresh mode Refresh output Remote latch clear Remote operation Remote PAUSE Remote RESET Remote RUN/STOP Remote station I/O number Retentive timer (OUT ST ) RUN status [S] S (Step relay) SB (Special link relay) Scan time SD (Special register) SD52, SD521 (Scan time: present value) SD524, SD525 (Scan time: Maximum value) SD526, SD527 (Scan time: Minimum value) Self-diagnosis function Sequence program Setting range in the internal user device Setting the number of stages Special link register (SW) Special link relay (SB) Special register (SD) Special relay (SM) ST (Retentive timer: OUT ST ) Standard RAM Standard RAM capacity... Standard ROM Step relay (S) Sub-routine program SW (Special link register) Switch setting of intelligent function module.7-24 System protect [T] T (Timer) Accuracy Processing [U] U (I/O No. designation device) U \G (Intelligent function module device) User memory [V] V (Edge relay) VD (Macro instruction argument device) [W] W (Link register) WDT (Watchdog timer) Write during RUN Writing to the time data [X] X (Input) [Y] Y (Output) [Z] Z (Index register) ZR (Serial number access format of file register) Index - 2 Index - 2

326 WARRANTY Please confirm the following product warranty details before starting use. 1. Gratis Warranty Term and Gratis Warranty Range If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the product within the gratis warranty term, the product shall be repaired at no cost via the dealer or Mitsubishi Service Company. Note that if repairs are required at a site overseas, on a detached island or remote place, expenses to dispatch an engineer shall be charged for. [Gratis Warranty Term] The gratis warranty term of the product shall be for one year after the date of purchase or delivery to a designated place. Note that after manufacture and shipment from Mitsubishi, the maximum distribution period shall be six (6) months, and the longest gratis warranty term after manufacturing shall be eighteen (18) months. The gratis warranty term of repair parts shall not exceed the gratis warranty term before repairs. [Gratis Warranty Range] (1) The range shall be limited to normal use within the usage state, usage methods and usage environment, etc., which follow the conditions and precautions, etc., given in the instruction manual, user's manual and caution labels on the product. (2) Even within the gratis warranty term, repairs shall be charged for in the following cases. 1. Failure occurring from inappropriate storage or handling, carelessness or negligence by the user. Failure caused by the user's hardware or software design. 2. Failure caused by unapproved modifications, etc., to the product by the user. 3. When the Mitsubishi product is assembled into a user's device, Failure that could have been avoided if functions or structures, judged as necessary in the legal safety measures the user's device is subject to or as necessary by industry standards, had been provided. 4. Failure that could have been avoided if consumable parts (battery, backlight, fuse, etc.) designated in the instruction manual had been correctly serviced or replaced. 5. Failure caused by external irresistible forces such as fires or abnormal voltages, and Failure caused by force majeure such as earthquakes, lightning, wind and water damage. 6. Failure caused by reasons unpredictable by scientific technology standards at time of shipment from Mitsubishi. 7. Any other failure found not to be the responsibility of Mitsubishi or the user. 2. Onerous repair term after discontinuation of production (1) Mitsubishi shall accept onerous product repairs for seven (7) years after production of the product is discontinued. Discontinuation of production shall be notified with Mitsubishi Technical Bulletins, etc. (2) Product supply (including repair parts) is not possible after production is discontinued. 3. Overseas service Overseas, repairs shall be accepted by Mitsubishi's local overseas FA Center. Note that the repair conditions at each FA Center may differ. 4. Exclusion of chance loss and secondary loss from warranty liability Regardless of the gratis warranty term, Mitsubishi shall not be liable for compensation to damages caused by any cause found not to be the responsibility of Mitsubishi, chance losses, lost profits incurred to the user by Failures of Mitsubishi products, damages and secondary damages caused from special reasons regardless of Mitsubishi's expectations, compensation for accidents, and compensation for damages to products other than Mitsubishi products and other duties. 5. Changes in product specifications The specifications given in the catalogs, manuals or technical documents are subject to change without prior notice. 6. Product application (1) In using the Mitsubishi MELSEC programmable logic controller, the usage conditions shall be that the application will not lead to a major accident even if any problem or fault should occur in the programmable logic controller device, and that backup and fail-safe functions are systematically provided outside of the device for any problem or fault. (2) The Mitsubishi general-purpose programmable logic controller has been designed and manufactured for applications in general industries, etc. Thus, applications in which the public could be affected such as in nuclear power plants and other power plants operated by respective power companies, and applications in which a special quality assurance system is required, such as for Railway companies or National Defense purposes shall be excluded from the programmable logic controller applications. Note that even with these applications, if the user approves that the application is to be limited and a special quality is not required, application shall be possible. When considering use in aircraft, medical applications, railways, incineration and fuel devices, manned transport devices, equipment for recreation and amusement, and safety devices, in which human life or assets could be greatly affected and for which a particularly high reliability is required in terms of safety and control system, please consult with Mitsubishi and discuss the required specifications.

327 Microsoft Windows, Microsoft Windows NT are registered trademarks of Microsoft Corporation in the United States and other countries. Pentium is a registered trademark of Intel Corporation in the United States and other countries. Ethernet is a registered trademark of Xerox. Co., Ltd in the United States. Other company and product names herein are either trademarks or registered trademarks of their respective owners.

328 Basic Model QCPU(Q Mode) User's Manual (Function Explanation, Program Fundamentals) MODEL MODEL CODE SQCPU(Q)-U-KI-E 13JR44 SH(NA)-8188-B(32)MEE HEAD OFFICE : , OFFICE TOWER Z 14F HARUMI CHUO-KU ,JAPAN NAGOYA WORKS : 1-14, YADA-MINAMI 5, HIGASHI-KU, NAGOYA, JAPAN When exported from Japan, this manual does not require application to the Ministry of Economy, Trade and Industry for service transaction permission. Specifications subject to change without notice.