Comparing Micron N25Q and Macronix MX25L Flash Devices

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1 Technical Note TN-12-14: Comparing and Flash Devices Introduction Comparing Micron and Macronix Flash Devices Introduction The purpose of this technical note is to compare features of the Micron (32Mb or 64Mb) and Macronix Flash memory devices. Features compared include memory architecture, package options, signal descriptions, command sets, electrical specifications, and device identification. tn1214_comparing_n25q_and_mx25l.pdf - Rev. A 10/10 EN 1 Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. All information discussed herein is provided on an "as is" basis, without warranties of any kind.

2 Memory Array Architecture TN-12-14: Comparing and Flash Devices Memory Array Architecture Features Program 1 to 256 bytes Uniform sector erase (64KB) Uniform subsector erase (4KB) Features Program 1 to 256 bytes Uniform sector erase (32KB and 64KB) Uniform subsector erase (4KB) Package Configurations Table 1: Package Configurations Package 32Mb 64Mb 32Mb 64Mb VDFPN8 (8mm x 6mm MLP8) Yes Yes Yes Yes TBGA24 (6mm x 8mm) Yes Yes VFDFPN8 (6mm x 5mm MLP) Yes Yes Yes Yes SO16 (300 mils body width) Yes Yes Yes Yes SO8W (SO8 208 mils body width) Yes Yes Yes Yes UFDFPN8 (4mm x 3mm MLP) Yes SO8N (SO8 150 mils body width) Yes Signal Descriptions Table 2: Signal Descriptions Signal Signal Type Description C SCLK Input Serial clock DQ0 SI/SIO0 Input or I/O Serial data input or I/O DQ1 SI/SIO0/P07 Output or I/O Serial data output or I/O S# CS# Input Chip select W/V PP /DQ2 #WP/SIO2 Input or I/O Write protect/enhanced program supply voltage or I/O HOLD#/DQ3 NC/SIO3 Input or I/O HOLD or I/O N/A PO0/PO7 I/O Parallel data output/input (PO0 PO6 can be connected to NC for serial mode) V CC V CC Input Supply voltage V SS GND Input Ground Notes: 1. The device does not support enhanced program supply voltage (V PP signal) or HOLD. 2. The parallel data feature is only available on the device. 3. During quad I/O operation, must set a bit (VCR or NVCR) for quad I/O functionality; during that time, the W and HOLD signals are functional. The W and HOLD signals lose functionality only when quad I/O operations are in progress (QUAD OUTPUT FAST READ, QUAD I/O FAST READ, QUAD SPI, and QUAD INPUT FAST PROGRAM). 4. During quad I/O operation, must set a bit (QE in SR6) for quad I/O functionality. tn1214_comparing_n25q_and_mx25l.pdf - Rev. A 10/10 EN 2

3 Commands Commands Table 3: Supported Command Set Command Name READ Command Code (Setup/Confirm) Command Code (Setup/Confirm) READ 03h 03h FAST READ 0Bh 0Bh DUAL OUTPUT FAST READ 3Bh N/A 1 DUAL INPUT/OUTPUT FAST READ BBh BBh QUAD OUTPUT FAST READ 6Bh N/A 1 QUAD INPUT/OUTPUT FAST READ EBh EBh READ DEVICE ID 9Fh/9Eh 9Fh 2 READ ELECTRONIC SIGNATURE N/A ABh/90h 3 READ ID (2x I/O, 4x I/O, 4x I/O DT) N/A EFh/DFh/CFh 3 READ CFI N/A N/A FAST DT READ (2x I/O, 4x I/O) N/A 0Dh/BDh/EDh 3 PARALLEL MODE (ENTER/EXIT) N/A 55h/45h 3 PROGRAM PAGE PROGRAM 02h 02h DUAL INPUT FAST PROGRAM A2h N/A 1 QUAD INPUT FAST PROGRAM 32h 38h 4 CONTINUOUS PROGRAM MODE N/A ADh 3 ERASE BULK ERASE C7h C7h/60h 5 SECTOR ERASE 64KB D8h D8h SECTOR ERASE 32KB N/A 52h 3 SUBSECTOR ERASE 4KB 20h 20h SUSPEND PROGRAM/ERASE SUSPEND 75h N/A 1, 6 PROGRAM/ERASE RESUME 7Ah N/A 1, 6 DEEP POWER-DOWN DEEP POWER-DOWN B9h B9h 7, 8 Notes RELEASE FROM DEEP POWER-DOWN ABh ABh 7, 8, 9 Notes: 1. Not supported on the. 2. 9Eh not supported on the. 3. Not supported on the. 4. The requires the 32h command. For the, the QE bit must be set prior to using the quad I/O instructions; then the 38h command must be issued h not supported on the. tn1214_comparing_n25q_and_mx25l.pdf - Rev. A 10/10 EN 3

4 Commands 6. PROGRAM/ERASE SUSPEND and PROGRAM/ERASE RESUME commands (75h/7Ah) are supported on the, but not on the. 7. Only available on the 1.8V, not on the 3V. 8. Commands are used to place the device in low power consumption mode. 9. The ABh command in the family is available but indicates RELEASE FROM DEEP- POWER DOWN (for 1.8V products). READ Commands The READ command set for the and devices is identical, and each device follows the standard three address byte protocol. The has a fixed dummy cycle read, but the dummy cycles can be configured and controlled in the nonvolatile configuration register (NVCR), bits 12 to 15, or in the volatile configuration register (VCR), bits 7 to 4. requires a nonvolatile QE bit in the SR2 to enable the quad I/O functionality, and when this bit is set, the W pin is disabled. also requires the HIGH PERFORM- ANCE MODE command (A3h) to be issued before either the DUAL I/O READ or QUAD I/ O READ command can be issued. VECR or NVCR enables the QSPI protocol (refer to the data sheet for more details). QUAD commands are available without any register setting. When VECR or NVCR bits are set, W and HOLD are still functional. With NVCR set (bit 3 = 0), the device can be powered up or down with quad I/O functionality. No additional commands are required for to use quad or dual I/O functionality. The and manufacturer ID, memory type, and memory capacity can be read out by issuing a 9Fh command. will output the same data when the 9Eh command is issued. The device has commands that output the device ID (ABh), and a command that outputs the manufacturer ID and device ID (90h). Power-Up Commands requires power-up to have a certain V CC slope and stay within the V CC rise time specification ( t VR). has no power-up limitation and can speed up the power-on sequence. tn1214_comparing_n25q_and_mx25l.pdf - Rev. A 10/10 EN 4

5 Execute in Place (XIP) TN-12-14: Comparing and Flash Devices Commands The protocol for execute in place (XIP) is different for the two devices. XIP is configured by selecting the appropriate line item or by issuing the correct confirmation command, whereas the XIP is enabled by issuing the correct confirmation command. Refer to Application Note, "Using XIP Modes in the Forte Flash Memory Device." Figure 1: XIP Timing Configuration S# Confirmation bits B7 B0 Mode C Mode 0 I/O switches from Input to Output DQ DQ DQ DQ Dummy Dummy Byte 1 Byte 2 Table 4: XIP Confirmation Bit Software Commands XIP Confirmation Bit Enter/confirm XIP mode B4 = 0 (B7 to B5 and B3 to B0 = "Don't Care") B7 B3 and B6 B2 and B5 B1 and B4 B0 Exit XIP mode B4 = 1 (B7 to B5 and B3 to B0 = "Don't Care") B7 = B3 or B6 = B2 or B5 = B1 or B4 = B0 tn1214_comparing_n25q_and_mx25l.pdf - Rev. A 10/10 EN 5

6 Electrical Characteristics Electrical Characteristics Table 5: DC Current Characteristics Parameter Symbol Min Max Min Max Standby current I CC µa Operating current (FAST READ QUAD I/O) Operating current (PAGE PROGRAM) Operating current (WRITE STATUS REGISTER) Units I CC ma I CC ma I CC ma Operating current (ERASE) I CC ma Table 6: DC Voltage Specifications Parameter Symbol Min Max Min Max Units Input low voltage V IL V CC V Input high voltage V IH 0.7 V CC V CC V CC V CC V Output low voltage V OL V Output high voltage V OH V CC V CC V tn1214_comparing_n25q_and_mx25l.pdf - Rev. A 10/10 EN 6

7 AC Characteristics AC Characteristics Table 7: AC Specifications Parameter Symbol Alternate Symbol Min Max Min Max Clock frequency (x1 FAST READ) f C f C MHz Clock frequency (x2, x4 FAST READ) f C f C MHz Clock frequency (READ) f R f R MHz S# active setup time t SLCH t CSS 4 8 ns Data-in setup time t DVCH t DSU 2 2 ns Data-in hold time t CHDX t DH 3 5 ns S# deselect time after correct READ (ARRAY READ to ARRAY READ) S# deselect time after incorrect READ or different instruction (ERASE/ PROGRAM to READ) Units t SHSL t CSH ns t SHSL t CSH ns Output disable time ( V) t SHQZ t DIS 8 10 ns Clock low to output valid (30pF) t CLQV t V 7 12 ns Output hold time t CLQX t HO 1 2 ns HOLD to output Low-Z t HHQX t LZ N/A 8 N/A N/A ns HOLD to output High-Z t HLQZ t HZ N/A 8 N/A N/A ns Note: 1. AC specifications compare the fastest versions available at the full voltage range ( V). Program and Erase Specifications Table 8: Program and Erase Specifications 32Mb 64Mb 32Mb 64Mb Operation Typ Max Typ Max Typ Max Typ Max Unit PAGE PROGRAM ms SUBSECTOR ERASE N/A N/A N/A N/A s SECTOR ERASE s BULK ERASE s tn1214_comparing_n25q_and_mx25l.pdf - Rev. A 10/10 EN 7

8 Configuration and Memory Map Table 9: Sectors and Subsectors by Density TN-12-14: Comparing and Flash Devices Configuration and Memory Map Density Sector Subsector Address Range FFFFFh 7FF000h : : : F0FFFh 7F0000h : : : : FFFFFh 3FF000h : : : F0FFFh 3F0000h : : : : FFFFh 0F000h : : : 4 04FFFh 04000h 3 03FFFh 03000h 2 02FFFh 02000h 1 01FFFh 01000h 0 00FFFh 00000h Device Identification Table 10: Read Identification Summary Manufacturer identification is assigned by JEDEC. As a result, the and devices have a different manufacturer ID and memory type codes even though their memory capacity is identical. Command 9Fh is used to read these codes in both devices. has a unique ID (UID) composed of 17 read-only bytes, which contain the following data: The first byte is set to 10h. The next two bytes of extended device ID specify device configuration (top, bottom, or uniform architecture and hold or reset functionality). The next 14 bytes contain optional customized factory data. The customized factory data bytes are factory programmed. Refer to the data sheet for more information. Parameter Code Code Manufacturer ID 20h EFh Memory type BAh 40h Memory capacity 16h (32Mb), 17h (64Mb) 16h (32Mb), 17h (64Mb) tn1214_comparing_n25q_and_mx25l.pdf - Rev. A 10/10 EN 8

9 Conclusion Conclusion Comparing the features of the Micron and Flash memory devices enables users to migrate applications from the to the. tn1214_comparing_n25q_and_mx25l.pdf - Rev. A 10/10 EN 9

10 Revision History Revision History Rev. A 10/10 Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID , Tel: Customer Comment Line: Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. tn1214_comparing_n25q_and_mx25l.pdf - Rev. A 10/10 EN 10

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