Storage Performance Development Kit (SPDK) Daniel Verkamp, Software Engineer
|
|
- Abraham Quinn
- 6 years ago
- Views:
Transcription
1 Storage Performance Development Kit (SPDK) Daniel Verkamp, Software Engineer
2 Agenda Threading model discussion SPDK Environment Layer SPDK Application Framework SPDK Blockdev Layer SPDK Example Apps 2
3 Motivation: Performance via Concurrency Modern CPUs provide many cores Core 0 Core 1 Core N Modern I/O devices provide many independent queues I/O Device I/O Device I/O Device Goal: Architect software to match the hardware 3
4 Context switching and interrupts OS-provided multitasking was important on single-core machines Modern machines have many cores Instead of context switching, dedicate core(s) to specific tasks Avoid interrupt handler overhead and latency by polling Instead of locks, pass messages 4
5 Threading Model Options Model Pros Cons Example One connection per thread with blocking I/O Simple programming model Interrupt driven High memory overhead Apache worker MPM Many connections per thread with I/O event multiplexing (select(), ) Low memory overhead Less context switching Interrupt driven Inefficient polling Apache event MPM, nginx, libuv, Many connections per thread with polled asynchronous I/O Low memory overhead No interrupts No context switching More complex programming model SPDK 5
6 What threading model does SPDK target? Asynchronous polled I/O 6
7
8 Why an environment abstraction? Flexibility for user 8
9 Environment abstraction Memory allocation (pinned for DMA) and address translation PCI enumeration and resource mapping Thread startup (pinned to cores) Lock-free ring and memory pool data structures env.h init.c pci.c pci_ioat.c pci_nvme.c vtophys.c 9
10 Environment abstraction Configurable:./configure --with-env=... Interface defined in spdk/env.h Default implementation uses DPDK (lib/env_dpdk) env.h init.c pci.c pci_ioat.c pci_nvme.c vtophys.c lib/env_dpdk Flexibility: Decoupling and DPDK enhancements 10
11
12 How do we combine SPDK components? The SPDK app Framework provides the glue 12
13 Application Framework Builds on the environment abstraction Example of how to glue other SPDK components together Libraries (lib/*) vs. applications (app/*) lib/event event.h app.c reactor.c subsystem.c 13
14 App Framework Components Reactor Event I/O Channel 14
15 Reactor Core 0 Core 1 Core N Event loop (essentially a scheduler) Events Events Events Pinned to a specific CPU core Polls I/O devices Polls event ring Reactor 0 Reactor 1 Reactor N Communication via event passing I/O Device I/O Device I/O Device 15
16 Core 0 Core 1 Core N Events Events Events Reactor 0 Reactor 1 Reactor N I/O Device I/O Device I/O Device 16
17 Essentially a task running on a reactor Primarily checks hardware for async events Can run periodically on a timer Example: poll completion queue Callback runs to completion on reactor thread Submit I/O SQ I/O completion callback CQ Completion handler may send an event I/O Device 17
18 Event Core 0 Core 1 Core N Events Events Events Reactor 0 Reactor 1 Reactor N I/O Device I/O Device I/O Device 18
19 Event Cross-thread communication Function pointer + arguments One-shot message passed between reactors Multi-producer/single-consumer ring Runs to completion on reactor thread Reactor A Allocate and call event Events Reactor B Execute and free event 19
20 I/O Channel Abstracts hardware I/O queues Register I/O devices Create I/O channel per thread/device combination Provides hooks for driver resource allocation I/O Device I/O channel creation drives poller creation Pervasive in SPDK 20
21
22 Block Device Layer Block device driver abstraction Async read, write, flush, deallocate SGL support (readv/writev) I/O channel integration Layering (virtual blockdevs) blockdev_nvme.c blockdev_malloc.c lib/bdev bdev.h bdev.c vbdev_split.c blockdev_aio.c blockdev_rbd.c 22
23 Bdev Drivers NVMe* (local, remote) Malloc (RAM disk) Linux libaio Ceph RBD Potential future work: pmem (NVML) blockdev_nvme.c blockdev_malloc.c lib/bdev bdev.h bdev.c vbdev_split.c blockdev_aio.c blockdev_rbd.c *Other names and brands may be claimed as the property of others. 23
24 Bdev Layering Virtual blockdev drivers Claim base bdev(s) Produce virtual bdev(s) Provide storage services Example: vbdev_split Coming soon: Blob bdev Bdev API Virtual bdev Bdev API Base bdev 24
25
26 NVMe over Fabrics Target Example Acceptor network poller handles connect events Events Connect Event Events Connection event registers new poller Reactor 0 Reactor 1 Acceptor Connection Network Connection 26
27 NVMe over Fabrics Target Example Acceptor network poller handles connect events Events Connect Event Events Connection event registers new poller I/O request arrives over network I/O submitted to storage Storage device poller checks completions Response sent All asynchronous work is driven by pollers Reactor 0 Acceptor Network Connection Reactor 1 Storage Storage I/O 27
28 vhost-scsi Example VM guest adds task to shared-memory queue Task retrieved from queue and passed to SCSI Events Reactor 0 I/O submitted to storage Queue SCSI Storage Storage poller completes I/O SCSI layer signals completion by sending an event Event completes I/O back to VM Virtio Queue Storage VM Guest I/O 28
29 Software design follows from hardware capabilities Building blocks to manage asynchronous I/O Swappable environment abstraction
30 Notices and Disclaimers Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit Intel, the Intel logo, Xeon, and others are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others Intel Corporation.
31
Ziye Yang. NPG, DCG, Intel
Ziye Yang NPG, DCG, Intel Agenda What is SPDK? Accelerated NVMe-oF via SPDK Conclusion 2 Agenda What is SPDK? Accelerated NVMe-oF via SPDK Conclusion 3 Storage Performance Development Kit Scalable and
More informationSPDK China Summit Ziye Yang. Senior Software Engineer. Network Platforms Group, Intel Corporation
SPDK China Summit 2018 Ziye Yang Senior Software Engineer Network Platforms Group, Intel Corporation Agenda SPDK programming framework Accelerated NVMe-oF via SPDK Conclusion 2 Agenda SPDK programming
More informationAccelerating NVMe-oF* for VMs with the Storage Performance Development Kit
Accelerating NVMe-oF* for VMs with the Storage Performance Development Kit Jim Harris Principal Software Engineer Intel Data Center Group Santa Clara, CA August 2017 1 Notices and Disclaimers Intel technologies
More informationChangpeng Liu, Cloud Software Engineer. Piotr Pelpliński, Cloud Software Engineer
Changpeng Liu, Cloud Software Engineer Piotr Pelpliński, Cloud Software Engineer Introduction to VirtIO and Vhost SPDK Vhost Architecture Use cases for vhost Benchmarks Next steps QEMU VIRTIO Vhost (KERNEL)
More informationBen Walker Data Center Group Intel Corporation
Ben Walker Data Center Group Intel Corporation Notices and Disclaimers Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service activation.
More informationNVMe Over Fabrics: Scaling Up With The Storage Performance Development Kit
NVMe Over Fabrics: Scaling Up With The Storage Performance Development Kit Ben Walker Data Center Group Intel Corporation 2018 Storage Developer Conference. Intel Corporation. All Rights Reserved. 1 Notices
More informationDaniel Verkamp, Software Engineer
Daniel Verkamp, Software Engineer Notices and Disclaimers Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn
More informationChangpeng Liu. Cloud Storage Software Engineer. Intel Data Center Group
Changpeng Liu Cloud Storage Software Engineer Intel Data Center Group Notices & Disclaimers Intel technologies features and benefits depend on system configuration and may require enabled hardware, software
More informationAccelerating NVMe I/Os in Virtual Machine via SPDK vhost* Solution Ziye Yang, Changpeng Liu Senior software Engineer Intel
Accelerating NVMe I/Os in Virtual Machine via SPDK vhost* Solution Ziye Yang, Changpeng Liu Senior software Engineer Intel @optimistyzy Notices & Disclaimers Intel technologies features and benefits depend
More informationChangpeng Liu. Senior Storage Software Engineer. Intel Data Center Group
Changpeng Liu Senior Storage Software Engineer Intel Data Center Group Legal Notices and Disclaimers Intel technologies features and benefits depend on system configuration and may require enabled hardware,
More informationJim Harris. Principal Software Engineer. Data Center Group
Jim Harris Principal Software Engineer Data Center Group Notices and Disclaimers Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service
More informationSPDK Blobstore: A Look Inside the NVM Optimized Allocator
SPDK Blobstore: A Look Inside the NVM Optimized Allocator Paul Luse, Principal Engineer, Intel Vishal Verma, Performance Engineer, Intel 1 Outline Storage Performance Development Kit What, Why, How? Blobstore
More informationAchieve Low Latency NFV with Openstack*
Achieve Low Latency NFV with Openstack* Yunhong Jiang Yunhong.Jiang@intel.com *Other names and brands may be claimed as the property of others. Agenda NFV and network latency Why network latency on NFV
More informationTHE STORAGE PERFORMANCE DEVELOPMENT KIT AND NVME-OF
14th ANNUAL WORKSHOP 2018 THE STORAGE PERFORMANCE DEVELOPMENT KIT AND NVME-OF Paul Luse Intel Corporation Apr 2018 AGENDA Storage Performance Development Kit What is SPDK? The SPDK Community Why are so
More informationJim Harris. Principal Software Engineer. Intel Data Center Group
Jim Harris Principal Software Engineer Intel Data Center Group Notices & Disclaimers Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or
More informationJim Harris Principal Software Engineer Intel Data Center Group
Jim Harris Principal Software Engineer Intel Data Center Group Legal Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
More informationAccelerate block service built on Ceph via SPDK Ziye Yang Intel
Accelerate block service built on Ceph via SPDK Ziye Yang Intel 1 Agenda SPDK Introduction Accelerate block service built on Ceph SPDK support in Ceph bluestore Summary 2 Agenda SPDK Introduction Accelerate
More informationOut-of-band (OOB) Management of Storage Software through Baseboard Management Controller Piotr Wysocki, Kapil Karkra Intel
Out-of-band (OOB) Management of Storage Software through Baseboard Management Controller Piotr Wysocki, Kapil Karkra Intel 2018 Storage Developer Conference. Intel Corporation. All Rights Reserved. 1 Notices
More informationOpenMPDK and unvme User Space Device Driver for Server and Data Center
OpenMPDK and unvme User Space Device Driver for Server and Data Center Open source for maximally utilizing Samsung s state-of-art Storage Solution in shorter development time White Paper 2 Target Audience
More informationMunara Tolubaeva Technical Consulting Engineer. 3D XPoint is a trademark of Intel Corporation in the U.S. and/or other countries.
Munara Tolubaeva Technical Consulting Engineer 3D XPoint is a trademark of Intel Corporation in the U.S. and/or other countries. notices and disclaimers Intel technologies features and benefits depend
More informationFuture of datacenter STORAGE. Carol Wilder, Niels Reimers,
Future of datacenter STORAGE Carol Wilder, carol.a.wilder@intel.com Niels Reimers, niels.reimers@intel.com Legal Notices/disclaimer Intel technologies features and benefits depend on system configuration
More informationEd Warnicke, Cisco. Tomasz Zawadzki, Intel
Ed Warnicke, Cisco Tomasz Zawadzki, Intel Agenda SPDK iscsi target overview FD.io and VPP SPDK iscsi VPP integration Q&A 2 Notices & Disclaimers Intel technologies features and benefits depend on system
More informationMDev-NVMe: A NVMe Storage Virtualization Solution with Mediated Pass-Through
MDev-NVMe: A NVMe Storage Virtualization Solution with Mediated Pass-Through Bo Peng 1,2, Haozhong Zhang 2, Jianguo Yao 1, Yaozu Dong 2, Yu Xu 1, Haibing Guan 1 1 Shanghai Key Laboratory of Scalable Computing
More informationIntel Builder s Conference - NetApp
Intel Builder s Conference - NetApp John Meneghini Data ONTAP NVMe-oF Target Architect Madhu Pai Data ONTAP NVMe-oF Transport Architect April 21, 2017 V1.2 1 2017 NetApp, Inc. All rights reserved.. Introduction
More informationMetadata Tagging in Cinder
Metadata Tagging in Cinder OpenStack Summit Vancouver Dave Chen May 2015 Agenda o Motivation o Use-case scenarios o Work in progress o o o Cinder CLI, API Properties protection New Dashboard o Conclusion
More informationVDPA: VHOST-MDEV AS NEW VHOST PROTOCOL TRANSPORT
VDPA: VHOST-MDEV AS NEW VHOST PROTOCOL TRANSPORT CUNMING(Steve) LIANG, Intel cunming.liang AT intel.com KVM Forum 2018, Edinburgh October, 2018 Background KVM Forum 2018 / Edinburg / 2018 Intel Corporation
More informationData and Intelligence in Storage Carol Wilder Intel Corporation
Data and Intelligence in Storage Carol Wilder carol.a.wilder@intel.com Intel Corporation 1 Legal Notices/Disclaimer Intel technologies features and benefits depend on system configuration and may require
More informationTotal Cost of Ownership Analysis for a Wireless Access Gateway
white paper Communications Service Providers TCO Analysis Total Cost of Ownership Analysis for a Wireless Access Gateway An analysis of the total cost of ownership of a wireless access gateway running
More informationThe Transition to PCI Express* for Client SSDs
The Transition to PCI Express* for Client SSDs Amber Huffman Senior Principal Engineer Intel Santa Clara, CA 1 *Other names and brands may be claimed as the property of others. Legal Notices and Disclaimers
More informationIntel Clear Containers. Amy Leeland Program Manager Clear Linux, Clear Containers And Ciao
Intel Clear Containers Amy Leeland Program Manager Clear Linux, Clear Containers And Ciao Containers are... Speedy Fast create, update and uninstall cycle. Request and provision in (milli)seconds Manageable
More informationJim Pappas Director of Technology Initiatives, Intel Vice-Chair, Storage Networking Industry Association (SNIA) December 07, 2018
Jim Pappas Director of Technology Initiatives, Intel Vice-Chair, Storage Networking Industry Association (SNIA) December 07, 2018 jim@intel.com 1 How did this Effort Start? Memristor MRAM Carbon Nanotube
More informationMichael Kinsner, Dirk Seynhaeve IWOCL 2018
Michael Kinsner, Dirk Seynhaeve IWOCL 2018 Topics 1. FPGA overview 2. Motivating application classes 3. Host pipes 4. Some data 2 FPGA: Fine-grained Massive Parallelism Intel Stratix 10 FPGA: Over 5 Million
More informationUsing persistent memory and RDMA for Ceph client write-back caching Scott Peterson, Senior Software Engineer Intel
Using persistent memory and RDMA for Ceph client write-back caching Scott Peterson, Senior Software Engineer Intel 2018 Storage Developer Conference. Intel Corporation. All Rights Reserved. 1 Ceph Concepts
More informationIntel. Rack Scale Design: A Deeper Perspective on Software Manageability for the Open Compute Project Community. Mohan J. Kumar Intel Fellow
Intel Rack Scale Design: A Deeper Perspective on Software Manageability for the Open Compute Project Community Mohan J. Kumar Intel Fellow Agenda Rack Scale Design (RSD) Overview Manageability for RSD
More informationThe Path to DPDK Speeds for AF XDP
The Path to DPDK Speeds for AF XDP Magnus Karlsson, magnus.karlsson@intel.com Björn Töpel, bjorn.topel@intel.com Linux Plumbers Conference, Vancouver, 2018 Legal Disclaimer Intel technologies may require
More informationRe-Architecting Cloud Storage with Intel 3D XPoint Technology and Intel 3D NAND SSDs
Re-Architecting Cloud Storage with Intel 3D XPoint Technology and Intel 3D NAND SSDs Jack Zhang yuan.zhang@intel.com, Cloud & Enterprise Storage Architect Santa Clara, CA 1 Agenda Memory Storage Hierarchy
More informationFast packet processing in linux with af_xdp
Fast packet processing in linux with af_xdp Magnus Karlsson and Björn Töpel, Intel Legal Disclaimer Intel technologies may require enabled hardware, specific software, or services activation. Check with
More informationLight & NOS. Dan Li Tsinghua University
Light & NOS Dan Li Tsinghua University Performance gain The Power of DPDK As claimed: 80 CPU cycles per packet Significant gain compared with Kernel! What we care more How to leverage the performance gain
More informationJomar Silva Technical Evangelist
Jomar Silva Technical Evangelist Agenda Introduction Intel Graphics Performance Analyzers: what is it, where do I get it, and how do I use it? Intel GPA with VR What devices can I use Intel GPA with and
More informationOpenFlow Software Switch & Intel DPDK. performance analysis
OpenFlow Software Switch & Intel DPDK performance analysis Agenda Background Intel DPDK OpenFlow 1.3 implementation sketch Prototype design and setup Results Future work, optimization ideas OF 1.3 prototype
More informationAlexei Katranov. IWOCL '16, April 21, 2016, Vienna, Austria
Alexei Katranov IWOCL '16, April 21, 2016, Vienna, Austria Hardware: customization, integration, heterogeneity Intel Processor Graphics CPU CPU CPU CPU Multicore CPU + integrated units for graphics, media
More informationDebugging and Analyzing Programs using the Intercept Layer for OpenCL Applications
Debugging and Analyzing Programs using the Intercept Layer for OpenCL Applications Ben Ashbaugh IWOCL 2018 https://github.com/intel/opencl-intercept-layer Why am I here? Intercept Layer for OpenCL Applications
More informationReal-Time Systems and Intel take industrial embedded systems to the next level
Solution brief Industrial IoT (IIoT) Embedded Software and Systems Real-Time Systems and Intel take industrial embedded systems to the next level Innovative hypervisor and partitioning software increases
More informationMICHAL MROZEK ZBIGNIEW ZDANOWICZ
MICHAL MROZEK ZBIGNIEW ZDANOWICZ Legal Notices and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY
More informationAre You Insured Against Your Noisy Neighbor Sunku Ranganath, Intel Corporation Sridhar Rao, Spirent Communications
Are You Insured Against Your Noisy Neighbor Sunku Ranganath, Intel Corporation Sridhar Rao, Spirent Communications @SunkuRanganath, @ngignir Legal Disclaimer 2018 Intel Corporation. Intel, the Intel logo,
More information12th ANNUAL WORKSHOP 2016 NVME OVER FABRICS. Presented by Phil Cayton Intel Corporation. April 6th, 2016
12th ANNUAL WORKSHOP 2016 NVME OVER FABRICS Presented by Phil Cayton Intel Corporation April 6th, 2016 NVM Express * Organization Scaling NVMe in the datacenter Architecture / Implementation Overview Standardization
More informationHigh Performance Storage : A Cloud Story. Luwei He Standard Engineer, Huawei
High Performance Storage : A Cloud Story Luwei He Standard Engineer, Huawei Outline Background Cloud Storage Core Technologies Proposed Design Conclusion Background? More and more applications rely on
More informationFlashGrid Software Enables Converged and Hyper-Converged Appliances for Oracle* RAC
white paper FlashGrid Software Intel SSD DC P3700/P3600/P3500 Topic: Hyper-converged Database/Storage FlashGrid Software Enables Converged and Hyper-Converged Appliances for Oracle* RAC Abstract FlashGrid
More informationI/O Handling. ECE 650 Systems Programming & Engineering Duke University, Spring Based on Operating Systems Concepts, Silberschatz Chapter 13
I/O Handling ECE 650 Systems Programming & Engineering Duke University, Spring 2018 Based on Operating Systems Concepts, Silberschatz Chapter 13 Input/Output (I/O) Typical application flow consists of
More informationAndrzej Jakowski, Armoun Forghan. Apr 2017 Santa Clara, CA
Andrzej Jakowski, Armoun Forghan Apr 2017 Santa Clara, CA Legal Disclaimers Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service
More informationScott Oaks, Oracle Sunil Raghavan, Intel Daniel Verkamp, Intel 03-Oct :45 p.m. - 4:30 p.m. Moscone West - Room 3020
Scott Oaks, Oracle Sunil Raghavan, Intel Daniel Verkamp, Intel 03-Oct-2017 3:45 p.m. - 4:30 p.m. Moscone West - Room 3020 Big Data Talk Exploring New SSD Usage Models to Accelerate Cloud Performance 03-Oct-2017,
More informationIntel Atom Processor Based Platform Technologies. Intelligent Systems Group Intel Corporation
Intel Atom Processor Based Platform Technologies Intelligent Systems Group Intel Corporation Legal Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS
More informationAndreas Schneider. Markus Leberecht. Senior Cloud Solution Architect, Intel Deutschland. Distribution Sales Manager, Intel Deutschland
Markus Leberecht Senior Cloud Solution Architect, Intel Deutschland Andreas Schneider Distribution Sales Manager, Intel Deutschland Legal Disclaimers 2016 Intel Corporation. Intel, the Intel logo, Xeon
More informationSPDK NVMe In-depth Look at its Architecture and Design Jim Harris Intel
SPDK NVMe In-depth Look at its Architecture and Design Jim Harris Intel 2018 Storage Developer Conference. Insert Your Company Name. All Rights Reserved. 1 What is SPDK? Storage Performance Development
More informationIntel Architecture 2S Server Tioga Pass Performance and Power Optimization
Intel Architecture 2S Server Tioga Pass Performance and Power Optimization Terry Trausch/Platform Architect/Intel Inc. Whitney Zhao/HW Engineer/Facebook Inc. Agenda Tioga Pass Feature Overview Intel Xeon
More informationIXPUG 16. Dmitry Durnov, Intel MPI team
IXPUG 16 Dmitry Durnov, Intel MPI team Agenda - Intel MPI 2017 Beta U1 product availability - New features overview - Competitive results - Useful links - Q/A 2 Intel MPI 2017 Beta U1 is available! Key
More informationAgenda. Introduction Network functions virtualization (NFV) promise and mission cloud native approach Where do we want to go with NFV?
August, 2018 Agenda Introduction Network functions virtualization (NFV) promise and mission cloud native approach Where do we want to go with NFV? 2 Miroslaw Walukiewicz I m from Gdansk, Poland. 25 years
More informationVälkommen. Intel Anders Huge
Välkommen Intel Anders Huge Transformative Technology from Intel A n d e r s H u g e I n t e l Why intel INTEL CORPORATION 5 TRANSFORMING BUSINESS MODERN BUSINESS DEMANDS Intel VISION Accelerate workplace
More informationIntel Speed Select Technology Base Frequency - Enhancing Performance
Intel Speed Select Technology Base Frequency - Enhancing Performance Application Note April 2019 Document Number: 338928-001 You may not use or facilitate the use of this document in connection with any
More informationFast-track Hybrid IT Transformation with Intel Data Center Blocks for Cloud
Fast-track Hybrid IT Transformation with Intel Data Center Blocks for Cloud Kyle Corrigan, Cloud Product Line Manager, Intel Server Products Group Wagner Diaz, Product Marketing Engineer, Intel Data Center
More informationDPDK Vhost/Virtio Performance Report Release 18.11
DPDK Vhost/Virtio Performance Report Test Date: December 3st 2018 Author: Intel DPDK Validation Team Revision History Date Revision Comment December 3st, 2018 1.0 Initial document for release 2 Contents
More informationOPENSHMEM AND OFI: BETTER TOGETHER
4th ANNUAL WORKSHOP 208 OPENSHMEM AND OFI: BETTER TOGETHER James Dinan, David Ozog, and Kayla Seager Intel Corporation [ April, 208 ] NOTICES AND DISCLAIMERS Intel technologies features and benefits depend
More informationIN-PERSISTENT-MEMORY COMPUTING WITH JAVA ERIC KACZMAREK INTEL CORPORATION
IN-PERSISTENT-MEMORY COMPUTING WITH JAVA ERIC KACZMAREK INTEL CORPORATION LEGAL DISCLAIMER & OPTIMIZATION NOTICE INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL
More informationKVM as The NFV Hypervisor
KVM as The NFV Hypervisor Jun Nakajima Contributors: Mesut Ergin, Yunhong Jiang, Krishna Murthy, James Tsai, Wei Wang, Huawei Xie, Yang Zhang 1 Legal Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED
More informationDPDK Summit China 2017
DPDK Summit China 2017 2 DPDK in container Status Quo and Future Directions Jianfeng Tan, June 2017 3 LEGAL DISCLAIMER No license (express or implied, by estoppel or otherwise) to any intellectual property
More informationColin Cunningham, Intel Kumaran Siva, Intel Sandeep Mahajan, Oracle 03-Oct :45 p.m. - 5:30 p.m. Moscone West - Room 3020
Colin Cunningham, Intel Kumaran Siva, Intel Sandeep Mahajan, Oracle 03-Oct-2017 4:45 p.m. - 5:30 p.m. Moscone West - Room 3020 Big Data Talk Exploring New SSD Usage Models to Accelerate Cloud Performance
More informationH.J. Lu, Sunil K Pandey. Intel. November, 2018
H.J. Lu, Sunil K Pandey Intel November, 2018 Issues with Run-time Library on IA Memory, string and math functions in today s glibc are optimized for today s Intel processors: AVX/AVX2/AVX512 FMA It takes
More informationStorage Performance Tuning for FAST! Virtual Machines
Storage Performance Tuning for FAST! Virtual Machines Fam Zheng Senior Software Engineer LC3-2018 Outline Virtual storage provisioning NUMA pinning VM configuration options Summary Appendix 2 Virtual storage
More informationDPDK Vhost/Virtio Performance Report Release 18.05
DPDK Vhost/Virtio Performance Report Test Date: Jun 1 2018 Author: Intel DPDK Validation Team Revision History Date Revision Comment Jun 1st, 2018 1.0 Initial document for release 2 Release 18.02 Contents
More informationINTEL HPC DEVELOPER CONFERENCE FUEL YOUR INSIGHT
INTEL HPC DEVELOPER CONFERENCE FUEL YOUR INSIGHT INTEL HPC DEVELOPER CONFERENCE FUEL YOUR INSIGHT UPDATE ON OPENSWR: A SCALABLE HIGH- PERFORMANCE SOFTWARE RASTERIZER FOR SCIVIS Jefferson Amstutz Intel
More informationException-Less System Calls for Event-Driven Servers
Exception-Less System Calls for Event-Driven Servers Livio Soares and Michael Stumm University of Toronto Talk overview At OSDI'10: exception-less system calls Technique targeted at highly threaded servers
More informationBuilding an Open Memory-Centric Computing Architecture using Intel Optane Frank Ober Efstathios Efstathiou Oracle Open World 2017 October 3, 2017
Building an Memory-Centric Computing Architecture using Intel Optane Frank Ober Efstathios Efstathiou Oracle World 2017 October 3, 2017 Agenda The legal stuff Why Memory Centric Computing? Overview of
More informationI/O Systems. Amir H. Payberah. Amirkabir University of Technology (Tehran Polytechnic)
I/O Systems Amir H. Payberah amir@sics.se Amirkabir University of Technology (Tehran Polytechnic) Amir H. Payberah (Tehran Polytechnic) I/O Systems 1393/9/15 1 / 57 Motivation Amir H. Payberah (Tehran
More informationIntel s Architecture for NFV
Intel s Architecture for NFV Evolution from specialized technology to mainstream programming Net Futures 2015 Network applications Legal Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION
More informationINTEL PENTIUM Gold AND CELERON PROCESSORS
INTEL PENTIUM Gold AND CELERON PROCESSORS Reliable performance and affordable priced PCs for value-oriented buyers Impressive performance for work and play. The new Pentium Gold processor provides great
More informationIntel RaId Intel Product Quick Reference Matrix - Servers Q1,
Intel Raid Intel Product Quick Reference Matrix - Servers Q1, 2018 1 Intel RAID Experience exceptional data protection, faster performance, and ease of use. Intel tri-mode generation RAID PRODuctS Intel
More informationZhang Tianfei. Rosen Xu
Zhang Tianfei Rosen Xu Agenda Part 1: FPGA and OPAE - Intel FPGAs and the Modern Datacenter - Platform Options and the Acceleration Stack - FPGA Hardware overview - Open Programmable Acceleration Engine
More informationLast class: Today: Course administration OS definition, some history. Background on Computer Architecture
1 Last class: Course administration OS definition, some history Today: Background on Computer Architecture 2 Canonical System Hardware CPU: Processor to perform computations Memory: Programs and data I/O
More informationNVMe over Fabrics support in Linux Christoph Hellwig Sagi Grimberg
NVMe over Fabrics support in Linux Christoph Hellwig Sagi Grimberg 2016 Storage Developer Conference. Insert Your Company Name. All Rights Reserved. NVMe over Fabrics: the beginning Early 2014 demo apparently
More informationCrosstalk between VMs. Alexander Komarov, Application Engineer Software and Services Group Developer Relations Division EMEA
Crosstalk between VMs Alexander Komarov, Application Engineer Software and Services Group Developer Relations Division EMEA 2 September 2015 Legal Disclaimer & Optimization Notice INFORMATION IN THIS DOCUMENT
More informationVirtualization, Xen and Denali
Virtualization, Xen and Denali Susmit Shannigrahi November 9, 2011 Susmit Shannigrahi () Virtualization, Xen and Denali November 9, 2011 1 / 70 Introduction Virtualization is the technology to allow two
More informationCeph BlueStore Performance on Latest Intel Server Platforms. Orlando Moreno Performance Engineer, Intel Corporation May 10, 2018
Ceph BlueStore Performance on Latest Intel Server Platforms Orlando Moreno Performance Engineer, Intel Corporation May 10, 2018 Legal Disclaimers 2017 Intel Corporation. Intel, the Intel logo, Xeon and
More informationIntel Core TM Processor i C Embedded Application Power Guideline Addendum
Intel Core TM Processor i3-2115 C Embedded Application Power Guideline Addendum August 2012 Document Number: 327874-001US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO
More informationAgenda. Optimization Notice Copyright 2017, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others.
Agenda VTune Amplifier XE OpenMP* Analysis: answering on customers questions about performance in the same language a program was written in Concepts, metrics and technology inside VTune Amplifier XE OpenMP
More informationVMware vsphere Virtualization of PMEM (PM) Richard A. Brunner, VMware
VMware vsphere Virtualization of PMEM (PM) Richard A. Brunner, VMware Disclaimer This presentation may contain product features that are currently under development. This overview of new technology represents
More informationI/O virtualization. Jiang, Yunhong Yang, Xiaowei Software and Service Group 2009 虚拟化技术全国高校师资研讨班
I/O virtualization Jiang, Yunhong Yang, Xiaowei 1 Legal Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE,
More informationCS370 Operating Systems
CS370 Operating Systems Colorado State University Yashwant K Malaiya Spring 2018 Lecture 2 Slides based on Text by Silberschatz, Galvin, Gagne Various sources 1 1 2 What is an Operating System? What is
More informationApril 2 nd, Bob Burroughs Director, HPC Solution Sales
April 2 nd, 2019 Bob Burroughs Director, HPC Solution Sales Today - Introducing 2 nd Generation Intel Xeon Scalable Processors how Intel Speeds HPC performance Work Time System Peak Efficiency Software
More informationIntel Parallel Studio XE 2015
2015 Create faster code faster with this comprehensive parallel software development suite. Faster code: Boost applications performance that scales on today s and next-gen processors Create code faster:
More informationHardware OS & OS- Application interface
CS 4410 Operating Systems Hardware OS & OS- Application interface Summer 2013 Cornell University 1 Today How my device becomes useful for the user? HW-OS interface Device controller Device driver Interrupts
More informationA Scalable Event Dispatching Library for Linux Network Servers
A Scalable Event Dispatching Library for Linux Network Servers Hao-Ran Liu and Tien-Fu Chen Dept. of CSIE National Chung Cheng University Traditional server: Multiple Process (MP) server A dedicated process
More informationStatus Update About COLO (COLO: COarse-grain LOck-stepping Virtual Machines for Non-stop Service)
Status Update About COLO (COLO: COarse-grain LOck-stepping Virtual Machines for Non-stop Service) eddie.dong@intel.com arei.gonglei@huawei.com yanghy@cn.fujitsu.com Agenda Background Introduction Of COLO
More informationIntel Xeon Phi Coprocessor. Technical Resources. Intel Xeon Phi Coprocessor Workshop Pawsey Centre & CSIRO, Aug Intel Xeon Phi Coprocessor
Technical Resources Legal Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPETY RIGHTS
More informationReimagining OpenStack*
Reimagining OpenStack* Kristen Accardi *Other names and brands may be claimed as the property of others. 1 "Evaluators of OpenStack believe that complexity and difficulty of deployment are decreasing,
More informationRE-IMAGINING THE DATACENTER. Lynn Comp Director of Datacenter Solutions and Technologies
RE-IMAGINING THE DATACENTER Lynn Comp Director of Datacenter Solutions and Technologies IT: Period of Transformation Computer-Centric Network-Centric Human-Centric Focused on Productivity through automation
More informationI/O Design, I/O Subsystem, I/O-Handler Device Driver, Buffering, Disks, RAID January WT 2008/09
21 I/O Management (1) I/O Design, I/O Subsystem, I/O-Handler Device Driver, Buffering, Disks, RAID January 26 2009 WT 2008/09 2009 Universität Karlsruhe, System Architecture Group 1 Recommended Reading
More informationVirtual Machines Disco and Xen (Lecture 10, cs262a) Ion Stoica & Ali Ghodsi UC Berkeley February 26, 2018
Virtual Machines Disco and Xen (Lecture 10, cs262a) Ion Stoica & Ali Ghodsi UC Berkeley February 26, 2018 Today s Papers Disco: Running Commodity Operating Systems on Scalable Multiprocessors, Edouard
More informationApplying Polling Techniques to QEMU
Applying Polling Techniques to QEMU Reducing virtio-blk I/O Latency Stefan Hajnoczi KVM Forum 2017 Agenda Problem: Virtualization overhead is significant for high IOPS devices QEMU
More informationDatacenter Network Solutions Group
1 Enabling NFV features in kubernetes IVAN COUGHLAN IVAN.COUGHLAN@INTEL.COM Software Architect Kuralamudhan Ramakrishnan kuralamudhan.ramakrishnan@intel.com Senior Software Engineer Data Center Network
More informationENVISION TECHNOLOGY CONFERENCE. Functional intel (ia) BLA PARTHAS, INTEL PLATFORM ARCHITECT
ENVISION TECHNOLOGY CONFERENCE Functional Safety @ intel (ia) BLA PARTHAS, INTEL PLATFORM ARCHITECT Legal Notices & Disclaimers This document contains information on products, services and/or processes
More information