Next-Generation Hot-Swap Controllers
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1 Next-Generation Hot-Swap Controllers By Jim Davis, Product Mktg Engineer Staff, Cypress Semiconductor Corp. Current hot-swap controllers are great at what they do: simple yet reliable monitoring of critical load conditions and currents preventing power spikes that would otherwise damage either the backplane that the hot-swap board is plugged into or the hotswap board itself. The drawbacks with the current hot-swap solutions, however, are that they re expensive and single, fixedfunction solutions. Additionally, the lack of flexibility in this portion of the system prevents systems engineers from discovering new methods of reducing or smartly managing the power consumption in these systems let alone the potential cost savings that a new hot-swap controller solution may offer. This article will introduce how using a programmable approach can enable the next generation of reliable and programmable hot-swap controller systems to not only implement these critical tasks but also enable engineers to add more functionality and specifically customize implementations to their applications. Why Hot-Swap Control Is So Critical In describing the criticality of a hot-swap controller, let s first establish the jargon used in this article up front. First, the backplane is the chassis or the main board in the system to which hot-swap boards will be plugged into. The hot-swap board is the line-card or board that is designed to be inserted or removed without affecting the backplane (i.e. without having to power down or otherwise notify the backplane that you are inserting or removing the hot-swap board, think USB peripherals). Hot-swap control has three main functions: 1) protect the backplane from any sudden drop in voltage that would affect the overall system or other hot-swap boards connected to the system; 2) prevent spikes in loads from one hot-swap board from affecting any other portions of the backplane or other host-swap boards connected; and 3) by all means necessary, provide a breaker circuit function in the event a hot-swap board inserted into the backplane contains a short-circuit or other system failure that could severely affect the overall system. Systems that employ hot-swap designs do so because of the requirement for reliability and redundancy and so all means available must be employed to maintain the reliability of these systems. One might ask, if reliability is the utmost priority in these systems, why complicate them with a programmable implementation. After all, programmable approaches are inherently unreliable in that an engineer could inadvertently change how the device functions. The answer is both yes and no, given that programmability done right can be reliable. For example, Cypress enables a hot-swap controller solution via their software tool PSoC Creator by means of a tested and hardened packaged set of IP comprising a set configuration of the analog and digital building blocks of their PSoC Programmable System-On-Chip device (refer to Cypress AN64350). Additionally, a programmable architecture that is based on analog and digital peripherals, like the PSoC Programmable System-On-Chip, can implement the hot-swap controller without any reliance on any integrated indeterministic processor functionality (aka MCU) if the processor can enable a highly reliable approach on par with fixedfunction alternatives. Let s take a look at a quick comparison of a programmable solution versus a discrete, fixed-function device. In this case we will take a standard and popular -48V hot-swap controller, a Linear Tech LTC4261, and a Cypress PSoC Programmable System-On-Chip CY8C3866PVI-021ES2 configured as a hot-swap controller per the Cypress application note AN The two examples we ll look at is both the in-rush current limiting function (the first critical main function described above) and the over-current protection function (the second critical main function). Before we get started, let s examine the test setup. Both devices are connected to a simulated hot-swap board that essentially looks like a 24-ohm, 1,000 micro-farad load. The simulated backplane is the -48V power supply source. For the over-current test, a switch in the system will simulate a change in resistance of the system from 24-ohms to 6-ohms to force a spike in current in the system. In this first example, the objective of an in-rush current limiting function is to control the initial ramp of current drawn to a maximum level and then ensure that the system, at some defined point, backs down to a normal operating level of current consumption. The ideal graph for this type of function is show below in Figure 1. Hot-swap controllers: A programmable approach Page 1 of 6
2 Figure 1 - Ideal In-Rush Current Limiting The LTC4261 is configured to limit the inrush current to a maximum of 2A (or 16mV when measured across a sense resistor in the system). The results are shown in Figure 2. From the oscilloscope graph, you can see the behavior of the power in the system. The blue line in this figure shows the current in the system (actually the voltage across the sense resistor configured such that 1A is equivalent to 8mV). The LTC4261 example limits the inrush of current to 3.4A, approximately 1.4A higher than the desired maximum hopefully the system was designed with some headroom. The PSoC is configured to limit the inrush current to a maximum of 3A (or 24mV). The results are shown in Figure 3. From the oscilloscope graph, the blue line in this figure clearly shows more precise control of the inrush current roughly matching that of the ideal drawing (figure 1). In the end, the PSoC example limits the inrush of current to 2.8A (or 22.2mV). Figure 2 - LTC4261 In-Rush Current Limiting Hot-swap controllers: A programmable approach Page 2 of 6
3 Figure 3 - PSoC In-Rush Current Limiting In this second example, the objective of the over-current protection is to detect and limit the amount of current drawn by the hot-swap board for a set amount of time and, if necessary, shut down the hot-swap board to protect the backplane. The ideal graph for this type of function is shown below in Figure 4. For this example, both the LTC4261 and PSoC solutions are configured to limit the maximum over-current to 6.25A (50mV) for a maximum of 500µs (PSoC) or 512µs (LTC4261). The resulting oscilloscope captures for the two solutions are shown below (LTC4261: Figure 5; PSoC: Figure 6). From the graphs you can see that both approaches perform fairly well during this test; however, the PSoC solution still outperforms the discrete architecture. The LTC4261 limits the over-current level to a maximum of 7A (56.0mV) and successfully, after 512µs, shuts the system down. The PSoC solution limits the over-current level to a maximum of 6.3A (50.4mV) and also successfully shuts the system down after 500µs. The blue lines in these oscilloscope captures again represent the current in the system (via the voltage across a current sense resistor, 1A=8mV). Figure 4 - Ideal Over-Current Limiting Hot-swap controllers: A programmable approach Page 3 of 6
4 Figure 5 - LTC4261 Over-Current Limiting Figure 6 - PSoC Over-Current Limiting Extending the Capability of a Hot-Swap Controller with Programmability As seen from the previous section, a programmable solution can be configured to not only be as reliable, but also can improve the performance of a hot-swap controller function in a system versus discrete, fixed-function devices. The true benefit of a programmable approach, however, just starts here. The additional benefits of a programmable hot-swap controller such as that offered by Cypress s PSoC Programmable System-on-Chip, includes 1) the ability to customize the hot-swap controller specifically to the system s requirements versus requiring the system to comply to the device; 2) enabling additional errorchecking such as detecting whether required external components like the power-controlling FET and sense resistors are installed and working; 3) adding additional, disparate functions not normally found in the primary power domains of hot-swap controllers like thermal management functions, additional customized communications interfaces like PMBus to the backplane or hot-swap board s host application processors; and 4) there are many other customizations a design engineer can add as well because we re implementing the functionality with a programmable architecture. Hot-swap controllers: A programmable approach Page 4 of 6
5 With a discrete, fixed-function hot-swap controller, you must design your system to comply within its parameters such as designing the hot-swap board and backplane to operate within the hot-swap controller s ability to limit the inrush current, overcurrent, and breaker currents. With a programmable architecture, you simply set the current limits that your system is designed to operate within. For example, Cypress s hot-swap controller design using its PSoC Programmable System-On- Chip devices are configured via their software tool PSoC Creator with a graphical customizer (figure 7) which allows you to easily configure these parameters. Figure 7 - Cypress PSoC Creator Hot-Swap Controller Customizer In addition to simply customizing the parameters of a hot-swap controller, programmable approaches also enable additional functionality to provide in-system board check-out s and error-checking to ensure required external components are installed and operational. For example, the Cypress Application Note AN64350, a PSoC-based hot-swap controller solution, includes functionality to ensure the power-controlling FET, which limits the flow of power into the hot-swap board, as well as the current sense resistor circuitry, required to measure the current draw of the hot-swap board, are not only installed but operating within system limits. Should this functionality not meet requirements, the programmable architecture prevents power from flowing to the hot-swap board which would otherwise cause a catastrophic failure on the backplane and hot-swap board. Finally, the ultimate benefit that a programmable hot-swap controller offers is the ability to add functionality that either compliments the primary power domain management of the hot-swap board or completely disparate functionality that a system engineer would not normally think about. For example, many systems include hot-swap fan trays to provide cooling management and operational functions to a system. With the right programmable architecture, a designer could easily implement not only the hot-swap controller functionality of the system but also add fan or thermal management controls to the same device. With a PSoC device, for example, an engineer simply has to add the hot-swap controller IP to their design and then add the closed-loop fan controller IP to generate an all-in-one hot-swap fan tray controller solution this could be a reduction in components on this board from as many as four relatively high cost devices into a single chip solution. Additionally, with a programmable approach, you can add other functionality like I2C or PMBus interfaces to other processors to report current and voltage usage of the primary power rail so higher-level decisions can be made in the system such as shutting down blades in the system to dynamically reduce overall power consumption. In this article we reviewed the criticality of hot-swap controllers, how programmability done right can be reliable and how programmability greatly extends the capability of the hot-swap control function within a single-device. With the growing need to not only reduce cost but increase reliability and integration of components within systems like these, programmable architectures like Cypress s PSoC Programmable System-On-Chip are enabling the next-generation of hot-swap controllers. Hot-swap controllers: A programmable approach Page 5 of 6
6 Cypress Semiconductor 198 Champion Court San Jose, CA Phone: Fax: Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PSoC Designer, Programmable System-on-Chip, and PSoC Express are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Hot-swap controllers: A programmable approach Page 6 of 6
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1.20 Features Single or differential inputs Adjustable between 2 and 32 inputs Software controlled Inputs may be pins or internal sources No simultaneous connections Bidirectional (passive) General Description
More informationEZ I 2 C Slave. Features. General Description. When to use a EZ I 2 C Slave 1.50
PSoC Creator Component Data Sheet EZ I 2 C Slave 1.50 Features Industry standard Philips I 2 C bus compatible interface Emulates common I 2 C EEPROM interface Only two pins (SDA and SCL) required to interface
More informationW H I T E P A P E R. Introduction. Devices. Energy Comparison of Cypress F-RAM and EEPROM
W H I T E P A P E R Harsha Medu, Applications Engineer Cypress Semiconductor Corp. Energy Comparison of Cypress and Abstract (Ferroelectric Random Access Memory) is a nonvolatile memory that uses a ferroelectric
More informationThis section describes the various input and output connections for the SysInt Component.
1.0 Features Generating interrupts from hardware signals Assigning interrupts to a CPU core Configuring interrupt priority Interrupt vectoring and control General Description The Component is a graphical
More informationThis optional pin is present if the Mode parameter is set to SyncMode or PulseMode. Otherwise, the clock input does not show.
1.50 Features Up to 8-bit General Description The allows the firmware to output digital signals. When to Use a Use a when the firmware needs to interact with a digital system. You can also use the as a
More informationGreenPAK Universal Development Board User Guide
User Guide Silego Technology Corporate Headquarters 1715 Wyatt Drive Santa Clara, CA 95054 USA Phone: 408-327-8800 http:// Copyrights Copyright 2010 Silego Technology. The information contained herein
More informationThis input determines the next value of the output. The output does not change until the next rising edge of the clock.
1.30 Features Asynchronous reset or preset Synchronous reset, preset, or both Configurable width for array of s General Description The stores a digital value. When to Use a Use the to implement sequential
More informationUse the Status Register when the firmware needs to query the state of internal digital signals.
PSoC Creator Component Datasheet Status Register 1.80 Features Up to 8-bit Status Register Interrupt support General Description The Status Register allows the firmware to read digital signals. When to
More informationUse a DieTemp component when you want to measure the die temperature of a device.
PSoC Creator Component Datasheet Die Temperature (DieTemp) 2.0 Features Accuracy of ±5 C Range 40 C to +140 C (0xFFD8 to 0x008C) Blocking and non-blocking API General Description The Die Temperature (DieTemp)
More informationH O S T. FX2 SX2 Back - to - Back Setup. Project Objective. Overview
FX2 SX2 Back - to - Back Setup Project Objective Project Name: FX2_SX2 Programming Language: C Associated Part Families: CY7C68013A,CY7C68001 Software Version: Keil µvision2 Related Hardware: CY3682/CY3684
More informationThis section describes the various input and output connections for the Voltage Fault Detector.
PSoC Creator Component Datasheet Voltage Fault Detector (VFD) 2.20 Features Monitor up to 32 voltage inputs User-defined over and under voltage limits Simply outputs a good/bad status result General Description
More informationTHIS SPEC IS OBSOLETE
THIS SPEC IS OBSOLETE Spec No: 002-09373 Spec Title: AN209373 - F2MC-FM3 Family OpenOCD GUI Frontend Replaced by: 002-0586 AN209373 This application note describes how to use on-board Open On-Chip Debug
More informationPSoC 6 Current Digital to Analog Converter (IDAC7)
1.0 Features Six current ranges (4.96 ua to 635 ua) Sink or Source current 7-bit resolution Two IDACs can be put in parallel to form an 8-bit IDAC Add external resistor for VDAC functionality General Description
More informationFor More Information Please contact your local sales office for additional information about Cypress products and solutions.
The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix MB. However, Cypress will offer these products
More informationW H I T E P A P E R. Timing Uncertainty in High Performance Clock Distribution. Introduction
W H I T E P A P E R Brijesh A Shah, Cypress Semiconductor Corp. Timing Uncertainty in High Performance Clock Distribution Abstract Several factors contribute to the timing uncertainty when using fanout
More informationComparator (Comp) Features. General Description. When to use a Comparator Low input offset. User controlled offset calibration
1.50 Features Low input offset User controlled offset calibration Multiple speed modes Low power mode Output routable to digital logic blocks or pins Selectable output polarity Configurable operation mode
More information1-Mbit (64K x 16) Static RAM
1-Mbit (64K x 16) Static RAM Features Temperature ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive-A: 40 C to 85 C Automotive-E: 40 C to 125 C Pin and function compatible with CY7C1021BV33
More informationSetting Oscillation Stabilization Wait Time of the main clock (CLKMO) and sub clock (CLKSO)
1.0 Features Selecting Clock mode Internal Bus Clock Frequency Division Control PLL Clock Control Setting Oscillation Stabilization Wait Time of the main clock (CLKMO) and sub clock (CLKSO) Interrupts
More informationPSoC Programmer Release Notes
SRN97283 Version 3.23.1 PSoC Programmer Release Notes Release Date: June 12, 2015 Thank you for your interest in PSoC Programmer. These release notes list all the new features, installation requirements,
More informationPSoC Blocks. CY8C20xx6/6A/6AS/6H/6L, CY8C20xx7/7S, CY7C643xx, CY7C604xx, CYONS2xxx, CYONSxNxxxx, CYRF89x35, CY8C20065, CY8C24x93, CY7C69xxx
Datasheet ADCINC V 3.00 001-45836 Rev. *H Incremental ADC Copyright 2008-2013 Cypress Semiconductor Corporation. All Rights Reserved. Resources PSoC Blocks API Memory (Bytes) CapSense I2C/SPI Timer Comparator
More informationCE CY8CKIT-042-BLE F-RAM Data Logger
CE210988 - CY8CKIT-042-BLE F-RAM Data Logger Objective This example project is based on a PSoC Creator starter design for the PSoC 4 device. It demonstrates how F-RAM can be used with the PSoC to capture
More informationPSoC 4 Voltage Comparator (Comp) Features. General Description. When to Use Comparator Low input offset. User controlled offset calibration
PSoC Creator Component Datasheet PSoC 4 Voltage Comparator (Comp) 1.10 Features Low input offset User controlled offset calibration Multiple speed modes Operates in Deep Sleep power mode Output routable
More information4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Features True dual-ported memory cells, which allow simultaneous reads of the same memory location 4K x 8 organization 0.65 micron
More informationOne 32-bit counter that can be free running or generate periodic interrupts
PSoC Creator Component Datasheet Multi-Counter Watchdog (MCWDT_PDL) 1.0 Features Configures up to three counters in a multi-counter watchdog (MCWDT) block Two 16-bit counters that can be free running,
More informationPSoC Creator Quick Start Guide
PSoC Creator Quick Start Guide Install Download PSoC Creator from www.cypress.com/psoccreator, or install from a kit CD. For assistance, go to http://www.cypress.com/go/support For features, system requirements,
More informationAutomatic reload of the period to the count register on terminal count
1.0 Features 7-bit read/write period register 7-bit count register that is read/write Automatic reload of the period to the count register on terminal count Routed load and enable signals General Description
More informationEZ-PD Analyzer Utility User Guide
EZ-PD Analyzer Utility User Guide Doc. No. 002-12896 Rev. ** Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 www.cypress.com Copyrights
More informationCE95314 PSoC 3, PSoC 4, and PSoC 5LP EZI2C
CE95314 PSoC 3, PSoC 4, and PSoC 5LP EZI2C Objective These code examples demonstrate the usage of the EZI2C slave and I 2 C master Components in PSoC 3, PSoC 4, and PSoC 5LP. Overview These code examples
More informationPSoC 4 Current Digital to Analog Converter (IDAC)
PSoC Creator Component Datasheet PSoC 4 Current Digital to Analog Converter (IDAC) 1.10 Features 7 or 8-bit resolution 7-bit range: 0 to 152.4 or 304.8 µa 8-bit range: 0 to 306 or 612 µa Current sink or
More information4-Mbit (256K x 16) Static RAM
4-Mbit (256K x 16) Static RAM Features Temperature ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive-A: 40 C to 85 C Automotive-E: 40 C to 125 C Pin and function compatible with CY7C1041BV33
More informationVoltage Fault Detector (VFD) Features. General Description. Input/Output Connections. When to Use a VFD. Clock Input 2.30
PSoC Creator Component Datasheet Voltage Fault Detector (VFD) 2.30 Features Monitor up to 32 voltage inputs User-defined over and under voltage limits Simply outputs a good/bad status result Programmable
More informationApplication Note. LCD Driver Based on the HT1621 Controller
Application Note AN LCD Driver Based on the HT Controller Author: Andrew Smetana Associated Project: Yes Associated Part Family: All PSoC Designer Version:. SP Associated Application Notes: AN8 Abstract
More informationSupported devices: CY8C29x66, CY8C27x43, CY8C28xxx, CY8C24x23, CY8C24x33, CY8C21x23, CY8C21x34, CY8C21x45, CY8C22x45, CY8C24x94
SMBus Slave Datasheet SMBusSlave V 2.00 001-81371 Rev. *A SMBusSlave Copyright 2012-2013 Cypress Semiconductor Corporation. All Rights Reserved. PSoC Blocks API Memory (Bytes) Resources Digital Analog
More informationMultifunction Serial Interface (PDL_MFS) Features. General Description. When to Use a PDL_MFS Component. Quick Start 1.0
1.0 Features Configures the Multi-Function Serial (MFS) Interface to one of the following modes: UART (Asynchronous normal serial interface) Clock synchronous serial interface (SPI and I 2 S can be supported)
More informationBase Timer Channel (BT) Features. General Description. When to Use a PDL_BT Component 1.0
1.0 Features Four operating modes 16-bit PWM Timer 16-bit PPG Timer 16/32-bit Reload Timer 16/32-bit PWC Timer Trigger generation for ADC conversion General The Peripheral Driver Library (PDL) Base Timer
More information