Challenges for Non Volatile Memory (NVM) for Automotive High Temperature Operating Conditions Alexander Muffler

Transcription

1 Challenges for Non Volatile Memory (NVM) for Automotive High Temperature Operating Conditions Alexander Muffler Product Marketing Manager Automotive, X-FAB

2 Outline Introduction NVM Technology & Design NVM Product Integration & Application NVM Test in Production Conclusions

3 X-FAB - Who we are The More than Moore Foundry. 25 years proven track record of experience in pure-play foundry services for analog/mixed-signal semiconductor applications Specialty foundry with a comprehensive set of robust technologies serving automotive needs such as high temperature, high voltage and non volatile memories Technologies interfacing the real world Expertise in analog/mixed-signal IC production, MEMS and SiC with a focus on high-growth automotive, medical and industrial end markets with long lifecycles Strong design support to drive customer engagement over the long-term with successful technology leaders Technologies qualified according to AEC- Q100 Manufacturing excellence 6 wafer fab facilities in Germany, France, Malaysia and US Capacity: 94,000 wafer starts per month (200mm equiv.) ISO certification for all sites (in transition to IATF 16949) Audited and approved by major OEMs More than 3,800 employees worldwide

4 Introduction Overview of typical NVM applications in modern cars, especially in hightemperature environments (close to engine, exhaust etc.) Hall sensor Pressure sensor Inertial/gyro sensor Temperature sensor Optical sensor Touch panel sensor LIN & CAN bus transceiver Voltage regulator IC BLDC motor controller Full Bridge MOSFET Pre-Driver Mid.-Power 3 Phase BLDC Pre-Driver High temperature spots in different zones of a car (source: Battery Fuel Gauges Battery Monitors Battery Protectors Semicon Europa

5 Introduction Micro-electronic devices with embedded non volatile memory (NVM) for certain automotive applications are expected to be highly reliable within an extended operating temperature range (e.g. AEC-Q100 Grade 0: T amb,max = 150 C). The kind of NVM application (data storage, program storage etc.) and mission profile have a strong impact on the actual reliability requirements e.g. in terms of program endurance and data retention. Different aspects related to the chosen NVM technology and design, its integration in a product and application as well as the quality control by dedicated tests in production need special attention in order to enable robust and hightemperature capable NVM solutions for sub-micron nodes. Semicon Europa

6 NVM Technology & Design Technology: memory principle, technology node, wafer process architecture, materials, primitive devices etc. NVM technology determines possible performance and reliability (performance over use time) with their dependencies e.g. on operating conditions (T, V, ). Design: memory cell architecture, memory size, bias conditions for memory operations (write, erase, read), address mapping, trimming, etc. NVM design determines actual performance and reliability. Both NVM technology and design refer to the pure NVM part and its periphery (e.g. charge pumps, read-out circuitry). Semicon Europa

7 NVM Technology & Design Challenge: How to realize high-temperature capable NVM technology & design? Performance Temperature-dependent electrical parameters (compensation via design) Parasitic effects (e.g. increasing junction leakage at higher temperatures) Material properties (e.g. CTE mismatch, thermal limitations) Reliability (-> next slides) Semicon Europa

8 NVM Technology & Design Typical NVM specific reliability failure mechanisms NVM type Failure mechanism Corresp. failure modes Countermeasures Floating gate OTP SILC, thermionic emission Electrical disturb effects Data corruption during operation High gate oxide quality, adjusted programming conditions Floating gate EEPROM SILC, thermionic emission Interface / oxide charge trapping Electrical disturb effects Asymmetrical V T window narrowing Data corruption during operation High tunnel and gate oxide quality, adjusted programming conditions and number of cycles, reference trimming Charge trapping EEPROM (e.g. SONOS) vertical leakage Interface / oxide charge trapping Asymmetrical V T window narrowing High oxide quality, adjusted programming conditions, reference trimming Semicon Europa

9 NVM Technology & Design Typical NVM specific reliability failure mechanisms strong temperature impact NVM type Failure mechanism Corresp. failure modes Countermeasures Floating gate OTP SILC, thermionic emission Electrical disturb effects Data corruption during operation High gate oxide quality, adjusted programming conditions Floating gate EEPROM SILC, thermionic emission Interface / oxide charge trapping Electrical disturb effects Asymmetrical V T window narrowing Data corruption during operation High tunnel and gate oxide quality, adjusted programming conditions and number of cycles, reference trimming Charge trapping EEPROM (e.g. SONOS) vertical leakage Interface / oxide charge trapping Asymmetrical V T window narrowing High oxide quality, adjusted programming conditions, reference trimming Semicon Europa

10 NVM Technology & Design Typical NVM specific reliability failure mechanisms NVM type Failure mechanism Corresp. failure modes Countermeasures Floating gate OTP SILC, thermionic emission Electrical disturb effects Data corruption during operation High gate oxide quality, adjusted programming conditions Floating gate EEPROM SILC, thermionic emission Interface / oxide charge trapping Electrical disturb effects Asymmetrical V T window narrowing Data corruption during operation High tunnel and gate oxide quality, adjusted programming conditions and number of cycles, reference trimming Charge trapping EEPROM (e.g. SONOS) vertical leakage Interface / oxide charge trapping Asymmetrical V T window narrowing High oxide quality, adjusted programming conditions, reference trimming Semicon Europa

11 NVM Technology & Design EEPROM endurance: V T window lowering during w/e cycling due to different mechanisms that all may occur in parallel; in addition: temperature dependence of V T levels and read threshold. Partial compensation by NVM design possible. Source: A. Spinelli, Tutorial at ESREF Semicon Europa

12 NVM Technology & Design Typical NVM specific reliability failure mechanisms NVM type Failure mechanism Corresp. failure modes Countermeasures Floating gate OTP SILC, thermionic emission Electrical disturb effects Data corruption during operation High gate oxide quality, adjusted programming conditions Floating gate EEPROM SILC, thermionic emission Interface / oxide charge trapping Electrical disturb effects Asymmetrical V T window narrowing Data corruption during operation High tunnel and gate oxide quality, adjusted programming conditions and number of cycles, reference trimming Charge trapping EEPROM (e.g. SONOS) vertical leakage Interface / oxide charge trapping Asymmetrical V T window narrowing High oxide quality, adjusted programming conditions, reference trimming Semicon Europa

13 NVM Technology & Design EEPROM data retention: intrinsic retention limited by oxide tunneling and thermionic emission; retention after w/e cycling additionally affected by charge de-trapping (strong thermal acceleration) and SILC (strong field acceleration). Source: A. Spinelli, Tutorial at ESREF Semicon Europa

14 NVM Technology & Design Other, CMOS related failure mechanism that can influence the reliability of NVM FEOL Process BEOL Process Affected structure Gate oxide, MOS NMOS, PMOS HV MOS Metallization Capacitor, ILD, IMD Passivation Failure mechanism Stress induced leakage current (SILC) Time dependent dielectric breakdown (TDDB) Plasma process induced damage (P2ID) Hot carrier injection (HCI) Bias temperature instability (BTI) Latch-up (LU) Thermal runaway Electro / stress migration (EM / SM or SIV) Corrosion Delamination Time dependent dielectric breakdown (TDDB) Plasma process induced damage (P2ID) Cracking Semicon Europa

15 NVM Technology & Design Other, CMOS related failure mechanism that can influence the reliability of NVM FEOL Process BEOL Process Affected structure Gate oxide, MOS NMOS, PMOS HV MOS Metallization Capacitor, ILD, IMD Passivation Failure mechanism Stress induced leakage current (SILC) Time dependent dielectric breakdown (TDDB) Plasma process induced damage (P2ID) Hot carrier injection (HCI) Bias temperature instability (BTI) Latch-up (LU) Thermal runaway Electro / stress migration (EM / SM or SIV) Corrosion Delamination Time dependent dielectric breakdown (TDDB) Plasma process induced damage (P2ID) Cracking strong temperature impact Semicon Europa

16 NVM Product Integration & Application Good matching of embedded NVM and surrounding circuitry Suitable interface for access to NVM Good control and high stability of memory biasing conditions Implementation of advanced safety measures E.g. data error detection, data error correction (ECC), redundancy of data or memory Adjustment of NVM mission profile ( load management ) based on knowledge of reliability models and limitations E.g. de-rating of programming conditions, wear levelling, duty cycle adjustment Product reliability risk assessment with respect to potential NVM failures E.g. functional safety (ISO26262): determination of ASIL, FMEDA, failure rate evaluation Semicon Europa

17 NVM Product Integration & Application Even for ready-to-use NVM IP it is essential to consider specific requirements and guidelines for the product integration and application, e.g. Defined operating conditions IP specification IP test specification Specific application notes Common design integration reviews between NVM IP provider and user can help to identify issues at an early stage and to mitigate the risks. Semicon Europa

18 NVM Test in Production Design for testability (DfT) Measurement access to quality and reliability relevant parameters at test High test coverage with respect to critical circuitry elements and paths Implementation of on-chip test features (e.g. BIST) Enablement of electrical (over-) stressing for screening purpose Advanced production test flow Test of all relevant NVM operating modes within full required operating temperature range Data retention test for complementary NVM data patterns Parallel testing for cost reasons required Statistical data analysis for outlier detection Wafer probe T1 (e.g 25 C) Bake Wafer probe T2 e.g. 175 C Bake Final T3 e.g. -40 C Fig. 1: Example test flow Semicon Europa

19 Conclusions Realization of high-temperature capable NVM for automotive applications and their successful process and product integration are feasible. Example: NVM in 0.18 Micron Analog Mixed Signal HV CMOS Technology ( Semicon Europa

20 Conclusions In order to achieve this, a couple of challenges have to be mastered through appropriate measures: 1. Baseline technology setup 5. NVM test implementation 2. NVM module integration 4. NVM integration in product 3. NVM design NVM development Product development Semicon Europa

21 Thank You! Alexander Muffler Product Marketing Manager Automotive alexander.muffler[at]xfab.com

22 Abbreviations ASIL BIST EEPROM FMEDA HV IP MOS NVM OTP SILC SONOS Automotive Safety Integrity Level Built-In Self-Test Electrically Erasable Programmable Read-Only Memory Failure Modes, Effects and Diagnostics Analysis High Voltage Intellectual Property Metal Oxide Semiconductor Non Volatile Memory One Time Programmable (Memory) Stress Induced Leakage Current Silicon Oxide Nitride Oxide Silicon