High-speed, high-bandwidth DRAM memory bus with Crosstalk Transfer Logic (XTL) interface. Outline
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1 High-speed, high-bandwidth DRAM memory bus with Crosstalk Transfer Logic (XTL) interface Hideki Osaka Hitachi Ltd., Kanagawa, Japan Toyohiko Komatsu Hitachi Ltd., Kanagawa, Japan Susumu Hatano Elpida Memory Inc., Kanagawa, Japan Takeshi Wada Hitachi Ltd., Tokyo, Japan HITACHI, ELPIDA MEMORY Outline Requirements of server memory system Background of high-speed interconnect Mechanism of XTL Design of evaluation system 0.5-µm process TEST chip ( hysteresis receiver) 8 modules mountable PCB w/ folding coupler XTL Experimental result Conclusion 2
2 Requirements of server memory system Memory system for high-performance workstation and server High band width 200 Large capacity Low latency access 600 Low power 400 High availability 200 Cost 0 Freq [MHz] Year CPU DRAM Target DDR- XTL 3 Background of high-speed interconnect Bus cheaper than point-to-point Low pin count and small real estate owing to sharing signal However, hard to manage trade-off speed-up and noise ISI (Inter Symbol Interference) limits speed-up Multi- reflections between branch points Important impedance flatness Information in a transition of datum Rising: L H, Falling: H L No change: Stable datum (L L/H H) R x.2 R R D0 D D2 LSI LSI LSI 4 information information Multi-reflection noise on bus 2
3 5 Features of XTL Many modules mountable a bus: 4 to 8 DIMM (conventionally 2 4) High speed operation: > 500Mbps Very small reflection noise ( lesser ISI ) Signal transmitter: Directional coupler formed in PCB Small impedance violation Transition data capture (NRZ RZ ) Hot Swappable DC Isolation (signal) C-MOS technology Push-pull driver (same as conventional SSTL driver) Hysteresis receiver Low cost PCB ( 2 signal layers ) NRZ coupler RZ Mechanism of XTL (WRITE mode) No branch on a mainline:impedance flat of the mainline Drive NRZ signal from Memory Controller Transform to RZ signal at coupler and Demodulate by hysteresis MC receiver Driver No brunch NRZ Rtt Flat impedance and small reflection RZ DRAM 6 demodulation NRZ Hysteresis receiver Directional coupler 3
4 Mechanism of XTL (READ mode) READ mode Opposite direction, but the same mechanism as WRITE mode DC isolation Driver No brunch Flat impedance and small reflection MC Hysteresis receiver DRAM 7 Design of XTL evaluation system Evaluate XTL performance for DRAM memory bus 0.5-µm DRAM process chip (HS-TEG) I/O circuits Driver: Impedance and slew-rate controllable Receiver: Controllable hysteresis Vernier timing controller PCB (Motherboard and DIMM) 8 modules mountable motherboard 2 layers for folding coupler ( total 8 layers stacking) Low cost using conventional technology Line width and spacing = 00 / 00 µ m [4 mil] 8 4
5 Receiver design Demodulate from RZ signal to NRZ High-speed operational receiver Receiver consists 2 controllable-offset comparators + RS-FF Hysteresis offset:± 50, ± 00, ± 50 mv Input waveform (RZ signal) Vthp Vout Vthn Output waveform (NRZ signal) IN Vref HST 3 RST S OUT IN Vref Vthn Vthp Vin R OUT (a) Hysteresis receiver circuit 9 HST (b) Controllable offset comparator Folding Coupler Low cost low noise folding line structure Reduce layers High density Avoid noise from adjacent signals Parameters Coupler 40 mm [.57'] length line Zo ( mainline ) = 75 Ω Coupling coeff. 25 % L/S = 00/00 µ m [4mil] Sub-coupling To chip A Vtt Vtt Signal from 2 To Rtt 3 controller To chip B Mainline 0 XTL coupler layout on a PCB layer 5
6 HS-TEG test chip Features: XTL interface test chip: 0.5-µ m process 54-ball CSP (Chips Scale Package) No DRAM cell '// RWKHUÀ IXQF YHUQLHU '4ÃSRUW ';ÃSRUW Figure 6. DIE photo of HS-TEG chip Evaluation PCB 8 modules mountable 4 bytes bus width Low cost PCB using conventional technology L/S = 00/00 µ m [4 mil] 2 Signal layers (total 8 layers) C ontroller (down side) Mother Board XTL wiring area DIMMs PC interface 2 Figure 7. Test board; a mother board and mounted 8 modules;all modules mounted 4 HS-TEG chips. 6
7 Layout of XTL signals 240-pin SMD DIMM socket Directional coupler Termination resister 3 Experimental results () Impedance measured when,4 and 8 DIMMs loaded Impedance variation [ohm] of mainline < ± 6 Ω ISI effect minimal TDR waveform [V] [ohm] Round trip flight time 7 [ns] DIMMx DIMMx4 DIMMx8 TDR : Time Domain Reflectometry) 4 0. HS-TEG capacitive reflection TIME [ns] TDR waveform; drive pulse applied to the ball of the HS-TEG of the mainline 7
8 Experimental results (2) XTL Signaling Drive falling time : ps [20-80%] XTL signal: mv (@ 8 th module) Coupling ration: Kb 24 % ( = XTL signal / Drive pulse) Drive pulse of the mainline 500 mv (a) HS-TEG point (b) Termination point XTL signal 00 mv ns (c) st (d) 4th (e) 8th 5 Drive pulse and XTL signal Experimental results (3) Eye diagram of XTL signaling (write mode) 400 Mbps 200 mv 2 ns 200 mv 2 ns 200 mv 2 ns (a) 400 Mbps at st module (b) 400 Mbps at 4th module (c) 400 Mbps at 8th module 600 Mbps 200 mv ns 200 mv ns 200 mv ns (d) 600 Mbps at st module (e) 600 Mbps at 4th module (f) 600 Mbps at 8th module 800 Mbps mv ns 200 mv ns 200 mv ns (g) 800 Mbps at st module (h) 800 Mbps at 4th module (i) 800 Mbps at 8th module 8
9 Experimental results (4) Max. operation frequency w/ Error Rate Tester Adjacent signals drove First module: over 600 Mbps 8th modules: over 500 Mbps Adjacent noise: 49.6 mv [600 Mbps / 4 th module] pulse MC #8 # #4 Table Maximum operation frequency Write Read DIMM# (Near End) DIMM#8 (Far end) 62 Mbps 523 Mbps 604 Mbps 524 Mbps Typ. Condition Room Temp. BERT < Conclusion XTL interconnection applied to DRAM memory bus Evaluation results Over 500 Mbps operation with 8 modules both read and write Test chip 0.5-µ m DRAM process Receiver: Controllable offset ± 50, ± 00, ± 50 mv Test board Only two signal layers for four byte bus Folding coupler reduces signal layers and avoid adjacent noise Hot swappable ( DC isolated signal) 8 9
10 Appendix Signaling of various memory buses Preamble of DQ/DQS Clock routing of DQ / DQS 9 Signaling of various memory buses DDR-SDRAM interface comparison Multi-reflection causes Inter-symbol interference degradation LVTTL(PC00/33) SSTL(DDR-II) XTL (proposal) Interface Low Voltage TTL Stub Series Crosstalk Terminated Logic Transceiver Logic Driver push-pull/open-drain push-pull push-pull Receiver Single-end/Differential Differential Hysteresis Branch Direct branch Series Termination Directional coupler Reflection Large 33 % Medium 20 % Small 6 % Bus Branch Main Line Stub Line Main Line Zo Zo Γ Γ 33% 33% Γ Γ 20% * 20% * 6% Rstub 6% Zo Z Stub Line Stub Line MC Main Line Z DRAM Zo Rtt 20 0
11 Preamble of DQ/DQS Low-state preamble before DQ/DQS Halved XTL signal from idle state to first data Basic Write Operation CLK/ CLKB Command Address t0 t t2 t3 t4 t5 t6 ACTV NOP WRITE NOP NOP NOP ROW COLUMN Preamble BL=4 DQ(TX) D0 D D2 D3 DQS(TX) DQ(RX) Preamble added before DQ and DQS and internal reset signal of DRAM receiver DQS(RX) RST (internal signal ) Output of XTL receiver Halved XTL signal D0 D D2 D3 2 Clock routing of DQ / DQS Read DQ/DQS same as CLK Controller (HS-TEG) DIMM DIMM2 DIMM8 CLK/ CLKB 2 DQS/ DQSB 2 vernier DQ vernier 8 CLK GEN. Vtt Rtt Termination L XTL 22
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