UM1855 User manual. Evaluation board with STM32L476ZGT6 MCU. Introduction

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1 UM855 User manual Evaluation board with STML76ZGT6 MCU Introduction The STML76G-EVAL evaluation board is designed as complete demonstration and development platform for STMicroelectronics ARM Cortex -M-core-based STML76ZGT6 microcontroller with three I ² C buses, three SPI and six USART ports, CAN port, SWPMI, two SAI ports, -bit ADC, -bit DAC, LCD driver, internal 8-Kbyte SRAM and -Mbyte Flash memory, Quad-SPI port, touch sensing capability, USB OTG FS port, LCD controller, flexible memory controller (FMC), JTAG debug port. STML76G-EVAL, shown in Figure, is used as reference design for user application development, although it is not considered as final application. A full range of hardware features on the board helps users to evaluate all on-board peripherals such as USB, USART, digital microphones, ADC and DAC, dot-matrix TFT LCD, LCD glass module, IrDA (supported up to version MB C-0 of the board), LDR, SRAM, NOR Flash memory device, Quad-SPI Flash memory device, microsd card, sigma-delta modulators, smartcard with SWP, CAN transceiver, EEPROM, RF-EEPROM. Extension headers allow connecting daughterboards or wrapping boards. ST-LINK/V- in-circuit debugger and flashing facility is integrated on the mainboard. Figure. STML76G-EVAL evaluation board. Picture not contractual. November 06 DocID075 Rev 5 /0

2 Contents UM855 Contents Overview Features Demonstration software Order code Unpacking recommendations Hardware layout and configuration ST-LINK/V Drivers ST-LINK/V- firmware upgrade ETM trace Power supply Supplying the board through ST-LINK/V- USB port Using ST-LINK/- along with powering through CN power jack Clock references Reset sources Boot Boot options Bootloader limitations Audio Digital microphones Headphones outputs Limitations in using audio features USB OTG FS port STML76G-EVAL used as USB device STML76G-EVAL used as USB host Configuration elements related with USB OTG FS port Limitations in using USB OTG FS port Operating voltage RS- and IrDA ports RS- port IrDA port Limitations /0 DocID075 Rev 5

3 UM855 Contents.9. Operating voltage LPUART port microsd card Limitations Operating voltage Motor control Board modifications to enable motor control Limitations CAN Limitations Operating voltage Extension connectors CN6 and CN LCD glass module daughterboard Limitations TFT LCD panel User LEDs Physical input devices Limitations Operational amplifier and comparator Operational amplifier Comparator Analog input, output, VREF SRAM device Limitations Operating voltage NOR Flash memory device Limitations Operating voltage EEPROM Operating voltage RF-EEPROM Quad-SPI Flash memory device Limitations Operating voltage Touch-sensing button DocID075 Rev 5 /0 5

4 Contents UM Limitations Smartcard, SWP Limitations Operating voltage Near-field communication (NFC) Dual-channel sigma-delta modulators STPMSL STPMSL presentation STPMSL settings STPMSL power metering STPMSL for PT00 measurement Limitations STML76ZGT6 current consumption measurement IDD measurement principle - analog part Low-power-mode IDD measurement principle - logic part IDD measurement in dynamic run mode Calibration procedure Connectors RS- D-sub male connector CN Power connector CN LCD daughterboard connectors CN and CN Extension connectors CN6 and CN ST-LINK/V- programming connector CN ST-LINK/V- Standard-B USB connector CN JTAG connector CN ETM trace debugging connector CN microsd card connector CN ADC/DAC connector CN RF-EEPROM daughterboard connector CN Motor control connector CN USB OTG FS Micro-AB connector CN CAN D-sub male connector CN NFC connector CN Appendix A Schematic diagrams /0 DocID075 Rev 5

5 UM855 Contents Appendix B Federal Communications Commission (FCC) and Industry Canada (IC) Compliance Statements B. FCC Compliance Statement B.. Part B.. Part B.. Part B. IC Compliance Statement B.. Compliance Statement B.. Déclaration de conformité Revision history DocID075 Rev 5 5/0 5

6 List of tables UM855 List of tables Table. Setting of configuration elements for trace connector CN Table. Power-supply-related jumper settings Table. X-crystal-related solder bridge settings Table. X-crystal-related solder bridge settings Table 5. Boot selection switch Table 6. Bootloader-related jumper setting Table 7. Digital microphone-related jumper settings Table 8. Configuration elements related with USB OTG FS port Table 9. Settings of configuration elements for RS- and IrDA ports Table 0. Hardware settings for LPUART Table. Terminals of CN8 microsd slot Table. Motor control terminal and function assignment Table. CAN related jumpers Table. LCD-daughterboard-related configuration elements Table 5. LCD glass element mapping - segments 0 to Table 6. LCD glass element mapping - segments 0 to Table 7. LCD glass element mapping - segments 0 to Table 8. LCD glass element mapping - segments 0 to Table 9. Access to TFT LCD resources with FMC address lines A0 and A Table 0. Assignment of CN9 connector terminals of TFT LCD panel Table. Port assignment for control of LED indicators Table. Port assignment for control of physical input devices Table. Setting of jumpers related with potentiometer and LDR Table. SRAM chip select configuration Table 5. NOR Flash memory-related configuration elements Table 6. Configuration elements related with Quad-SPI device Table 7. Touch-sensing-related configuration elements Table 8. Assignment of ports for ST80CDR control Table 9. Configuration elements related with smartcard and SWP Table 0. CN NFC connector terminal assignment Table. JP jumper settings during IDD measurement with calibration Table. RS- D-sub (DE-9M) connector CN9 with HW flow control and ISP support Table. CN and CN daughterboard connectors Table. Daughterboard extension connector CN Table 5. Daughterboard extension connector CN Table 6. USB Standard-B connector CN Table 7. JATG debugging connector CN Table 8. Trace debugging connector CN Table 9. microsd card connector CN Table 0. Analog input-output connector CN Table. RF-EEPROM daughterboard connector CN Table. Motor control connector CN Table. USB OTG FS Micro-AB connector CN Table. CAN D-sub (DE-9M) 9-pins male connector CN Table 5. NFC CN terminal assignment Table 6. Document revision history /0 DocID075 Rev 5

7 UM855 List of figures List of figures Figure. STML76G-EVAL evaluation board Figure. STML76G-EVAL hardware block diagram Figure. STML76G-EVAL main component layout Figure. USB composite device Figure 5. CN power jack polarity Figure 6. CN0, CN top view Figure 7. PCB top-side rework for motor control Figure 8. PCB underside rework for motor control Figure 9. LCD glass module daughterboard in display position Figure 0. LCD glass module daughterboard in I/O-bridge position Figure. LCD glass display element mapping Figure. NFC board plugged into STML76G-EVAL board Figure. Routing of STPMSL dual-channel sigma-delta modulators Figure. Power measurement principle schematic diagram Figure 5. STPMSL power metering schematic diagram Figure 6. Temperature measurement principle schematic diagram Figure 7. Schematic diagram of the analog part of IDD measurement Figure 8. Schematic diagram of logic part of low-power-mode IDD measurement Figure 9. Low-power-mode IDD measurement timing Figure 0. RS- D-sub (DE-9M) 9-pole connector (front view) Figure. Power supply connector CN (front view) Figure. USB type B connector CN7 (front view) Figure. JTAG debugging connector CN5 (top view) Figure. Trace debugging connector CN (top view) Figure 5. microsd card connector CN Figure 6. Analog input-output connector CN8 (top view) Figure 7. RF-EEPROM daughterboard connector CN (front view) Figure 8. Motor control connector CN (top view) Figure 9. USB OTG FS Micro-AB connector CN (front view) Figure 0. CAN D-sub (DE-9M) 9-pole male connector CN5 (front view) Figure. NFC female connector CN (top view) Figure. STML76G-EVAL top Figure. MCU, LCD daughterboard and I/O expander interfaces Figure. STML76G-EVAL MCU part Figure 5. STML76G-EVAL MCU part Figure 6. LCD glass module daughterboard connectors Figure 7. I/O expander Figure 8. Power supply Figure 9. Smartcard, SWP and NFC Figure 0. USART and IrDA Figure. SRAM and NOR Flash memory devices Figure. TFT LCD Figure. Extension connector Figure. Quad-SPI Flash memory device Figure 5. microsd card Figure 6. Physical control peripherals Figure 7. CAN transceiver Figure 8. Touch-sensing device DocID075 Rev 5 7/0 8

8 List of figures UM855 Figure 9. USB_OTG_FS port Figure 50. IDD measurement Figure 5. Audio codec device Figure 5. STPMSL and PT Figure 5. RF-EEPROM and EEPROM Figure 5. Motor control connector Figure 55. JTAG and trace debug connectors Figure 56. ST-LINK/V /0 DocID075 Rev 5

9 UM855 Overview Overview. Features STML76ZGT6 microcontroller with -Mbyte Flash memory and 8-Kbyte RAM Four power supply options: power jack, ST-LINK/V- USB connector, USB OTG FS connector, daughterboard Microcontroller supply voltage:. V or range from.7 V to.6 V Two MEMS digital microphones Two jack outputs for stereo audio headphone with independent content Slot for microsd card supporting SD, SDHC, SDXC -Gbyte microsd card bundled 6-Mbit (M x 6 bit) SRAM device 8-Mbit (8M x 6 bit) NOR Flash memory device 56-Mbit Quad-SPI Flash memory device with double transfer rate (DTR) support RF-EEPROM with I ² C bus EEPROM supporting MHz I ² C-bus communication speed RS- port configurable for communication or MCU flashing IrDA transceiver (only supported up to MB C-0 version of the board, no more supported from MB C-0 version) USB OTG FS Micro-AB port CAN.0A/B-compliant port Joystick with four-way controller and selector Reset and wake-up / tamper buttons Touch-sensing button Light-dependent resistor (LDR) Potentiometer Coin battery cell for power backup LCD glass module daughterboard (MB979) with 0x8-segment LCD driven directly by STML76ZGT6.8-inch 0x0 dot-matrix color TFT LCD panel with resistive touchscreen Smartcard connector and SWP support NFC transceiver connector Connector for ADC input and DAC output Power-metering demonstration with dual-channel, sigma-delta modulator PT00 thermal sensor with dual-channel, sigma-delta modulator MCU current consumption measurement circuit Access to comparator and operational amplifier of STML76ZGT6 Extension connector for motor control module JTAG/SWD, ETM trace debug support, user interface through USB virtual COM port, embedded ST-LINK/V- debug and flashing facility Extension connector for daughterboard DocID075 Rev 5 9/0 00

10 Overview UM855. Demonstration software Demonstration software is preloaded in the STML76ZGT6 Flash memory, for easy demonstration of the device peripherals in stand-alone mode. For more information and to download the latest available version, refer to the STML76G-EVAL demonstration software available on the website.. Order code To order the evaluation board based on the STML76ZGT6 MCU, use the order code STML76G-EVAL.. Unpacking recommendations Before the first use, make sure that, no damage occurred to the board during shipment and no socketed components are loosen in their sockets or fallen into the plastic bag. In particular, pay attention to the following components:. Quartz crystal (X position). microsd card in its CN8 receptacle. RF-EEPROM board (ANT7-MLR-A) in its CN connector For product information related with STML76ZGT6 microcontroller, visit website. 0/0 DocID075 Rev 5

11 UM855 Hardware layout and configuration Hardware layout and configuration The STML76G-EVAL evaluation board is designed around STML76ZGT6 target microcontroller in LQFP -pin package. Figure illustrates STML76ZGT6 connections with peripheral components. Figure shows the location of main components on the evaluation board. Figure. STML76G-EVAL hardware block diagram Note: If the STML76G-EVAL board version is greater than or equal to MB C-0, the IrDA feature is not populated. Any mention of the IrDA feature in this User manual refers to the previous versions of the board (up to MB C-0). The version of the board is written on the sticker placed on bottom side of the board. DocID075 Rev 5 /0 00

12 Hardware layout and configuration UM855 Figure. STML76G-EVAL main component layout /0 DocID075 Rev 5

13 UM855 Hardware layout and configuration. ST-LINK/V- ST-LINK/V- facility for debug and flashing of STML76ZGT6, is integrated on the STML76G-EVAL evaluation board. Compared to ST-LINK/V stand-alone tool available from STMicroelectronics, ST-LINK/V- offers new features and drops some others. New features: USB software re-enumeration Virtual COM port interface on USB Mass storage interface on USB USB power management request for more than 00mA power on USB Features dropped:.. Drivers SWIM interface The USB connector CN7 can be used to power STML76G-EVAL regardless of the ST-LINK/V- facility use for debugging or for flashing STML76ZGT6. This holds also when ST-LINK/V stand-alone tool is connected to CN or CN5 connector and used for debugging or flashing STML76ZGT6. Section. provides more detail on powering STML76G-EVAL. For full detail on both versions of the debug and flashing tool, the stand-alone ST-LINK/V and the embedded ST-LINK/V-, refer to Before connecting STML76G-EVAL to a Windows 7, Windows 8 or Windows XP PC via USB, a driver for ST-LINK/V- must be installed. It can be downloaded from In case the STML76G-EVAL evaluation board is connected to the PC before installing the driver, the Windows device manager may report some USB devices found on STML76G-EVAL as Unknown. To recover from this situation, after installing the dedicated driver downloaded from the association of Unknown USB devices found on STML76G-EVAL to this dedicated driver must be updated in the device manager manually. It is recommended to proceed using USB Composite Device line, as shown in Figure. Figure. USB composite device DocID075 Rev 5 /0 00

14 Hardware layout and configuration UM855.. ST-LINK/V- firmware upgrade For its own operation, ST-LINK/V- employs a dedicated MCU with Flash memory. Its firmware determines ST-LINK/V- functionality and performance. The firmware may evolve during the life span of STML76G-EVAL to include new functionality, fix bugs or support new target microcontroller families. It is therefore recommended to keep ST-LINK/V- firmware up to date. The latest version is available from ETM trace The connector CN can output trace signals used for debug. By default, the evaluation board is configured such that, STML76ZGT6 signals PE through PE5 are not connected to trace outputs Trace_D0, Trace_D, Trace_D, Trace_D and Trace_CK of CN. They are used for other functions. Table shows the setting of configuration elements to shunt PE, PE, PE and PE5 MCU ports to CN connector, to use them as debug trace signals. Table. Setting of configuration elements for trace connector CN Element Setting Use of PE, PE, PE, PE5 terminals of STML76ZGT6 R0 SB6 R0 R8 SB0 R85 SB8 R86 SB9 R0 in SB6 open R0 out SB6 closed R0 in R0 out R8 in SB0 open R8 out SB0 closed R85 in SB8 open R85 out SB8 closed R86 in SB9 open R86 out SB9 closed Default setting. PE connected to LCDSEG8 and memory address line A. PE connected to TRACE_CK on CN. A pulled down. Default setting. PE connected to LCDSEG9 and memory address line A9. PE connected to TRACE_D0 on CN. A9 pulled down. Default setting. PE connected to memory address line A0. PE connected to TRACE_D on CN. A0 pulled down. Default setting. PE5 connected to memory address line A. PE5 connected to TRACE_D on CN. A pulled down. Default setting. PE6 is used for address bit A. PE6 connected to TRACE_D on CN. A pulled down. Warning: Enabling the CN trace outputs through hardware modifications described in Table results in reducing the memory address bus width to 9 address lines and so the addressable space to 5 Kwords of 6 bits. As a consequence, the on-board SRAM and NOR Flash memory usable capacity is reduced to 8 Mbits. /0 DocID075 Rev 5

15 UM855 Hardware layout and configuration. Power supply STML76G-EVAL evaluation board is designed to be powered from 5 V DC power source. It incorporates a precise polymer Zener diode (Poly-Zen) protecting the board from damage due to wrong power supply. One of the following four 5V DC power inputs can be used, upon an appropriate board configuration: Power jack CN, marked PSU_E5V on the board. A jumper must be placed in PSU location of JP7. The positive pole is on the center pin as illustrated in Figure 5. Standard-B USB receptacle CN7 of ST-LINK/V-, offering enumeration feature described in Section... Micro-AB USB receptacle CN of USB OTG interface, marked OTG_FS on the board. Up to 500mA can be supplied to the board in this way. Pin 8 of CN6 extension connector for custom daughterboards, marked D5V on the board. No external power supply is provided with the board. LD7 red LED turns on when the voltage on the power line marked as +5V is present. All supply lines required for the operation of the components on STML76G-EVAL are derived from that +5V line. Table describes the settings of all jumpers related with powering STML76G-EVAL and extension board. _MCU is STML76ZGT6 digital supply voltage line. It can be connected to either fixed. V or to an adjustable voltage regulator controlled with RV potentiometer and producing a range of voltages between.7 V and.6 V... Supplying the board through ST-LINK/V- USB port To power STML76G-EVAL in this way, the USB host (a PC) gets connected with the STML76G-EVAL board s Standard-B USB receptacle, via a USB cable. This event starts the USB enumeration procedure. In its initial phase, the host s USB port current supply capability is limited to 00 ma. It is enough because only ST-LINK/V- part of STML76G-EVAL draws power at that time. If the jumper header JP8 is open, the U7 ST890 power switch is set to OFF position, which isolates the remainder of STML76G-EVAL from the power source. In the next phase of the enumeration procedure, the host PC informs the ST-LINK/V- facility of its capability to supply up to 00 ma of current. If the answer is positive, the ST-LINK/V- sets the U7 ST890 switch to ON position to supply power to the remainder of the STML76G-EVAL board. If the PC USB port is not capable of supplying up to 00 ma of current, the CN power jack can be used to supply the board. Should a short-circuit occur on the board, the ST890 power switch protects the USB port of the host PC against a current demand exceeding 600 ma, In such an event, the LD9 LED lights on. The STML76G-EVAL board can also be supplied from a USB power source not supporting enumeration, such as a USB charger. In this particular case, the JP8 header must be fitted with a jumper as shown in Table. ST-LINK/V- turns the ST890 power switch ON regardless of enumeration procedure result and passes the power unconditionally to the board. The LD7 red LED turns on whenever the whole board is powered. DocID075 Rev 5 5/0 00

16 Hardware layout and configuration UM855.. Using ST-LINK/- along with powering through CN power jack It can happen that the board requires more than 00 ma of supply current. It cannot be supplied from host PC connected to ST-LINK/- USB port for debugging or flashing STML76ZGT6. In such a case, the board can be supplied through CN (marked PSU _E5V on the board). To do this, it is important to power the board before connecting it with the host PC, which requires the following sequence to be respected:. Set the jumper in JP5 header in PSU position. Connect the external 5 V power source to CN. Check the red LED LD7 is turned on. Connect host PC to USB connector CN7 In case the board demands more than 00 ma and the host PC is connected via USB before the board is powered from CN, there is a risk of the following events to occur, in the order of severity:. The host PC is capable of supplying 00 ma (the enumeration succeeds) but it does not incorporate any over-current protection on its USB port. It is damaged due to overcurrent.. The host PC is capable of supplying 00 ma (the enumeration succeeds) and it has a built-in over-current protection on its USB port, limiting or shutting down the power out of its USB port when the excessive current demand from STML76G-EVAL is detected. This causes an operating failure to STML76G-EVAL.. The host PC is not capable of supplying 00 ma (the enumeration fails) so ST-LINK/V- does not supply the remainder of STML76G-EVAL from its USB port VBUS line. Figure 5. CN power jack polarity 6/0 DocID075 Rev 5

17 UM855 Hardware layout and configuration Table. Power-supply-related jumper settings Jumper array Jumper setting Configuration JP7 STML76G-EVAL is supplied through CN power jack (marked PSU_E5V). CN6 extension connector does not pass the 5 V of STML76G-EVAL to daughterboard. JP7 STML76G-EVAL is supplied through CN Micro-AB USB connector. CN6 extension connector does not pass the 5 V of STML76G-EVAL to daughterboard. JP7 Power source selector JP7 Default setting. STML76G-EVAL is supplied through CN7 Standard-B USB connector. CN6 extension connector does not pass the 5 V of STML76G-EVAL to daughterboard. Check JP8 setting in Table. JP7 STML76G-EVAL is supplied through pin 8 of CN6 extension connector. JP7 STML76G-EVAL is supplied through CN power jack (marked PSU_E5V). CN6 extension connector passes the 5 V of STML76G-EVAL to daughterboard. Make sure to disconnect from the daughterboard any power supply that could generate conflict with the power supply on CN power jack. JP V bat connection JP JP V bat is connected to battery. Default setting. V bat is connected to V DD. DocID075 Rev 5 7/0 00

18 Hardware layout and configuration UM855 Table. Power-supply-related jumper settings (continued) Jumper array Jumper setting Configuration JP _MCU connection JP JP Default setting. _MCU ( terminals of STML76ZGT6) is connected to fixed +. V. _MCU is connected to voltage in the range from +.7 V to +.6 V, adjustable with potentiometer RV. JP0 A connection JP0 JP0 Default setting. A terminal of STML76ZGT6 is connected with _MCU. A terminal of STML76ZGT6 is connected to +. V. JP _USB connection JP JP Default setting. _USB (USB terminal of STML76ZGT6) is connected with _MCU. _USB is connected to +.V. JP _IO connection JP JP Default setting. _IO (IO terminals of STML76ZGT6) is connected with _MCU _IO is open. JP8 Powering through USB of ST-LINK/V- JP8 JP8 Default setting. Standard-B USB connector CN7 of ST-LINK/V- can supply power to the STML76G-EVAL board remainder, depending on host PC USB port s powering capability declared in the enumeration. Standard-B USB connector CN7 of ST-LINK/V- supplies power to the STML76G-EVAL board remainder. Setting for powering the board through CN7 using USB charger. 8/0 DocID075 Rev 5

19 UM855 Hardware layout and configuration. Clock references Two clock references are available on STML76G-EVAL for the STML76ZGT6 target microcontroller:.768 khz crystal X, for embedded RTC 8 MHz crystal X, for main clock generator The main clock can also be generated using an internal RC oscillator. The X crystal is in a socket. It can be removed when the internal RC oscillator is used. Table. X-crystal-related solder bridge settings Solder bridge SB SB Setting Open Closed Open Closed Description Default setting. PC-OSC_IN terminal is not routed to extension connector CN7. X is used as clock reference. PC-OSC_IN is routed to extension connector CN7. R87 must be removed, for X quartz circuit not to disturb clock reference or source on daughterboard. Default setting. PC5-OSC_OUT terminal is not routed to extension connector CN7. X is used as clock reference. PC5-OSC_OUT is routed to extension connector CN7. R88 must be removed, for X quartz circuit not to disturb clock reference on daughterboard. Table. X-crystal-related solder bridge settings Solder bridge SB SB Setting Open Closed Open Closed Configuration Default setting. PH0-OSC_IN terminal is not routed to extension connector CN7. X is used as clock reference. PH0-OSC_IN is routed to extension connector CN7. X and C5 must be removed, in order not to disturb clock reference or source on daughterboard. Default setting. PH-OSC_OUT terminal is not routed to extension connector CN7. X is used as clock reference. PH-OSC_OUT is routed to extension connector CN7. R95 must be removed, in order not to disturb clock reference or source on daughterboard..5 Reset sources Reset signal of the STML76G-EVAL board is active low. DocID075 Rev 5 9/0 00

20 Hardware layout and configuration UM855 Sources of reset are: reset button B JTAG/SWD connector CN5 and ETM trace connector CN (reset from debug tools) through extension connector CN7, pin (reset from daughterboard) ST-LINK/V- RS- connector CN9, terminal 8 (CTS signal), if JP9 is closed (open by default).6 Boot.6. Boot options After reset, the STML76ZGT6 MCU can boot from the following embedded memory locations: main (user, non-protected) Flash memory system (protected) Flash memory RAM, for debugging The microcontroller is configured to one of the listed boot options by setting the STML76ZGT6 port BOOT0 level by the switch SW and by setting nboot bit of FLASH_OPTR option bytes register, as shown in Table 5. Depending on JP8, BOOT0 level can be forced high and, SW action overruled, by DSR line of RS- connector CN9, as shown in Table 6. This can be used to force the execution of bootloader and start user Flash memory flashing process (ISP) from RS- interface. The option bytes of STML76ZGT6 and their modification procedure are described in the reference manual RM05. The application note AN606 details the bootloader mechanism and configurations. Table 5. Boot selection switch Switch Setting Description SW Default setting. BOOT0 line is tied low. STML76ZGT6 boots from user Flash memory. BOOT0 line is tied high. STML76ZGT6 boots from system Flash memory (nboot bit of FLASH_OPTR register is set high) or from RAM (nboot is set low). Table 6. Bootloader-related jumper setting Jumper Setting Description JP8 JP8 JP8 Default setting. BOOT0 level only depends on SW switch position BOOT0 can be forced high with terminal 6 of CN9 connector (RS- DSR line). This configuration is used to allow the device connected via RS- to initiate STML76ZGT6 flashing process. 0/0 DocID075 Rev 5

21 UM855 Hardware layout and configuration.6. Bootloader limitations Boot from system Flash memory results in executing bootloader code stored in the system Flash memory protected against write and erase. This allows in-system programming (ISP), that is, flashing the MCU user Flash memory. It also allows writing data into RAM. The data come in via one of the communication interfaces such as USART, SPI, I ² C bus, USB or CAN. Bootloader version can be identified by reading Bootloader ID at the address 0xFFF6FFE. The STML76ZGT6 part soldered on the STML76G-EVAL main board is marked with a date code corresponding to its date of manufacture. STML76ZGT6 parts with the date code prior or equal to week of 05 are fitted with bootloader V 9.0 affected by the limitations to be worked around, as described hereunder. Parts with the date code starting week of 05 contain bootloader V9. in which the limitations no longer exist. To locate the visual date code information on the STML76ZGT6 package, refer to its datasheet (DS098) available on section Package Information. Date code related portion of the package marking takes Y WW format, where Y is the last digit of the year and WW is the week. For example, a part manufactured in week of 05 bares the date code 5. Bootloader ID of the bootloader V 9.0 is 0x90. The following limitations exist in the bootloader V 9.0:. RAM data get corrupted when written via USART/SPI/IC/USB interface Description: Data write operation into RAM space via USART, SPI, I ² C bus or USB results in wrong or no data written. Workaround: To correct the issue of wrong write into RAM, download STSW-STM58 bootloader V 9.0 patch package from and load "Bootloader V9.0 SRAM patch" to the MCU, following the information in readme.txt file available in the package.. User Flash memory data get corrupted when written via CAN interface Description: Data write operation into user Flash memory space via CAN interface results in wrong or no data written. Workaround: To correct the issue of wrong write into Flash memory, download STSW-STM58 bootloader V 0.9 patch package from and load "Bootloader V9.0 CAN patch" to the MCU, following the information in readme.txt file available in the package..7 Audio A codec connected to SAI interface of STML76ZGT6 supports TDM feature of the SAI port. TDM feature offers to STML76ZGT6 the capability to stream two independent stereo audio channels to two separate stereo analog audio outputs, simultaneously. There are two digital microphones on board of STML76G-EVAL. DocID075 Rev 5 /0 00

22 Hardware layout and configuration UM Digital microphones U5 and U6 on board of STML76G-EVAL are MPDT0TR MEMS digital omnidirectional microphones providing PDM (pulse density modulation) outputs. To share the same data line, their outputs are interlaced. The combined data output of the microphones is directly routed to STML76ZGT6 terminals, thanks to the integrated input digital filters. The microphones are supplied with programmable clock generated directly by STML76ZGT6. As an option, the microphones can be connected to U9, Wolfson audio codec device, WM899. In that configuration, U9 also supplies the PDM clock to the microphones. Regardless of where the microphones are routed to, STML76ZGT6 or WM899, they can be power-supplied from either or MICBIAS output of the WM899 codec device. Table 7 shows settings of all jumpers associated with the digital microphones on the board. Table 7. Digital microphone-related jumper settings Jumper Setting Configuration JP JP JP Default setting. PDM clock for digital microphones comes from STML76ZGT6 PDM clock for digital microphones comes from WM899 codec. JP6 JP6 JP6 Default setting. Power supply of digital microphones is. Power supply of digital microphones is generated by WM899 codec..7. Headphones outputs The STML76G-EVAL evaluation board can drive two sets of stereo headphones. Identical or different stereo audio content can be played back in each set of headphones. The STML76ZGT6 sends up to two independent stereo audio channels, via its SAI TDM port, to the WM899 codec device. The codec device converts the digital audio stream to stereo analog signals. It then boosts them for direct drive of headphones connecting to.5 mm stereo jack receptacles on the board, CN0 for Audio-output and CN for Audio_output. Figure 6 shows a top view of the CN0 and CN headphones jack receptacles. The CN jack takes its signal from the output of the WM899 codec device intended for driving an amplifier for loudspeakers. A hardware adaptation is incorporated on the board to make it compatible with a direct headphone drive. The adaptation consists of coupling capacitors blocking the DC component of the signal, attenuator and anti-pop resistors. The loudspeaker output of the WM899 codec device must be configured by software in linear mode called class AB and not in switching mode called class D. The I ² C-bus address of WM899 is 0b0000. /0 DocID075 Rev 5

23 UM855 Hardware layout and configuration Figure 6. CN0, CN top view.7. Limitations in using audio features Due to the share of some terminals of STML76ZGT6 by multiple peripherals, the following limitations apply in using the audio features: If the SAI_SDA is used as part of SAI port, it cannot be used as FMC_NWAIT signal for NOR Flash memory device. However, FMC_NWAIT is not necessary for operating the NOR Flash memory device. More details on FMC_NWAIT are available in Section.: NOR Flash memory device. If the SAI port of STML76ZGT6 is used for streaming audio to the WM899 codec IC, STML76ZGT6 cannot control the motor. If the digital microphones are attached to STML76ZGT6, the LCD glass module cannot be driven..8 USB OTG FS port The STML76G-EVAL board supports USB OTG full-speed (FS) communication. The USB OTG connector CN is of Micro-AB type..8. STML76G-EVAL used as USB device When a USB host connection to the CN Micro-AB USB connector of STML76G-EVAL is detected, the STML76G-EVAL board starts behaving as USB device. Depending on the powering capability of the USB host, the board can take power from VBUS terminal of CN. In the board schematic diagrams, the corresponding power voltage line is called U5V. Section. provides information on how to set associated jumpers for this powering option. The JP9 jumper must be left open to prevent STML76G-EVAL from sourcing 5 V to VBUS terminal, which would cause conflict with the 5 V sourced by the USB host. This may DocID075 Rev 5 /0 00

24 Hardware layout and configuration UM855 happen if the PC6 GPIO is controlled by the software of the STML76ZGT6 such that, it enables the output of U power switch..8. STML76G-EVAL used as USB host When a USB device connection to the CN Micro-AB USB connector is detected, the STML76G-EVAL board starts behaving as USB host. It sources 5 V on the VBUS terminal of CN Micro-AB USB connector to power the USB device. For this to happen, the STML76ZGT6 MCU sets the U power switch STMPS5STR to ON state. The LD5 green LED marked VBUS indicates that the peripheral is supplied from the board. The LD6 red LED marked FAULT lights up if over-current is detected. The JP9 jumper must be closed to allow the PC6 GPIO to control the U power switch. In any other STML76G-EVAL powering option, the JP9 jumper should be open, to avoid accidental damage caused to an external USB host..8. Configuration elements related with USB OTG FS port The following STML76ZGT6 terminals related with USB OTG FS port control are shared by other resources of the STML76G-EVAL board: PB, used as USB over-current input (USBOTG_OVRCR signal); it is shared with SWP, touch sensing, LCD glass module and motor control resources PB, used as USB power ready input (USBOTG_PRDY signal); it is shared with NFC, touch sensing and LCD glass module resources PC6, used as USB power switch control (USBOTG_PPWR signal); it is shared with touch sensing, LCD glass module and motor control Configuration elements related with the USB OTG FS port, such as jumpers, solder bridges and zero-ohm resistors, shunt the shared ports toward different resources or determine the operating mode of the USB OTG FS port. By default, they are set such as to enable the USB OTG FS port operation where STML76G-EVAL plays USB device role and can be connected to a USB host. Table 8 gives an overview of all configuration elements related with the USB OTG FS port. The LCD glass module daughterboard should be connected in I/O position. USBOTG_OVRCR and USBOTG_PRDY signals, requiring the PB and PB ports of STML76ZGT6, are only exploited when STML76G-EVAL acts as USB host. That is why, the USB host function of STML76G-EVAL is exclusive with alternate functions also requiring PB and PB ports of STML76ZGT6 - NFC, touch sensing, motor control, SWP. The PB and PB ports of STML76ZGT6 are not required for the USB OTG FS port operating as USB device. Table 8. Configuration elements related with USB OTG FS port Element Setting Description JP9 Open Closed USB OTG FS port can be connected with a USB host and get power from it. If connected with USB device, STML76G-EVAL cannot supply power to it. Default setting. USB OTG FS port can be connected with a USB device and supply power to it. It must not be connected with USB host. /0 DocID075 Rev 5

25 UM855 Hardware layout and configuration Table 8. Configuration elements related with USB OTG FS port (continued) Element Setting Description R6 R9 R8 In Out In Out In Out Default setting PC6 is shunted to control the U power switch, transiting through the LCD glass module daughterboard connector. LCD glass module daughterboard should be in I/O position, with SB and SB7 open. PC6 is disconnected from the LCD glass module daughterboard connector. It can be shunted to one of alternate resources, either touch sensing (SB closed) or motor control (SB7 closed). Default setting. PB receives USBOTG_OVRCR signal from U power switch, transiting through the LCD glass module daughterboard connector. SB should be open, R09 in, no smartcard in CN slot. PB is disconnected from the LCD glass module daughterboard connector. It can be shunted to one of alternate resources, either touch sensing or motor control (SB closed). Default setting. PB receives USBOTG_PRDY signal from CN connector, transiting through the LCD glass module daughterboard connector. SB6 should be open and no daughterboard inserted in CN NFC connector. PB s disconnected from the LCD glass module daughterboard connector. It can be shunted to touch sensing (SB6 closed)..8. Limitations in using USB OTG FS port The USB OTG FS port operation as USB host is exclusive with NFC, SWP, LCD glass module, touch sensing, motor control The USB OTG FS port operation as USB device is exclusive with LCD glass module, touch sensing, motor control.8.5 Operating voltage The USB-related operating supply voltage of STML76ZGT6 (_USB line) must be within the range from.0 V to.6 V..9 RS- and IrDA ports The STML76G-EVAL board offers one RS- communication port and one IrDA port. If the STML76G-EVAL board version is greater than or equal to MB C-0, the IrDA transceiver (TFDU600) is not populated, but it is possible to solder manually the TDFU600 on U footprint to support IRDA feature. DocID075 Rev 5 5/0 00

26 Hardware layout and configuration UM RS- port.9. IrDA port The RS- communication port uses the DE-9M 9-pole connector CN9. RX, TX, RTS and CTS signals of USART port of STML76ZGT6 are routed to CN9. Bootloader_RESET_V and Bootloader_BOOT0_V signals can also be routed to CN9, for ISP (in-system programming) support. To route Bootloader_RESET_V to CN9, the R9 resistor must be removed and the JP9 jumper closed (open by default). To route Bootloader_BOOT0_V to CN9, the JP8 jumper must be closed. For configuration elements related with the RS- port operation, refer to Table 6 and Table 9. Section.0 brings information on using the LPUART port of STML76ZGT6 for RS-, instead of its USART port. The IrDA communication port uses an IrDA transceiver (U). Table 9 shows the configuration elements related with the IrDA port operation. Table 9. Settings of configuration elements for RS- and IrDA ports Element Setting Description 5 JP5 6 Default setting. RS- selected: PB7 port of STML76ZGT6 receives signal originating from RXD terminal of CN9. JP5 JP5 5 6 IrDA selected: PB7 port of STML76ZGT6 is connected with RxD terminal of the IrDA transceiver U. R9, R8, R6 5 JP5 In 6 NFC selected: PB7 port of STML76ZGT6 receives NFC_IRQOUT signal from NFC peripheral. Section.8 provides more detail on the NFC peripheral. Required for IrDA operation R58, R9 Out Required for IrDA operation.9. Limitations The operation of RS- and IrDA ports is mutually exclusive. The operation of either port is also mutually exclusive with the NFC peripheral operation..9. Operating voltage The RS-- and IrDA-related operating supply voltage of STML76ZGT6 ( line) must be within the range from.7 V to.6 V. 6/0 DocID075 Rev 5

27 UM855 Hardware layout and configuration.0 LPUART port On top of USART port for serial communication, the STML76ZGT6 offers LPUART, a low-power UART port. In the default configuration of STML76G-EVAL, the RX and TX terminals of the LPUART port are routed to the USB virtual COM port of ST-LINK/V- and, the RX and TX terminals of USART port to the RS- connector CN9. For specific purposes, the TX and RX of the LPUART port of STML76ZGT6 can be routed to the RS- connector CN9 instead. As RTS and CTS terminals of CN9 keep routed to USART port, they may block the LPUART communication flow. To avoid this, set the USART hardware flow control off. The default settings of LPUART are: 500b/s, 8bits, no parity, stop bit, no flow control. Table 0. Hardware settings for LPUART LPUART port use R88 R89 R58 R9 R8 JP5 - Default setting USB virtual COM port of ST-LINK/V- In In Out Out Do not care Do not care RS- (RX and TX) Out Out In In Out Closed. microsd card The CN8 slot for microsd card is routed to STML76ZGT6 s SDIO port, accepting SD (up to Gbytes), SDHC (up to Gbytes) and SDXC (up to Tbytes) cards. One -Gbyte microsd card is delivered as part of STML76G-EVAL. The card insertion switch is routed to the PA8 GPIO port. Table. Terminals of CN8 microsd slot Terminal Terminal name (MCU port) Terminal Terminal name (MCU port) SDIO_D (PC0) 6 Vss/ SDIO_D (PC) 7 SDIO_D0 (PC8) SDIO_CMD (PD) 8 SDIO_D (PC9) 9 5 SDIO_CLK (PC) 0 MicroSDcard_detect (PA8) For microsd card operation, the LCD glass module daughterboard must be plugged into CN and CN in I/O-bridge position, as explained in Section.5... Limitations Due to the share of SDIO port and PA8 terminals, the following limitations apply: The microsd card cannot be operated simultaneously with LCD glass module or with motor control. The microsd card insertion cannot be detected when the PA8 is used as microcontroller clock output (MCO), one of alternate functions of PA8. DocID075 Rev 5 7/0 00

28 Hardware layout and configuration UM855.. Operating voltage The supply voltage for STML76G-EVAL microsd card operation must be within the range from.7 V to.6 V.. Motor control The CN connector is designed to receive a motor control (MC) module. Table shows the assignment of CN and STML76ZGT6 terminals. Table also lists the modifications to be made on the board versus its by-default configuration. See Section.. for further details. Table. Motor control terminal and function assignment Motor control connector CN STML76ZGT6 microcontroller Terminal Terminal name Port name Function Alternate function Board modifications for enabling motor control Emergency Stop PC9 TIM8_BKIN - Close SB9 Remove MB979 daughterboard PWM_H PC6 TIM8_CH - Close SB7 Open SB Remove MB979 daughterboard PWM_L PA7 TIM8_CHN - Close SB9 Open SB8 Remove R PWM_H PC7 TIM8_CH - Close SB0 Open SB Remove R PWM_L PB0 TIM8_CHN - Close SB5 Open SB Remove R PWM_H PC8 TIM8_CH - Close SB8 Remove MB979 daughterboard PWM_L PB TIM8_CHN - Bus Voltage PC5 ADC_IN - Close SB Open SB Close SB6 Remove MB979 daughterboard 8/0 DocID075 Rev 5

29 UM855 Hardware layout and configuration Table. Motor control terminal and function assignment (continued) Motor control connector CN STML76ZGT6 microcontroller Terminal Terminal name Port name Function Alternate function Board modifications for enabling motor control PhaseA current+ PhaseA current- PhaseB current+ PhaseB current- PhaseC current+ PhaseC current- PC0 ADC_IN - Close SB Remove MB979 daughterboard PC ADC_IN - Close SB PC ADC_IN - Close SB Remove MB979 daughterboard ICL Shutout PG6 GPIO - Close SB5 Remove R Dissipative Brake PFC ind. curr. PB GPIO - PC ADC_IN - Close SB Remove R5 Close SB7 Remove MB979 daughterboard 5 +5V - +5V Heatsink Temp. PA ADC_IN - 7 PFC Sync PF9 TIM5_CH - Close SB Remove MB979 daughterboard Close SB5 Remove R V - +.V PFC PWM PF0 TIM5_CH - 0 PFC Shutdown PB TIM5_BKIN - Encoder A PA0 TIM_CH ADC_IN PFC Vac PA6 ADC_IN - Encoder B PA TIM_CH ADC_IN Encoder Index PA TIM_CH ADC_IN Close SB7 Remove R9 Close SB Remove MB979 daughterboard Close SB5 Remove R8 Close SB0 Open SB Remove MB979 daughterboard Close SB Remove MB979 daughterboard Close SB Remove MB979 daughterboard DocID075 Rev 5 9/0 00

30 Hardware layout and configuration UM855.. Board modifications to enable motor control Figure 7 (top side) and Figure 8 (bottom side) illustrate the board modifications listed in Table, required for the operation of motor control. Red color denotes a component to be remove. Green color denotes a component to be fitted. Figure 7. PCB top-side rework for motor control 0/0 DocID075 Rev 5

31 UM855 Hardware layout and configuration Figure 8. PCB underside rework for motor control.. Limitations Motor control operation is exclusive with LCD glass module, Quad-SPI Flash memory device, audio codec, potentiometer, LDR, smartcard, LED drive and the use of sigma-delta modulators.. CAN The STML76G-EVAL board supports one CAN.0A/B channel compliant with CAN specification. The CN5 9-pole male connector of DE-9M type is available as CAN interface. A. V CAN transceiver is fitted between the CN5 connector and the CAN controller port of STML76ZGT6. The JP jumper allows selecting one of high-speed, standby and slope control modes of the CAN transceiver. The JP6 jumper can fit a CAN termination resistor in. DocID075 Rev 5 /0 00

32 Hardware layout and configuration UM855 Table. CAN related jumpers Jumper Setting Configuration JP JP JP Default setting CAN transceiver operates in high-speed mode CAN transceiver is in standby mode JP6 No termination resistor on CAN physical link JP6 JP6 Default setting Termination resistor fitted on CAN physical link.. Limitations CAN operation is exclusive with LCD glass module operation... Operating voltage The supply voltage for STML76G-EVAL CAN operation must be within the range from.0 V to.6 V.. Extension connectors CN6 and CN7 The CN6 and CN7 headers complement the LCD glass module daughterboard connector, to give access to all GPIOs of the STML76ZGT6 microcontroller. In addition to GPIOs, the following signals and power supply lines are also routed on CN6 or CN7: +V DSV RESET# Clock terminals PC-OSC_IN, PC5-OSC_OUT, PH0-OSC_IN, PH-OSC_OUT Each header has two rows of 0 pins, with.7 mm pitch and.5 mm row spacing. For extension modules, SAMTEC RSM-0-0-L-D-xxx and SMS-0-x-x-D can be recommended as SMD and through-hole receptacles, respectively (x is a wild card)..5 LCD glass module daughterboard The MB979 daughterboard delivered in the STML76G-EVAL package bears a segmented LCD glass module. The daughterboard inserts into CN and CN extension headers of the main board, each having two rows of pins. The corresponding female /0 DocID075 Rev 5

33 UM855 Hardware layout and configuration connectors on the daughterboard have three rows of holes each. One raw is routed to segments of the LCD. The other two rows are interconnected and form a series of jumpers. The way of inserting the LCD glass module daughterboard into CN and CN headers determines two functions of LCD glass module daughterboard. In its display function, STML76ZGT6 terminals are routed to LCD segments. In its I/O-bridge function, they are not. Instead, they transit from one row of CN pins to the other and from one row of CN pins to the other, thanks to interconnections fitted by the LCD glass module daughterboard. Figure 9 shows how the LCD glass module daughterboard must be positioned for display function. This position is designated in the document as display position. Figure 0 shows how the LCD glass module daughterboard must be positioned for I/Obridge function. This position is designated in the document as I/O-bridge position. The arrow indicates the side of the CN and CN headers where the extra row of holes of each female counterpart on the LCD glass module daughterboard has to protrude. When the LCD glass module daughterboard is not plugged in, CN and CN give access to ports of the target microcontroller. Figure 6 shows the related schematic diagram. Table shows the default settings of board configuration elements linked with CN and CN extension connectors and LCD glass module daughterboard. Figure 9. LCD glass module daughterboard in display position DocID075 Rev 5 /0 00

34 Hardware layout and configuration UM855 Figure 0. LCD glass module daughterboard in I/O-bridge position Table. LCD-daughterboard-related configuration elements LCD segment Element Setting to enable LCD glass module Description SEG0 SEG SEG SEG SEG SEG5 SEG6 SEG0 R8 In PA routed to LCDSEG0 SB Open PA not routed to motor control R8 In PA routed to LCDSEG SB Open PA not routed to motor control R78 In PA routed to LCDSEG SB Open PA not routed to motor control R68 In PA6 routed to LCDSEG SB Open PA6 not routed to Quad-SPI Flash memory device SB0 Open PA6 not routed to motor control R66 In PA7 routed to LCDSEG SB8 Open PA7 not routed to Quad-SPI Flash memory device SB9 Open PA7 not routed to motor control R6 In PB0 routed to LCDSEG5 SB Open PB0 not routed to Quad-SPI Flash memory device SB5 Open PB0 not routed to motor control R56 In PB routed to LCDSEG6 SB Open PB not routed to Quad-SPI Flash memory device SB Open PB not routed to motor control R50 In PB0 routed to LCDSEG0 SB9 Open PB0 not routed to Quad-SPI Flash memory device /0 DocID075 Rev 5

35 UM855 Hardware layout and configuration Table. LCD-daughterboard-related configuration elements (continued) LCD segment Element Setting to enable LCD glass module Description SEG R8 In PB routed to LCDSEG SB8 Open PB not routed to Quad-SPI Flash memory device SEG R9 In PB routed to LCDSEG SB Open PB not routed to Quad-SPI Flash memory device SEG R8 In PB routed to LCDSEG SB6 Open PB not routed to Touch sensing SEG8 R97 In PC0 routed to LCDSEG8 SB Open PC0 not routed to motor control SEG9 R98 In PC routed to LCDSEG9 SB6 Open PC not routed to motor control SEG0 R99 In PC routed to LCDSEG0 SB Open PC not routed to motor control SEG R65 In PC routed to LCDSEG SB7 Open PC not routed to motor control SEG R6 In PC5 routed to LCDSEG SB6 Open PC5 not routed to motor control R6 In PC6 routed to LCDSEG SEG SB Open PC6 not routed to Touch sensing SB7 Open PC6 not routed to for motor control R In PC7 routed to LCDSEG5 SEG5 SB Open PC7 not routed to Touch sensing SB0 Open PC7 not routed to for motor control SEG6 SB8 Open PC8 not routed to motor control SEG7 SB9 Open PC9 not routed to motor control SEG8 R0 In PE routed to LCDSEG8 SB6 Open PE not routed to Trace SEG9 R0 In PE routed to LCDSEG9 The custom LCD glass module used on MB979 daughterboard is XHO500B. To optimize the number of driving signals, the display elements are connected to eight common planes called COMx (LCDCOMx in the schematic diagrams), where x can be substituted with figures from 0 to 7. The other pole of each display element is called segment, SEGy (LCDSEGy in the schematic diagrams), where y can be substituted with figures from 0 to 9. Each combination of COMx and SEGy addresses one display element. Table 5, Table 6, Table 7 and Table show the LCD element mapping. COMx are ordered in rows, SEGy in columns. The table cells then display the display element names DocID075 Rev 5 5/0 00

36 Hardware layout and configuration UM855 corresponding to each COMx and SEGy combination. Names in quoting marks denote elements forming textual symbols, for example µa or +. Figure shows the physical location and shape of each segment on the LCD glass module. Table 5. LCD glass element mapping - segments 0 to 9 SEG0 SEG SEG SEG SEG SEG5 SEG6 SEG7 SEG8 SEG9 COM0 O 5D Q O 6D Q5 ST 7D Q6 S5 COM O 5K 5L O 6K 6L na 7K 7L S6 COM b b b 6b 5b b 9b 8b 7b b COM a a a 6a 5a a 9a 8a 7a a COM 5I 5A 5G 6I 6A 6G 7I 7A 7G I COM5 5B 5H 5F 6B 6H 6F 7B 7H 7F B COM6 5C 5M P 6C 6M P5 7C 7M P6 C COM7 5J 5N 5E 6J 6N 6E 7J 7N 7E J Table 6. LCD glass element mapping - segments 0 to 9 SEG0 SEG SEG SEG SEG SEG5 SEG6 SEG7 SEG8 SEG9 COM0 D - C D Q C D Q µa D COM K L C K L C K L ma K COM S S b b b 7b 6b 5b 0b 9b COM S S a a a 7a 6a 5a 0a 9a COM A G I A G I A G I A COM5 H F B H F B H F B H COM6 M + C M P C M P C M COM7 N E J N E J N E J N Table 7. LCD glass element mapping - segments 0 to 9 SEG0 SEG SEG SEG SEG SEG5 SEG6 SEG7 SEG8 SEG9 COM0 Q e e e e 5e 6e 7e 8e 9e COM L f f f f 5f 6f 7f 8f 9f COM 8b c c c c 5c 6c 7c 8c 9c COM 8a d d d d 5d 6d 7d 8d 9d COM G j j j j 5j 6j 7j 8j 9j COM5 F i i i i 5i 6i 7i 8i 9i COM6 P h h h h 5h 6h 7h 8h 9h COM7 E g g g g 5g 6g 7g 8g 9g 6/0 DocID075 Rev 5

37 UM855 Hardware layout and configuration Table 8. LCD glass element mapping - segments 0 to 9 SEG0 SEG SEG SEG SEG SEG5 SEG6 SEG7 SEG8 SEG9 COM0 0e e e e e 5e 6e 7e 8e 9e COM 0f f f f f 5f 6f 7f 8f 9f COM 0c c c c c 5c 6c 7c 8c 9c COM 0d d d d d 5d 6d 7d 8d 9d COM 0j j j j j 5j 6j 7j 8j 9j COM5 0i i i i i 5i 6i 7i 8i 9i COM6 0h h h h h 5h 6h 7h 8h 9h COM7 0g g g g g 5g 6g 7g 8g 9g.5. Limitations LCD glass module operation is exclusive with all other features of the board. DocID075 Rev 5 7/0 00

38 8/0 DocID075 Rev 5 Figure. LCD glass display element mapping Hardware layout and configuration UM855

39 UM855 Hardware layout and configuration.6 TFT LCD panel STML76G-EVAL is delivered with MB989P, a daughterboard plugged into the CN9 extension connector. It bears a TFT.8-inch color LCD panel with resistive touchscreen and an on-board controller. Section.8 provides further information. Thanks to level shifters on all signal lines, the TFT LCD panel can operate with the entire operating voltage range of STML76G-EVAL. The TFT LCD panel is attached to the 6-bit data bus and accessed with FMC. The base address is 0x , corresponding to NOR/SRAM bank. The panel is selected with LCD_NE chip select signal generated by PG0 port of the STML76ZGT6. Address lines A0 and A determine the panel resources addressed, as depicted in Table 9. Table 0 gives the CN9 extension connector terminal assignment. Table 9. Access to TFT LCD resources with FMC address lines A0 and A Address A A0 Usage 0x6800_ Read register 0x6800_000 0 Read Graphic RAM (GRAM) 0x6800_000 0 Write register 0x6800_0006 Write graphic RAM (GRAM) Table 0. Assignment of CN9 connector terminals of TFT LCD panel CN9 terminal Terminal name MCU port CN9 terminal Terminal name MCU port CSN PG0 RS PF0 WRN PD5 RDN PD 5 RSTN RESET# 6 D0 PD 7 D PD5 8 D PD0 9 D PD 0 D PE7 D5 PE8 D6 PE9 D7 PE0 D8 PE 5 D9 PE 6 D0 PE 7 D PE 8 D PE5 9 D PD8 0 D PD9 D5 PD0 BL_ - BL_CONTROL - +V - 5 +V BL_ - 9 SDO - 0 SDI - XL I/O expander_x- XR I/O expander_x+ YD I/O expander_y- YU I/O expander_y+ DocID075 Rev 5 9/0 00

40 Hardware layout and configuration UM855.7 User LEDs Four general-purpose color LEDs (LD, LD, LD, LD) are available as light indicators. Each LED is in light-emitting state with low level of the corresponding control port. They are controlled either by the STML76ZGT6 or by the I/O expander IC U, named IOExpander in the schematic diagram. Table gives the assignment of control ports to the LED indicators. Table. Port assignment for control of LED indicators User LED Control port Control device LED (Green) PB STML76ZGT6 LED (Orange) GPIO0 IOExpander LED (Red) PC STML76ZGT6 LED (Blue) GPIO IOExpander.8 Physical input devices The STML76G-EVAL board provides a number of input devices for physical human control. These are: four-way joystick controller with select key (B) wake-up/ tamper button (B) reset button (B) resistive touchscreen of the TFT LCD panel 0 kω potentiometer (RV) light-dependent resistor, LDR (R5) Table shows the assignment of ports routed to the physical input devices. They are either ports of the STML76ZGT6 or of one of the two I/O expander ICs on the board, named, in the schematic diagrams, IOExpander and IOExpander. Table. Port assignment for control of physical input devices Input device Control port Control device Joystick SEL GPIO0 IOExpander Joystick DOWN GPIO IOExpander Joystick LEFT GPIO IOExpander Joystick RIGHT GPIO IOExpander Joystick UP GPIO IOExpander Wake-up/ tamper B PC STML76ZGT6 Reset B NRST STML76ZGT6 Resistive touch screen X+ X+ IOExpander Resistive touch screen X- X- IOExpander Resistive touch screen Y+ Y+ IOExpander 0/0 DocID075 Rev 5

41 UM855 Hardware layout and configuration Table. Port assignment for control of physical input devices (continued) Input device Control port Control device Resistive touch screen Y- Y- IOExpander Potentiometer PB or PA0 STML76ZGT6 LDR PA0 or PB STML76ZGT6 The potentiometer and the light-dependent resistor can be routed, mutually exclusively, to either PB or to PA0 port of STML76ZGT6. Table depicts the setting of associated configuration jumpers. As illustrated in the schematic diagram in Figure 6, the PB port is routed, in the STML76ZGT6, to the non-inverting input of comparator Comp. The PA0 is routed to non-inverting input of operational amplifier OpAmp. However, depending on register settings, it can also be routed to ADC or to ADC. Table. Setting of jumpers related with potentiometer and LDR Jumper Setting Routing JP5 JP7 JP5 JP7 Potentiometer is routed to pin PB of STML76ZGT6. JP5 JP7 JP5 JP7 Default setting. Potentiometer is routed to pin PA0 of STML76ZGT6. JP5 JP7 JP5 JP7 LDR is routed to pin PB of STML76ZGT6. JP5 JP7 JP5 JP7 LDR is routed to pin PA0 of STML76ZGT6..8. Limitations The potentiometer and the light-dependent resistor are mutually exclusive..9 Operational amplifier and comparator.9. Operational amplifier STML76ZGT6 provides two on-board operational amplifiers, one of which, OpAmp, is made accessible on STML76G-EVAL. OpAmp has its inputs and its output routed to I/O ports PA0, PA and PA, respectively. The non-inverting input PA0 is accessible on the terminal of the JP7 jumper header. On top of the possibility of routing either of the DocID075 Rev 5 /0 00

42 Hardware layout and configuration UM855 potentiometer or LDR to PA0, en external source can also be connected to it, using the terminal of JP7. The PA output of the operational amplifier can be accessed on test point TP9. Refer to the schematic diagram in Figure 6. The gain of OpAmp is determined by the ratio of the variable resistor RV and the resistor R, as shown in the following equation: With the RV ranging from 0 to 0 kω and R being kω, the gain can vary from to. The R6 resistor in series with PA0 is beneficial for reducing the output offset..9. Comparator Gain = + ( RV) ( R) STML76ZGT6 provides two on-board comparators, one of which, Comp, is made accessible on STML76G-EVAL. Comp has its non-inverting input and its output routed to I/O ports PB and PB5, respectively. The input is accessible on the terminal of the JP7 jumper header. On top of the possibility of routing either the potentiometer or LDR to PB, an external source can also be connected to it, using the terminal of JP7. The PB5 output of the comparator can be accessed on test point TP6. Refer to the schematic diagram in Figure 6..0 Analog input, output, VREF STML76ZGT6 provides on-board analog-to-digital converter, ADC and, digital-to-analog converter, DAC. The port PA can be configured to operate either as ADC input or as DAC output. PA is routed to the two-way header CN8 allowing to fetch signals to or from PA or to ground it by fitting a jumper into CN8. Parameters of the ADC input low-pass filter formed with R7 and C7 can be modified by replacing these components according to application requirements. Similarly, parameters of the DAC output low-pass filter formed with R7 and C7 can be modified by replacing these components according to application requirements. The VREF+ terminal of STML76ZGT6 is used as reference voltage for both ADC and DAC. By default, it is routed to A through a jumper fitted into the two-way header CN0. The jumper can be removed and an external voltage applied to the terminal of CN0, for specific purposes.. SRAM device IS6WV06BLL, a 6-Mbit static RAM (SRAM), M x6 bit, is fitted on the STML76G-EVAL main board, in U position. The STML76G-EVAL main board as well as the addressing capabilities of FMC allow hosting SRAM devices up to 6 Mbytes. This is the reason why the schematic diagram in Figure mentions several SRAM devices. The SRAM device is attached to the 6-bit data bus and accessed with FMC. The base address is 0x , corresponding to NOR/SRAM bank. The SRAM device is /0 DocID075 Rev 5

43 UM855 Hardware layout and configuration selected with FMC_NE chip select. FMC_NBL0 and FMC_NBL signals allow selecting 8- bit and 6-bit data word operating modes. By removal of R8, a zero-ohm resistor, the SRAM is deselected and the STML76ZGT6 ports PD7, PE0 and PE corresponding to FMC_NE, FMC_NBL0 and FMC_NBL signals, respectively, can be used for other application purposes. Table. SRAM chip select configuration Resistor Fitting Configuration R8 In Out Default setting. SRAM chip select is controlled with FMC_NE SRAM is deselected. FMC_NE is freed for other application purposes... Limitations The SRAM addressable space is limited if some or all of A9, A0, A, A and A FMC address lines are shunted to the CN connector for debug trace purposes. In such a case, the disconnected addressing inputs of the SRAM device are pulled down by resistors. Section. provides information on the associated configuration elements... Operating voltage The SRAM device operating voltage is in the range from. V to.6 V.. NOR Flash memory device M9W8GL70ZA6E, a 8-Mbit NOR Flash memory, 8 M x6 bit, is fitted on the STML76G-EVAL main board, in U5 position. The STML76G-EVAL main board as well as the addressing capabilities of FMC allow hosting M9W56GL70ZA6E, a 56-Mbit NOR Flash memory device. This is the reason why the schematic diagram in Figure mentions both devices. The NOR Flash memory device is attached to the 6-bit data bus and accessed with FMC. The base address is 0x , corresponding to NOR/SRAM bank. The NOR Flash memory device is selected with FMC_NE chip select signal. 6-bit data word operation mode is selected by a pull-up resistor connected to BYTE terminal of NOR Flash memory. The jumper JP is dedicated for write protect configuration. By default, the FMC_NWAIT signal is not routed to RB port of the NOR Flash memory device, and, to know its ready status, its status register is polled by the demo software fitted in STML76G-EVAL. This can be modified with configuration elements, as shown in Table 5. DocID075 Rev 5 /0 00

44 Hardware layout and configuration UM855 Table 5. NOR Flash memory-related configuration elements Element Setting Configuration JP JP JP Default setting. NOR Flash memory write is enabled. NOR Flash memory write is inhibited. Write protect is activated. R5 SB0 R5 In SB0 open R5 Out SB0 closed Default setting. PD6 port of STML76ZGT6 is used for SAI_SDA signal and routed to audio codec. NOR Flash memory device s status register can be accessed. PD6 port of STML76ZGT6 is used for FMC_NWAIT signal and routed to NOR Flash memory device s RB port. NOR Flash memory device s status register cannot be accessed... Limitations FMC_NWAIT and SAI_SDA signals are mutually exclusive. The NOR Flash memory device s addressable space is limited if some or all of A9, A0, A, A and A FMC address lines are shunted to the CN connector for debug trace purposes. In such a case, the disconnected addressing inputs of the NOR Flash memory device are pulled down by resistors. Section. provides information on the associated configuration elements... Operating voltage NOR Flash memory operating voltage must be in the range from.65 V to.6 V.. EEPROM M8-DFDW6TP, a 8-Kbit I ² C-bus EEPROM device, is fitted on the main board of STML76G-EVAL, in U6 position. It is accessed with I ² C-bus lines IC_SCL and IC_SDA of STML76ZGT6. It supports all I ² C-bus modes with speeds up to MHz. The base I ² C-bus address is 0xA0. Write-protecting the EEPROM is possible through opening the SB7 solder bridge. By default, SB7 is closed and writing into the EEPROM enabled... Operating voltage The M8-DFDW6TP EEPROM device s operating voltage must be in the range from.7 V to.6 V. RF-EEPROM RF-EEPROM daughterboard, ANT7-MLR-A, can be connected to CN connector of the STML76G-EVAL board. STML76ZGT6 can access the RF-EEPROM in two ways, /0 DocID075 Rev 5

45 UM855 Hardware layout and configuration wired through I ² C bus or wireless using.56 MHz RF band reserved for RFID and NFC equipment. For wireless access, CR95HF reader daughterboard plugged in the CN connector can be used, for example. I ² C address of RF-EEPROM device is 0xA6..5 Quad-SPI Flash memory device N5Q56AEF80E, a 56-Mbit Quad-SPI Flash memory device, is fitted on the STML76G-EVAL main board, in U9 position. It allows evaluating STML76ZGT6 Quad-SPI Flash memory device interface. N5Q56AEF80E can operate in single transfer rate (STR) and double transfer rate (DTR) modes. By default, the Quad-SPI Flash memory device is not accessible. Table 6 shows the configuration elements and their settings allowing to access the Quad-SPI Flash memory device. The LCD glass module daughterboard MB979 takes active part in the configuration. It must be removed from the main board (denoted as MB979 out ), to operate the Quad- SPI Flash memory device. Section.: Motor control provides additional information. Table 6. Configuration elements related with Quad-SPI device Element Setting Configuration SB SB MB979 SB SB5 MB979 SB8 SB9 MB979 SB open SB open SB closed SB open MB979 out SB open SB5 open SB closed SB5 open MB979 out SB8 open SB9 open SB8 closed SB9 open MB979 out Default setting. QSPI_D0 data line is not available at Quad-SPI Flash memory device: PB port of STML76ZGT6 is only routed to CN connector for the MB979 daughterboard. QSPI_D0 data line is available at Quad-SPI Flash memory device: PB port of STML76ZGT6 is routed to DQ0 port of Quad-SPI Flash memory device. Default setting. QSPI_D data line is not available at Quad-SPI Flash memory device: PB0 port of STML76ZGT6 is only routed to CN connector for the MB979 daughterboard. QSPI_D data line is available at Quad-SPI Flash memory device: PB0 port of STML76ZGT6 is routed to DQ port of Quad-SPI Flash memory device. Default setting. QSPI_D data line is not available at Quad-SPI Flash memory device: PA7 port of STML76ZGT6 is only routed to CN connector for the MB979 daughterboard. QSPI_D data line is available at Quad-SPI Flash memory device: PA7 port of STML76ZGT6 is routed to DQ port of Quad-SPI Flash memory device. DocID075 Rev 5 5/0 00

46 Hardware layout and configuration UM855 Table 6. Configuration elements related with Quad-SPI device (continued) Element Setting Configuration SB SB0 MB979 SB9 MB979 SB8 MB979 SB open SB0 open SB closed SB0 open MB979 out SB9 open SB9 closed MB979 out SB8 open SB8 closed MB979 out Default setting. QSPI_D data line is not available at Quad-SPI Flash memory device: PA6 port of STML76ZGT6 is only routed to CN connector for the MB979 daughterboard. QSPI_D data line is available at Quad-SPI Flash memory device: PA6 port of STML76ZGT6 is routed to DQ port of Quad-SPI Flash memory device. Default setting. QSPI_CLK clock line is not available at Quad-SPI Flash memory device: PB0 port of STML76ZGT6 is only routed to CN connector for the MB979 daughterboard. QSPI_CLK clock line is available at Quad-SPI Flash memory device: PB0 port of STML76ZGT6 is routed to C port of Quad-SPI Flash memory device. Default setting. QSPI_CS line is not available at Quad-SPI Flash memory device: PB port of STML76ZGT6 is only routed to CN connector for the MB979 daughterboard. QSPI_CS line is available at Quad-SPI Flash memory device: PB port of STML76ZGT6 is routed to S# port of Quad-SPI Flash memory device..5. Limitations Quad-SPI operation is exclusive with LCD glass module and with motor control..5. Operating voltage Voltage of Quad-SPI Flash memory device N5Q56AEF80E is in the range of.7 V to.6 V..6 Touch-sensing button The STML76G-EVAL evaluation board supports a touch sensing button based on either RC charging or on charge-transfer technique. The latter is enabled, by default. The touch sensing button is connected to PB port of STML76ZGT6 and the related charge capacitor is connected to PB. An active shield is designed in the layer two of the main PCB, under the button footprint. It allows reducing disturbances from other circuits to prevent from false touch detections. The active shield is connected to PC6 port of STML76ZGT6 through the resistor R7.The related charge capacitor is connected to PC7. Table 7 shows the configuration elements related with the touch sensing function. Some of them serve to enable or disable its operation. However, most of them serve to optimize the touch sensing performance, by isolating copper tracks to avoid disturbances due to their antenna effect. 6/0 DocID075 Rev 5

47 UM855 Hardware layout and configuration Table 7. Touch-sensing-related configuration elements Element Setting Configuration R9 SB R8 SB6 R6 SB SB7 R SB In Out Open Closed In Out Open Closed In Out Open Closed Open Closed In Out Open Closed Default setting. PB port is routed to CN connector for LCD glass module daughterboard. This setting is not good for robustness of touch sensing. PB port is cut from CN. This setting is good for robustness of touch sensing. Default setting. PB is not routed to motor control. This setting is good for robustness of touch sensing. PB is routed to motor control. This setting is not good for robustness of touch sensing. Default setting. PB port is routed to CN connector for LCD glass module daughterboard. This setting is not good for robustness of touch sensing. PB port is cut from CN. This setting is good for robustness of touch sensing. Default setting. PB is not routed to sampling capacitor. Touch sensing cannot operate. PB is routed to sampling capacitor. Touch sensing can operate. Default setting. PC6 port is routed to CN connector for LCD glass module daughterboard. This setting is not good for robustness of touch sensing. PC6 port is cut from CN. This setting is good for robustness of touch sensing. Default setting. PC6 is not routed to active shield under the touchsensing button. This setting is not good for robustness of touch sensing. PC6 is routed to active shield under the touch-sensing button. This setting is good for robustness of touch sensing. Default setting. PC6 port of STML76ZGT6 is not routed to motor control. This setting is good for robustness of touch sensing. PC6 is routed to motor control. This setting is not good for robustness of touch sensing. Default setting. PC7 port is routed to CN connector for LCD glass module daughterboard. This setting is not good for robustness of touch sensing. PC7 port is cut from CN. This setting is good for robustness of touch sensing. Default setting. PC7 port of STML76ZGT6 is not routed to sampling capacitor of the active shield under the touch-sensing button. This setting is not good for robustness of touch sensing. PC7 is routed to sampling capacitor of the active shield under the touch-sensing button. This setting is good for robustness of touch sensing. DocID075 Rev 5 7/0 00

48 Hardware layout and configuration UM855 Table 7. Touch-sensing-related configuration elements (continued) Element Setting Configuration SB0 Open Closed Default setting. PC7 port of STML76ZGT6 is not routed to motor control. This setting is good for robustness of touch sensing. PC7 is routed to motor control. This setting is not good for robustness of touch sensing..6. Limitations Touch sensing button is exclusive with LCD glass module, thermal sensor PT00 via sigmadelta conversion, USB OTG FS port operating as USB host, SWP and NFC..7 Smartcard, SWP ST80CDR, an interface device for V and 5 V asynchronous smartcards, is fitted on the STML76G-EVAL main board, in U0 position. ST80CDR performs all supply protection and control functions of the smartcard. ST80CDR is controlled, on its turn, by STML76ZGT6, directly through its ports or indirectly through ports of the U I/O expander device (IOExpander), as shown in Table 8. The SWIO port of the smartcard for single-wire protocol (SWP) communication is managed directly by PB port of STML76ZGT6. Table 8. Assignment of ports for ST80CDR control ST80CDR port Function Control port 5V/V Smartcard power supply selection pin. IOexpander GPIO7 I/OUC Data I/O line STML76ZGT6 PC XTAL Quartz crystal or external clock input STML76ZGT6 PB0 OFF Card presence detect IOexpander GPIO8 RSTIN Card reset command input IOexpander GPIO5 CMDVCC Activation sequence start command input (active low) IOexpander GPIO6 Table 9 provides information on configuration elements related with smartcard operation. Refer to Table 8, Table, Table 6 and Table 7 for complementary information. Bridging of CN and CN rows of I/Os can be done by means of the MB979 daughterboard plugged into CN and CN in I/O-bridge position, as explained in Section.5. 8/0 DocID075 Rev 5

49 UM855 Hardware layout and configuration Table 9. Configuration elements related with smartcard and SWP Element Setting Configuration R9 SB R09 CN R6 SB SB5 R65 SB7 CN R09 in R9 in SB open CN I/O-bridged R09 out R9 in SB open CN I/O-bridged R9 out SB closed R9 out SB open R6 in SB open SB5 open CN I/O-bridged R6 out SB closed SB5 open R6 out SB open SB5 closed R65 in SB7 open CN I/O-bridged R65 out SB7 closed Default setting. Smartcard SWP cannot be handled: PB is routed to USB OTG FS port as USBOTG_OVRCR line, on top of being routed to SWIO port of smartcard Configuration dedicated for USB OTG FS operation. Smartcard SWP can be handled: PB is routed to SWIO port of smartcard. It is disconnected from any other resource that could affect the SWP operation Configuration dedicated for smartcard SWP operation Smartcard SWP cannot be handled: PB is routed to motor control as MC_PFC_Shutdown Configuration dedicated for motor control operation Smartcard SWP cannot be handled: PB is only routed to touch-sensing button and it is disconnected from any other resource. Configuration dedicated for touch-sensing button operation. Default setting. Smartcard controller U0 is supplied with clock: PB0 port is routed to XTAL of U0, as SmartCard_CLK line and it is not routed to other resources. Configuration dedicated for smartcard operation. Smartcard controller U0 is not supplied with clock: PB0 is routed to Quad-SPI Flash memory device as QSPI_D and it is not routed to other resources. Configuration dedicated for Quad-SPI Flash memory device operation. Smartcard controller U0 is not supplied with clock: PB0 is routed to motor control as MC_PWM_L line and it is not routed to other resources. Configuration dedicated for motor control operation. Default setting. Smartcard controller gets SmartCard_IO line: PC port of MCU is routed to IOUC port of U0, as SmartCard_IO line and it is not routed to other resources. Configuration dedicated for smartcard operation. Smartcard controller does not get SmartCard_IO line: PC port of MCU is routed to motor control as MC0PFC0IndCur line and it is not routed to other resources. Configuration dedicated for motor control operation. DocID075 Rev 5 9/0 00

50 Hardware layout and configuration UM Limitations The following limitations apply for the smartcard operation: Smartcard operation is mutually exclusive with LCD glass module, Quad-SPI Flash memory device and motor control operation. SWP operation is mutually exclusive with LCD glass module, touch-sensing button, motor control and USB OTG FS port operation, if the last operates as USB host. SWP can operate concurrently with USB OTG FS port acting as USB device..7. Operating voltage Smartcard operating ranging from V DD =.7 V to V DD =.6 V. However, the SWP only operates with the supply voltage of. V..8 Near-field communication (NFC) The STML76G-EVAL board can host an NFC transceiver board plugged in CN extension connector. Figure illustrates the way of attaching an NFC board. Figure. NFC board plugged into STML76G-EVAL board 50/0 DocID075 Rev 5

51 UM855 Hardware layout and configuration Table 0 shows the assignment of signals to CN connector. The serial communication with the module plugged in CN can either use SPI communication protocol (default) or UART communication protocol. Table 0. CN NFC connector terminal assignment CN terminal NFC line name MCU port Function NFC_IRQOUTN or UART_TX NFC_IRQINN or UART_RX PB7 PB6 NFC_NSS PF SPI slave select Interrupt output for NFC device Connected to STML76ZGT6 UART RX Interrupt input for NFC device Connected to STML76ZGT6 UART TX NFC_MISO PB SPI data, slave output 5 NFC_MOSI PB5 SPI data, slave input 6 NFC_SCK PB SPI serial clock 7 +V - Main power supply/power supply for RF drivers 8 - Ground.9 Dual-channel sigma-delta modulators STPMSL.9. STPMSL presentation With its DFSDM interface, the STML76ZGT6 microcontroller can directly interact with sigma-delta modulator devices, such as STPMSL. STPMSL comprises two analog measuring channels based on second-order sigma-delta modulators. Typically, it can be used in power metering where both voltage and current need to be known. One channel measures the voltage, the other channel measures the current. DAT port outputs converted measurement data on the DFSDM_DATIN line, received by the STML76ZGT6 DFSDM controller. The data from STPMSL are synchronized with DFSDM_CKOUT clock generated by the STML76ZGT6 DFSDM controller and received on CLK terminal of STPMSL. There are two STPMSL devices on STML76G-EVAL, sharing the DFSDM clock. One is wired such as to support a power-metering demonstrator. The other allows measuring temperature using the PT00 sensor. DocID075 Rev 5 5/0 00

52 Hardware layout and configuration UM855 Figure. Routing of STPMSL dual-channel sigma-delta modulators.9. STPMSL settings STPMSL operating parameters are set through its configuration terminals MS0, MS, MS and MS. On STML76G-EVAL, both devices are configured as follows: Voltage channel range: differential voltage +/- 00mV Current channel range: differential voltage +/- 00mV Internal voltage reference is used Input bandwidth: 0 to khz Temperature compensation: flattest +0ppm/ C DAT output: voltage and current samples multiplexed DATn output: not used HW mode selected for settings.9. STPMSL power metering STPMSL in U position simulates low-voltage AC power metering, with capacitive load impedance, to give different phase to voltage and current. 5/0 DocID075 Rev 5

53 UM855 Hardware layout and configuration Figure. Power measurement principle schematic diagram A low-voltage AC generator is to be applied by the user as shown in Figure. The shunt resistor is connected in series with the load to provide current measurement points to one of STPMSL input channels. The voltage measurement points for the other input channel are taken across the load. Figure 5 shows an extract of the corresponding schematic diagram. Warning: do not connect AC mains! Test example: The output of a low-voltage AC generator is connected to CN, terminals and. The amplitude is set between 00 mv and 00 mv and the frequency adjustable between 0 Hz and 00 Hz. With Hz frequency and the load formed of R7 of kω in parallel with C9 of.7 µf, the voltage and current phases are theoretically 5 degrees apart. Figure 5. STPMSL power metering schematic diagram STPMS power metering CN external generator input: pins and voltage of complex load: pins and shunt voltage : pins and C9.7uF current shunt R6 K R7 K R+jX Load C6 00nF U STPMSL-PUR CIP CIN VIP VIN 7 VBG AV 9 A MS0 0 Exposed pad C7 uf AC MS VCC MS DATn DAT CLK MS uf C 6 5 C uf DocID075 Rev 5 5/0 00

54 Hardware layout and configuration UM STPMSL for PT00 measurement PT00 is a resistor with temperature-dependent resistance. Usually, one of two methods is used for measuring temperature with a temperaturedependent resistor. In the first method, a known current is driven through the measuring resistor. The temperature is represented by the voltage measured across the resistor. In the second method, a known voltage is applied on the resistor and the current flowing through is measured, representing the temperature. In these methods, either an accurate current source or an accurate voltage source is required. With the dual-input measurement with STPMSL in U position, no such accurate current or voltage sources are required. Instead, a precision shunt resistor is required. One channel of the STPMSL measures the voltage across the precise shunt resistor, representing the current flowing through PT00. The other channel measures the voltage across PT00. Figure 6. Temperature measurement principle schematic diagram With voltage across and current through the PT00 resistor, the STML76ZGT6 microcontroller computes resistance PT00. For temperatures lower than +00 C, the temperature is given by the following equation, where PT00 is resistance of the PT00 resistor and T is temperature in degrees centigrade: T = ( PT00 00) ( 0.85).9.5 Limitations Operating voltage must be in the range from. V to.6 V..0 STML76ZGT6 current consumption measurement STML76ZGT6 has a built-in circuit allowing to measure its own current consumption (IDD) in Run and Low-power modes, except for Shutdown mode. 5/0 DocID075 Rev 5

55 UM855 Hardware layout and configuration It is strongly recommended that, the MCU supply voltage (_MCU line) does not exceed. V. This is because there are components on STML76G-EVAL supplied from. V that communicate with the MCU through I/O ports. Voltage exceeding. V on the MCU output port may inject current into. V-supplied peripheral I/Os and false the MCU current consumption measurement..0. IDD measurement principle - analog part The analog part is based on measuring voltage drop across a shunt resistor, amplified with a differential amplifier. The STML76ZGT6 microcontroller supply current is shunted, by jumper settings, to flow through the measurement Ω resistor R5: JP terminals and are to be open, terminals and closed. When the transistor T is in conductive state, the MCU supply current is proportional to the voltage across R5. When T is in highimpedance state, the MCU supply current is proportional to the voltage across the series of R5 and R. The former state is used for measuring the current consumption in dynamic run mode, the latter in low-power mode. The differential amplifier uses three stages U5B, U5C, U5D of quadruple operational amplifier device U5, TSZ. The gain is set to 50, so every ma of supply current is represented by additional 50 mv at the U5C output, terminal 8 of U5. The resistance formed with the series of R5 and R, when T is in high-impedance state, is of 00 Ω. It makes the voltage on terminal 8 of U5 increase by approximately 50 mv for every µa of MCU power consumption. The full-scale range, with at.8 V is about 0 µa. Even with precision resistors R6, R5, R9, R to set the gain of the differential amplifier, the output voltage may theoretically become negative. To avoid the need of negative power supply, a positive offset of about 0 mv is created at the output, at zero current consumption of the MCU. This offset does not need to be precise. Any dispersion is compensated through a calibration procedure detailed in Section.0.. For allowing the IDD measurement, the jumper in the JP header must be placed such as to short its terminals and. DocID075 Rev 5 55/0 00

56 Hardware layout and configuration UM855 Figure 7. Schematic diagram of the analog part of IDD measurement +5V Current direction from power supply C 00nF R8 K R K C75 00nF V+ V- decoupling capacitor close from TSZ part U5A TSZIPT T Shunt_x FDC606P G S D R5 [%] shunts R K[%] 5 6 U5B TSZIPT 7 R6 K6 0.% differential amplifier U5D TSZIPT R5 K6 0.% R9 80K 0.% U5C 0 TSZIPT 8 9 R 80K 0.% bypass path current measurement path JP Current direction _MCU to MCU.0. Low-power-mode IDD measurement principle - logic part The target microcontroller can only carry out actions for measuring a voltage when in dynamic run mode. This is the reason why, voltage representing the current consumed by the microcontroller when in low-power mode needs to be held by a sample-and-hold circuit, for being exploited by the microcontroller at a later time, when back in dynamic run mode. The sample-and-hold (S&H) circuit is built with U switch, R resistor and C7 sampling capacitor. The measurement of low-power-mode current consumption is started and end by the microcontroller in its dynamic run mode. As, between the start and end event, the microcontroller must transit through one of its low-power modes, an extra logic is required to time and control events during this state. It consists of U counter, U6 inverter and the transistor T. Figure 8 shows the corresponding schematic diagram. 56/0 DocID075 Rev 5

57 UM855 Hardware layout and configuration Figure 8. Schematic diagram of logic part of low-power-mode IDD measurement U5C TSZIPT 8 C nF Shunt_x000 U I/O O/I C VCC SN7LVCG66DCKT C7 5 U6 SN7LVCG0DCKT 00nF U Q Q Q Q5 5 Q 6 Q6 7 Q 8 VCC Q9 Q7 Q8 MR RS Rtc Ctc 7LV060PW R 0K C7 uf C77 nf T 5 6 FDC606P G S D C7 00nF R 5K R0 0K R7 0K PA5 IDD_Measurement PC5 IDD_WAKEUP R7 0K PF0 IDD_CNT_EN Oscillator frequency 0KHz The measurement process consists of phases: Phase - start and transiting to low-power mode While in dynamic run mode, the MCU sets IDD_CNT_EN signal on its PF0 port low, starting the measurement process. This makes the counters in U start counting the clock pulses generated with an own RC oscillator. At about 50 ms from the start, the Q output of U goes high, terminating the phase. After starting the measurement process, the MCU transits to low-power mode. The duration of the phase of about 50ms allows the MCU enough time for transiting into low-power mode. Phase - sampling The MCU is now in low-power mode. The phase starts with the Q port of U going high, 50 ms after the MCU, at that time in dynamic run mode, started the low-power-mode consumption current measurement process. The transistor T goes in high-impedance mode, which results in setting the analog part in high sensitivity state, needed for measuring very low currents. The Q port of U keeps the path between ports I/O and O/I of U conductive. The sampling capacitor C7 is charged through the resistor R to the voltage at the output of the differential analog amplifier, representing the current consumed by the MCU in low-power mode. The duration of the phase is about 50 ms. This time is needed to allow the voltage on the sampling capacitor C7 to stabilize. Phase - exiting low-power mode, measurement and end The MCU is in low-power mode. The voltage across C7 capacitor is now stabilized so it represents the current consumed by the MCU in low-power mode. The phase starts with setting the U path between ports O/I and I/O to non-conductive state, for the voltage across C7 to hold. The same event causes the IDD_WAKEUP signal for the MCU to change state, to signal to the MCU that the voltage on C7 is now ready for being measured. The MCU transits from low-power mode to dynamic run mode. The voltage on C7 representing the current the MCU consumed when it was in low-power mode, is now measured by the MCU, using the ADC port PA5, and stored. The Q port transits to low state at the same time as the Q goes high. As a consequence, the analog part of the IDD measurement circuit is back to low-sensitivity mode adapted for measuring the microcontroller supply current in its dynamic run mode. The phase and the whole measurement process ends with the microcontroller setting the IDD_CNT_EN signal back high. Figure 9 illustrates the timing of the low-power-mode current consumption measurement process. DocID075 Rev 5 57/0 00

58 Hardware layout and configuration UM855 Figure 9. Low-power-mode IDD measurement timing.0. IDD measurement in dynamic run mode In dynamic run mode, the IDD_CNT_EN remains high. The T is in conductive state, setting the shunt resistor to Ω. The U path from port to is permanently conductive and the voltage on the capacitor C7 follows the MCU current consumption. R allows filtering fast changes..0. Calibration procedure For the measurement to be precise, it is mandatory to perform a calibration before the measurement. The calibration allows subtracting, from the voltage measured across C7, the offset at the differential amplifier output, described in Section.0.. The calibration procedure consists in measuring the offset voltage when the current through the shunt resistor is zero. The current consumption values measured by the microcontroller are then compensated for offset, by subtracting the now-known offset number from the measured number. Setting the current through the shunt resistor to zero is reached through appropriate setting jumpers in the JP jumper header. 58/0 DocID075 Rev 5

59 UM855 Hardware layout and configuration Calibration procedure and current measurement compensation steps: On JP, short terminals and and open terminals and. The current through the shunt resistor is now zero. Run low-power-mode IDD measurement as described in Section.0.. The value V offset measured corresponds to offset of the differential amplifier. On JP, add a second jumper, to short terminals and, then remove the jumper from terminals and of JP. The MCU supply has not been interrupted and the supply current now passes through the shunt resistor. Run low-power-mode IDD measurement as described in Section.0.. The value V measured obtained corresponds to the sum of MCU supply current and the differential amplifier s offset V offset. The software computes a V out number representing the MCU supply current as V out = V measured - V offset Table. JP jumper settings during IDD measurement with calibration Jumper Setting Description JP Configuration used to measure V offset. JP in position STML76ZGT6 supply current does not flow through shunt resistor. JP JP Configuration to transit from direct to shunted supply to STML76ZGT6, without ever interrupting the MCU supply. JP Default setting. Configuration used to measure the MCU supply current. JP in IDD position STML76ZGT6 supply current flows through shunt resistor. DocID075 Rev 5 59/0 00

60 Connectors UM855 Connectors. RS- D-sub male connector CN9 Figure 0. RS- D-sub (DE-9M) 9-pole connector (front view) Table. RS- D-sub (DE-9M) connector CN9 with HW flow control and ISP support Terminal Terminal name Terminal Description NC 6 Bootloader_BOOT0 RS_RX (PB7) 7 NC RS_TX (PG) 8 Bootloader_RESET NC 9 NC Power connector CN The STML76G-EVAL board can be powered from a DC-5V external power supply via the CN jack illustrated in Figure. The central pin of CN must be positive. Figure. Power supply connector CN (front view) 60/0 DocID075 Rev 5

61 UM855 Connectors. LCD daughterboard connectors CN and CN Two 8-pin male headers CN and CN are used to connect to LCD glass module daughterboard MB979. The type of connectors, their mutual orientation, distance and terminal assignment are kept for a number of ST MCU evaluation boards. This standardization allows developing daughterboards that can be used in multiple evaluation kits. The width between CN pin and CN pin is 700 mils (7.78 mm). STML76ZGT6 ports routed to these two connectors can be accessed on odd CN and CN pins (the row of pin ), when no daughterboard is plugged in. Daughterboards plugging into CN and CN must keep the even terminals of CN and CN open. Table shows the signal assignment to terminals. Table. CN and CN daughterboard connectors CN CN Odd pin MCU port Odd pin MCU port PA9 PD PA8 PC 5 PA0 5 PC 7 PB9 7 PC0 9 PB 9 PB7 PB0 PC PB5 PC5 5 PB 5 PC6 7 PB 7 PC7 9 PB 9 PC8 PA5 PC9 PB8 PD8 5 PB5 5 PD9 7 PC 7 PD0 9 PC 9 PD PC0 PD PA PD 5 PA 5 PD 7 PB0 7 PD5 9 PA7 9 PE0 PA6 PE PB PE DocID075 Rev 5 6/0 00

62 Connectors UM855 Table. CN and CN daughterboard connectors (continued) CN CN Odd pin MCU port Odd pin MCU port 5 PB 5 PE 7 PB 7 PA. Extension connectors CN6 and CN7 Table. Daughterboard extension connector CN6 Pin Description Alternative Functions How to disconnect Alternative functions to use on the extension connector - - PG6 CODEC_INT, MC_ICL_Shutout 5 PA TMS/SWDIO 7 PA USBOTG_DP Remove R Remove R5, Open SB5 9 PG8 LPUART_RX_V Remove R58, R PG A 5 PD DFSDM_DATIN Remove R 7 PD0 D 9 PD5 FMC_NWE PG0 LCD_NE PD7 FMC_NE Remove R8 5 PF0 A0 7 PG USART_CTS_V Remove R9 9 PG IC_SDA Remove R58 PG USART_RTS Remove R6 PG IC_SCL Remove R6 5 PG5 IOExpander_INT Remove R8 7 PF A Do not use Trace connector CN and JTAG connector CN5 Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 Cannot be disconnected from SRAM and Flash memory, but is an input for SRAM and Flash memory Cannot be disconnected from TFT LCD level shifters U and U, but is an input for TFT LCD. Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 6/0 DocID075 Rev 5

63 UM855 Connectors Table. Daughterboard extension connector CN6 (continued) Pin Description Alternative Functions How to disconnect Alternative functions to use on the extension connector V - - PG7 LPUART_TX Remove R9, R89 6 PA USBOTG_DM Remove R 8 PA TCK/SWCLK 0 PG5 A5 PG A PG A 6 PD D 8 PD FMC_NOE 0 PG9 FMC_NE Remove R - - PD6 SAI_SDA, FMC_NWAIT 6 PF A 8 D5V - - Do not use Trace connector CN and JTAG connector CN5 Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 Remove R5, open SB0 0 PC Wake-up Remove R PF A PF A PF5 A5 0 PB6 USART_TX Remove R8 Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 Remove R8 to deselect SRAM U Remove R to deselect Flash memory U5 Table 5. Daughterboard extension connector CN7 Pin Description Alternative Functions How to disconnect Alternative functions to use on the extension connector - - PE D - DocID075 Rev 5 6/0 00

64 Connectors UM855 Table 5. Daughterboard extension connector CN7 (continued) Pin Description Alternative Functions How to disconnect Alternative functions to use on the extension connector 5 PE D9-7 PE0 D7-9 PE8 D5 - PG A - PB LED, MC_DissipativeBrake PF A6-9 PF NFC_NSS Remove R5, SB PE A0, TRACE_D Remove R8, SB0 PE5 A, TRACE_D Remove R85, SB8 Do not connect the NFC daughterboard to connector CN 5 PC OSC_IN Remove R87, Close SB 7 PF6 SAI_SDB Remove R05 9 PF9 PF0 SAI_FSB, MC_PFC_sync IDD_CNT_EN, MC_PFC_PWM Remove R90, SB5 Remove R9, SB7 PH OSC_OUT Remove R95, close SB 5 PA5 IDD_Measurement Remove R69 7 PA0 OpAmp_INP, MC_EncA PE5 D - PE D0-6 PE D8-8 PE9 D6-0 PE7 D - PG0 A0 - PF5 A9-6 PF A8-8 PF A7-0 BOOT0 BootLoader from UART Remove R8, SB5 Remove JP8 PE6 A, TRACE_D Remove R86, SB9 PC5 OSC_OUT Remove R88, close SB 6/0 DocID075 Rev 5

65 UM855 Connectors Table 5. Daughterboard extension connector CN7 (continued) Pin Description Alternative Functions How to disconnect Alternative functions to use on the extension connector PF7 SAI_MCKB Remove R06 0 PF8 SAI_SCKB Remove R89 RESET# - - PH0 OSCIN Remove crystal X, C5, close SB 6 PC VLCD Remove R9 8 PA ADC_DAC Remove R ST-LINK/V- programming connector CN6 The connector CN6 is used only for embedded ST-LINK/V- programming, during board manufacture. It is not populated by default and not for use by the end user..6 ST-LINK/V- Standard-B USB connector CN7 The USB connector CN7 is used to connect the on-board ST-LINK/V- facility to PC for flashing and debugging software. Figure. USB type B connector CN7 (front view) DocID075 Rev 5 65/0 00

66 Connectors UM855 Table 6. USB Standard-B connector CN7 Terminal Description Terminal Description VBUS(power) DM 5,6 Shield DP JTAG connector CN5 Figure. JTAG debugging connector CN5 (top view) Table 7. JATG debugging connector CN5 Terminal Function / MCU port Terminal Function / MCU port power power PB 5 PA5 6 7 PA 8 9 PA 0 RTCK PB 5 RESET# 6 7 DBGRQ 8 9 DBGACK 0 66/0 DocID075 Rev 5

67 UM855 Connectors.8 ETM trace debugging connector CN Figure. Trace debugging connector CN (top view) Table 8. Trace debugging connector CN Terminal Function / MCU port Terminal Function / MCU port power TMS/PA TCK/PA 5 6 TDO/PB 7 KEY 8 TDI/PA5 9 0 RESET# TraceCLK/PE TraceD0/PE or SWO/PB 5 6 TraceD/PE or ntrst/pb 7 8 TraceD/PE5 9 0 TraceD/PE6 DocID075 Rev 5 67/0 00

68 Connectors UM855.9 microsd card connector CN8 Figure 5. microsd card connector CN8 Table 9. microsd card connector CN8 Terminal Terminal name (MCU port) Terminal Terminal name (MCU port) SDIO_D (PC0) 6 Vss/ SDIO_D (PC) 7 SDIO_D0 (PC8) SDIO_CMD (PD) 8 SDIO_D (PC9) 9 5 SDIO_CLK (PC) 0 MicroSDcard_detect (PA8).0 ADC/DAC connector CN8 Figure 6. Analog input-output connector CN8 (top view) 68/0 DocID075 Rev 5

69 UM855 Connectors Table 0. Analog input-output connector CN8 Terminal Function / MCU port Terminal Function / MCU port analog input-output PA. RF-EEPROM daughterboard connector CN Figure 7. RF-EEPROM daughterboard connector CN (front view) Table. RF-EEPROM daughterboard connector CN Terminal Terminal name (MCU port) Terminal Terminal name (MCU port) IC_SDA (PG) 5 +V NC 6 NC IC_SCL (PG) 7 EXT_RESET(PC6) 8 +5 V. Motor control connector CN Figure 8. Motor control connector CN (top view) DocID075 Rev 5 69/0 00

70 Connectors UM855 Table. Motor control connector CN CN terminal Description MCU port CN terminal MCU port Description Emergency STOP PC9 - PWM_H PC6-5 PWM_L PA7 6-7 PWM_H PC7 8-9 PWM_L PB0 0 - PWM_H PC8 - PWM_L PB PC5 BUS VOLTAGE 5 CURRENT A PC0 6-7 CURRENT B PC 8-9 CURRENT C PC 0 - ICL Shutout PG6 - DISSIPATIVE BRAKE PB PC PCD Ind Current 5 +5V power - 6 PA Heat sink temperature 7 PFC SYNC PF V power 9 PFC PWM PF0 0 PB PFC Shut Down Encoder A PA0 PA6 PFC Vac Encoder B PA PA Encoder Index. USB OTG FS Micro-AB connector CN Figure 9. USB OTG FS Micro-AB connector CN (front view) Table. USB OTG FS Micro-AB connector CN Terminal Terminal name (MCU port) Terminal Terminal name (MCU port) VBUS (PA9 & PB) ID (PA0) D- (PA) 5 D+ (PA) /0 DocID075 Rev 5

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