Comprehensive Layout-based ESD Check Methodology with Fast Full-chip Static and Macro-level Dynamic Solutions

Size: px
Start display at page:

Download "Comprehensive Layout-based ESD Check Methodology with Fast Full-chip Static and Macro-level Dynamic Solutions"

Transcription

1 Comprehensive Layout-based ESD Check Methodology with Fast Full-chip Static and Macro-level Dynamic Solutions Norman Chang, Ting-Sheng Ku, Jai Pollayil 26 th International Conference on VLSI January 2013 Pune, India

2 Agenda ESD Overview Verification Solutions Static verification on HBM/MM/CDM and test cases Block/IP-level dynamic ESD analysis and HBM/CDM test cases Summary 1/11/2013 2

3 1/11/ Worsening Trend in ESD Thinner oxide and lower junction thermal breakdown voltages Reduced failure current density limit Worsening CDM issue for high-frequency designs White Paper 2: A case for lowering component level CDM ESD specifications and requirements, April, 2010

4 ESD Models 1/11/2013 4

5 1/11/ Full-chip ESD Protection Methodology Protection Circuit Requirement Consider full permutation Timely and uniform turn-on Low impedance path for discharging No impact on normal operation Protection Coverage Regular I/O Intra-domain Multi-domain High-speed I/O

6 Mapping ESD Verification Flow to IC Design Flow [3] 1/11/ IC design flow needs to be synchronized with ESD development, implementation, and check

7 Agenda ESD Overview Verification Solutions Static verification on HBM/MM/CDM and test cases Block/IP level dynamic ESD analysis and HBM/CDM test cases Summary 1/11/2013 7

8 1/11/ Requirements for Fast Full-chip Static and Macro-level Dynamic Solutions Fast full-chip layout-based checks High-capacity and accurate metal/via resistance extraction Inter- and intra-domain resistance checks Realistic I-V model (snapback included) for diode/clamp in R and current density checks Current density and voltage check, particularly critical for IP Full-chip ESD check required for identifying problems such as inter-block connectivity related Macro-level dynamic ESD solution Transistor-level stress analysis for 1M+ transistor blocks within couple of days Consider substrate effect, clamp modeling with snapback, metal grid RLC, and pogo pin modeling

9 1/11/ Analysis Coverage for SoC ESD Integrity Verification Pad / Clamp Layout Connectivity Wire / Via Current Density Signal to Power(S2P) Ground to Signal(G2S) Power to Ground(P2G) Current Density Violation Map Domain Crossing Checks Signal to Ground (S2G) D1-D4 to Power Clamp D5-D6 to Power Clamp Current density violations Routing congestion, narrow wires Voltage check on all the P/G/S nodes

10 1/11/ Resistance Check Between Gates/Macros to Clamps Sample a subset of cells based on their minimum R path to respective nearby clamps Calculate the smallest loop R from power/ground nodes of the sampled gates Calculate the smallest arc R from the sampled pins of a macro to respective nearby clamps

11 1/11/ Current Density Check Model diode/clamp with I-V curve including snapback characteristics Automatically determines the on/off clamp in the discharging paths on off For disjoint discharging paths, parallel threads used to achieve fast, full-chip run Check current density of wires/vias

12 1/11/ Early ESD Planning Optimize the need and placement of ESD cells early in the design flow Easily insert and/or modify ESD cells, preferably using GUI

13 Full-chip ESD Verification Flow 1/11/

14 1/11/ Full-chip ESD Verification Example Large SoC with ~40M instances 20 power/ground domains 600 signal domains 2000 C4 bumps and 400 package pins Perform HBM on all power/ground/signal domains Perform CDM on sampled instances

15 Run Time and Memory Statistics 1/11/

16 1/11/ Nvidia Examples on Detection of HBM Issues with Static Solution

17 1/11/ Static ESD Check Flow at Nvidia Static Resistance and Current Density Check Apache s PathFinder performed full-chip resistance and current density (CD) checks between diodes and clamps, and also between bumps and clamps Goal is to identify and fix any resistance and current density larger than design target values before tape-out

18 1/11/ Resistance Check Statistics PathFinder took 5.5 hours for fullchip static resistance analysis Calculated resistance between clamp-diode pairs within 2000um moving radius constraint Calculated 826 bump to clamp resistance within 2000um moving radius constraint

19 Nvidia Example #1 HBM Check USB Interface Block in Full-Chip Analysis Detected in pre-tape-out check, saved a metal spin PathFinder calculated effective 2.68 ohm resistance between diode and clamp in USB cell Shortest Resistance Path (SPT) tracing performed to identify the larger than expected resistance paths SPT analysis 1/11/

20 1/11/ Nvidia Example #2 HBM Check HDMI Block in Full-Chip Analysis PathFinder calculated 3.35 ohm resistance between diode and clamp in HDMI cell Highlighted shortest resistance path clearly identified problems buried deep in layout Detected insufficient top-level power connection before tape-out

21 1/11/ Nvidia Example #3 CD Check High Current Density Issue in I/O Area High current density observed from D5->VSS->D2 Current Density Map i Electro-migration Map

22 1/11/ Other Examples on Detection of HBM Issues with Static Solution

23 1/11/ Case Study: ESD Analysis for Analog Chip Very high resistance between I/O bump to clamp causing SI failure on chip, detected by transistor-level static ESD Analysis IO BUMP ESD Analysis GND BUMP CLAMP

24 1/11/ Debugging Shortest Resistance Path on Analog Chip Shortest resistance path through wires/vias can be highlighted and shown on a table

25 Current Density Checks Example Comprehensive verification of all the ESD discharge paths Place core clamps here Routing congestion, narrow wires Identify current crowding in diode/clamp fingers Instance-level differential voltage check for guiding core clamp placement Differential voltage check between driver/receiver pair 1/11/

26 1/11/ Large R Problem Highlighted Between Instance and Clamp (CDM Failure) Long M3 connection (~250um) and stack via (connecting M3 to M1 through M4) causing high VDD ARC resistance

27 Agenda ESD Overview Verification Solutions Static verification on HBM/MM/CDM and test cases Block/IP-level dynamic ESD analysis and HBM/CDM test cases Summary 1/11/

28 1/11/ ESD Dynamic Methodology Perform diagnosis of potential failure mechanisms when silicon failures occur Verify robustness of the fix by comparing differential stressed values of the failed junctions Check potential design weaknesses of CDM events before tape-out on analog / mixed-signal / I/O blocks

29 Target Applications for Dynamic ESD Analysis Target Users: Initially ESD experts Eventually mixed-signal macros designers Transistor Count: ~1M per macro Dynamic ESD check coverage beyond static ESD check Model physically correct CDM discharging behavior Explicitly detect worst transient voltage stressed junctions Evaluate clamp transient effectiveness related to design and placement Perform trade-off on peak vs. duration device failure mode 1/11/

30 Cross-domain CDM Example: Cross-domain Check and Possible Failure Mechanism for PLL + VDD1 VDD2 Power Clamp 1 Vgs Power Clamp 1 VSS1 VSS2 Rbus GND Possible Vgs junction failure due to disparate discharging rate from gate and source nodes to CDM grounded pin 1/11/

31 1/11/ Core Technology Requirements Electrical modeling Substrate RC and well diode extraction Snapback behavior model for ESD clamps P/G RCL extraction Specialized ESD simulation engine Handling of the non-convergence behavior for ESD circuits High performance and large capacity for post-layout designs Layout-based debugging GUI Cross probing between netlist, layout, and voltage waveforms

32 1/11/ Substrate Model for Dynamic ESD Extract substrate well diodes and RC grid GND R mesh VDD R mesh P+ N+ N+ P+ P+ N+ P-well N_well P-substrate

33 1/11/ Block-based ESD Dynamic Flow Import DSPF (Detailed Standard Parasitic Format) of coupled signal RC netlist and create P/G contact pins Extract metal grid RLC, substrate RC, and well diodes Hook up the two netlist above through contact pins and create test bench for HBM or CDM zapping condition Perform the simulation on the final netlist above and generate junction stress report

34 1/11/ Nvidia Examples on Detection of HBM/CDM Issues with Dynamic Solution

35 HBM Case Comparison: Grounded vs. Floating P-well Guard Ring in RC-based Clamp Both test cases with AGND -2000V HBM zap and AVDD grounded Grounded P-well guard ring case failed, while floating P-well guard ring case passed AVDD AVDD sig Pwell guard ring grounded _ sig Pwell guard ring floating _ AGND AGND Failed clamp Passed clamp 1/11/

36 1/11/ Snapshot of HBM Failure Case AVDD sig P-well guard ring grounded _ AGND Failed clamp Lab de-processed result of failed HBM test on I/O with grounded P-well guard ring

37 1/11/ HBM Test Case Device count : 12K subckt (xmos), 6K Diodes Extracted elements: 5.79M RLCs Simulation Conditions: Initialized at -2000V (HBM test) Zap Init at -2000V 3.0u 1525ohm AGND VDD 100pf 0.1f P/G RLC AVDD Macro Block w/ coupled signal RC GND HBM Analysis Setup: 48min Simulation: 2hr Peak memory use: 15GB Substrate RC w/ Well diode

38 Melt-down of Center Finger of RC-based Clamp Due to Parasitic BJT Turn-on (HBM Failure) Center finger furthest from grounded Pwell guard ring result in largest resistance from the AGND zap point Vbs of finger higher due to substrate node distance from Pwell guard ring Higher Vbs of center finger with higher Ids current may turn on parasitic bipolar earlier than other fingers, causing center finger melt down AGND X AVDD Center Finger of RC-based Clamp 1/11/

39 D/G/S/B Node Waveforms of RC-based Clamp Fingers with Grounded Substrate Pwell Guard Ring 1.37ns Vg Vb of different fingers w/ the center finger having largest Vbs Vd Vs Vbs of different clamp fingers have varying amplitude, with center finger having largest Vbs causing non-uniform turn-on of the center finger and triggering its parasitic BJT 1/11/

40 D/G/S/B Node Waveforms of RC-based Clamp Fingers with Substrate Floating Pwell Guard Ring 1.37ns Vg Vd Vb of different fingers Vs Vbs of different clamp fingers have similar amplitude, resulting in uniform turn-on among all fingers 1/11/

41 1/11/ Worst Stress Movie for HBM AGND -2000V Zap with Hot Spot on Center Finger of RC-based Clamp Hot spot at 1.37nsec of the HBM zap at the center finger of RC-based clamp

42 1/11/ Example CDM Test Case Device count : 62,256 subckt (xmos), 541 Diodes Extracted elements: 3,709,648 RLCs Simulation Conditions: Initialized at -500V (ESD class choice) Zap Lpogo Rpogo Cpogo IOP ION P/G RLC VDD VDDP Macro Block w/ coupled signal RC GND CDM Analysis Setup: 1hr Simulation: 2hr Peak Memory Use: 25 GB Substrate RC w/ well diode Cdut of 3pF evenly distributed among substrate Tuned substrate_to_gnd_cap to match expected pogo pin peak current

43 1/11/ CDM Issue Due to Discharging Paths Race Condition Worst Junction Worst junction voltage waveform Pogo pin current waveform Impedance mismatch between I/O (sig) and LDO bias net caused large Vgd junction stress on -500V zap LDO bias net heavily referenced to ground due to large capacitance

44 Stress Movie on CDM Test Case: IOP Zap at -500V -500V Zap at I/O Pin Highest stress occurred at failed junction (Vgd) on the top around 137psec; the 2 nd ranked stressed junction with similar design issue, except the I/O transistor size is much larger 1/11/

45 1/11/ Failure Emission Image for CDM Test Case emission site Lab emission result of failed CDM test on high-speed I/O

46 1/11/ PMOS Passgate Insertion as Proposed Fix for Failed Junction Stress Reduction PMOS passgate PMOS passgate inserted Worst junction voltage waveform PMOS passgate inserted at the gate of the failed NMOS isolates the junction from bias net loading, allowing the junction voltage delta to stay within device tolerance

47 1/11/ PathFinder: SoC and IP ESD Integrity DEF / GDS Technology Spice Netlist/ Clamp Models ESD rules Connectivity Rule based Checks Dynamic Checks Isolated bumps Inter domain clamp checks Resistance Checks Current Density/ IR checks Device stress voltage checks Current discharge waveforms Layout based Flexible check Interactive fixing Early ESD Planning I/O / IP level checks SoC level checks Package Support

48 1/11/ Summary With tighter design margin in 45/28/20/14nm technology nodes, ESD verification is a must for SoC, mixed-signal, and custom designs Static ESD methodology required for sign-off check on large SoC and mixed-signal chips Passing CDM at standard voltage is getting more difficult for high-speed I/O, mixed-signal designs Dynamic ESD methodology required for the diagnosis and predictive simulation of HBM/CDM events

49 1/11/ References [1] N. Chang, Y. Liao, Y. Li, P. Johari, A. Sarkar, Efficient Multi-domain ESD Analysis and Verification for Large SoC Designs, ESD/EOS Symposium, [2] Ting-Sheng Ku, Jau-Wen Chen, George Kokai, Norman Chang, Shen Lin, Yu Liu, Ying-Shiun Li, Bo Hu, ESD Dynamic Methodology for Diagnosis and Predictive Simulation of HBM/CDM Events, ESD/EOS Symposium, [3] Michael Khazhinsky, Victor Cao, Harald Gossner, Gianluca Boselli, Melanie Etherton, Electronic Design Automation (EDA) Solutions for ESD-robust Design and Verification, CICC [4] ESDA Technical Report #TR , ESD Electronic Design Automation Checks, ESDA Committee, 2011.

TABLE OF CONTENTS 1.0 PURPOSE INTRODUCTION ESD CHECKS THROUGHOUT IC DESIGN FLOW... 2

TABLE OF CONTENTS 1.0 PURPOSE INTRODUCTION ESD CHECKS THROUGHOUT IC DESIGN FLOW... 2 TABLE OF CONTENTS 1.0 PURPOSE... 1 2.0 INTRODUCTION... 1 3.0 ESD CHECKS THROUGHOUT IC DESIGN FLOW... 2 3.1 PRODUCT DEFINITION PHASE... 3 3.2 CHIP ARCHITECTURE PHASE... 4 3.3 MODULE AND FULL IC DESIGN PHASE...

More information

RMAP software for resistance verification of power nets and ESD protection structures

RMAP software for resistance verification of power nets and ESD protection structures RMAP software for resistance verification of power nets and ESD protection structures Maxim Ershov*, Meruzhan Cadjan*, Yuri Feinberg*, and Thomas Jochum** (*) Silicon Frontline Technology, (**) Intersil

More information

Power IC 용 ESD 보호기술. 구용서 ( Yong-Seo Koo ) Electronic Engineering Dankook University, Korea

Power IC 용 ESD 보호기술. 구용서 ( Yong-Seo Koo ) Electronic Engineering Dankook University, Korea Power IC 용 ESD 보호기술 구용서 ( Yong-Seo Koo ) Electronic Engineering Dankook University, Korea yskoo@dankook.ac.kr 031-8005-3625 Outline Introduction Basic Concept of ESD Protection Circuit ESD Technology Issue

More information

Chapter 2 On-Chip Protection Solution for Radio Frequency Integrated Circuits in Standard CMOS Process

Chapter 2 On-Chip Protection Solution for Radio Frequency Integrated Circuits in Standard CMOS Process Chapter 2 On-Chip Protection Solution for Radio Frequency Integrated Circuits in Standard CMOS Process 2.1 Introduction Standard CMOS technologies have been increasingly used in RF IC applications mainly

More information

EDA Software for Verification of Metal Interconnects in ESD Protection Networks at Chip, Block, and Cell Level

EDA Software for Verification of Metal Interconnects in ESD Protection Networks at Chip, Block, and Cell Level EDA Software for Verification of Metal Interconnects in ESD Protection Networks at Chip, Block, and Cell Level Maxim Ershov (1)*, Yuri Feinberg (1), Meruzhan Cadjan (1), David Klein (2), Melanie Etherton

More information

Modeling of High Voltage Devices for ESD Event Simulation in SPICE

Modeling of High Voltage Devices for ESD Event Simulation in SPICE The World Leader in High Performance Signal Processing Solutions Modeling of High Voltage Devices for ESD Event Simulation in SPICE Yuanzhong (Paul) Zhou, Javier A. Salcedo Jean-Jacques Hajjar Analog Devices

More information

SYSTEM LEVEL ESD - BEYOND THE COMPONENT LEVEL IC PROTECTION CHARVAKA DUVVURY

SYSTEM LEVEL ESD - BEYOND THE COMPONENT LEVEL IC PROTECTION CHARVAKA DUVVURY SYSTEM LEVEL ESD - BEYOND THE COMPONENT LEVEL IC PROTECTION CHARVAKA DUVVURY 1 1 Outline Impact from Advanced Technologies and High Speed Circuit Designs on Component Level ESD System Level ESD and the

More information

Electromagnetic Compatibility ( EMC )

Electromagnetic Compatibility ( EMC ) Electromagnetic Compatibility ( EMC ) ESD Strategies in IC and System Design 8-1 Agenda ESD Design in IC Level ( ) Design Guide Lines CMOS Design Process Level Method Circuit Level Method Whole Chip Design

More information

ESD Protection Circuits: Basics to nano-metric ASICs

ESD Protection Circuits: Basics to nano-metric ASICs ESD Protection Circuits: Basics to nano-metric ASICs Manoj Sachdev University of Waterloo msachdev@ece.uwaterloo.ca September 2007 1 Outline Group Introduction ESD Basics Basic ESD Protection Circuits

More information

ESD 충북대학교 전자정보대학 김영석

ESD 충북대학교 전자정보대학 김영석 ESD 충북대학교 2011.9 1 ElectroStatic Charge Generation When 2 Surfaces in Contact then Separate Some Atom Electrons Move Causing Imbalance One Surface Has Positive Charge & One Surface Has Negative Charge

More information

ESD Protection Design for Mixed-Voltage I/O Interfaces -- Overview

ESD Protection Design for Mixed-Voltage I/O Interfaces -- Overview ESD Protection Design for Mixed-Voltage Interfaces -- Overview Ming-Dou Ker and Kun-Hsien Lin Abstract Electrostatic discharge (ESD) protection design for mixed-voltage interfaces has been one of the key

More information

ESD Protection Device Simulation and Design

ESD Protection Device Simulation and Design ESD Protection Device Simulation and Design Introduction Electrostatic Discharge (ESD) is one of the major reliability issues in Integrated Circuits today ESD is a high current (1A) short duration (1ns

More information

ESD Protection Scheme for I/O Interface of CMOS IC Operating in the Power-Down Mode on System Board

ESD Protection Scheme for I/O Interface of CMOS IC Operating in the Power-Down Mode on System Board ESD Protection Scheme for I/O Interface of CMOS IC Operating in the Power-Down Mode on System Board Kun-Hsien Lin and Ming-Dou Ker Nanoelectronics and Gigascale Systems Laboratory Institute of Electronics,

More information

Improved Circuit Reliability/Robustness. Carey Robertson Product Marketing Director Mentor Graphics Corporation

Improved Circuit Reliability/Robustness. Carey Robertson Product Marketing Director Mentor Graphics Corporation Improved Circuit Reliability/Robustness Carey Robertson Product Marketing Director Mentor Graphics Corporation Reliability Requirements are Growing in all Market Segments Transportation Mobile / Wireless

More information

Apache s Power Noise Simulation Technologies

Apache s Power Noise Simulation Technologies Enabling Power Efficient i Designs Apache s Power Noise Simulation Technologies 1 Aveek Sarkar VP of Support Apache Design Inc, A wholly owned subsidiary of ANSYS Trends in Today s Electronic Designs Low-power

More information

Latch-up Verification / Rule Checking Throughout Circuit Design Flow

Latch-up Verification / Rule Checking Throughout Circuit Design Flow Latch-up Verification / Rule Checking Throughout Circuit Design Flow Michael Khazhinsky ESD and Latch-up Design Silicon Labs April 2016 Motivation The verification of latch-up protection networks in modern

More information

RTL2GDS Low Power Convergence for Chip-Package-System Designs. Aveek Sarkar VP, Technology Evangelism, ANSYS Inc.

RTL2GDS Low Power Convergence for Chip-Package-System Designs. Aveek Sarkar VP, Technology Evangelism, ANSYS Inc. RTL2GDS Low Power Convergence for Chip-Package-System Designs Aveek Sarkar VP, Technology Evangelism, ANSYS Inc. Electronics Design Complexities Antenna Design and Placement Chip Low Power and Thermal

More information

Characterizing Touch Panel Sensor ESD Failure with IV-Curve TLP (System Level ESD)

Characterizing Touch Panel Sensor ESD Failure with IV-Curve TLP (System Level ESD) Characterizing Touch Panel Sensor ESD Failure with IV-Curve TLP (System Level ESD) Wei Huang, Jerry Tichenor, David Pommerenke 2014 ESDA Exhibition Booth 606 Web: www.esdemc.com Email: info@esdemc.com

More information

Design of local ESD clamp for cross-power-domain interface circuits

Design of local ESD clamp for cross-power-domain interface circuits This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,*-* Design of local ESD clamp for cross-power-domain

More information

New Layout Scheme to Improve ESD Robustness of I/O Buffers in Fully-Silicided CMOS Process

New Layout Scheme to Improve ESD Robustness of I/O Buffers in Fully-Silicided CMOS Process New Layout Scheme to Improve ESD Robustness of I/O Buffers in Fully-Silicided CMOS Process Ming-Dou Ker (1, 2), Wen-Yi Chen (1), Wuu-Trong Shieh (3), and I-Ju Wei (3) (1) Institute of Electronics, National

More information

Will Silicon Proof Stay the Only Way to Verify Analog Circuits?

Will Silicon Proof Stay the Only Way to Verify Analog Circuits? Will Silicon Proof Stay the Only Way to Verify Analog Circuits? Pierre Dautriche Jean-Paul Morin Advanced CMOS and analog. Embedded analog Embedded RF 0.5 um 0.18um 65nm 28nm FDSOI 0.25um 0.13um 45nm 1997

More information

IN DEEP submicrometer CMOS technology, electrostatic

IN DEEP submicrometer CMOS technology, electrostatic 102 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 1, MARCH 2006 ESD Failure Mechanisms of Analog I/O Cells in 0.18-µm CMOS Technology Ming-Dou Ker, Senior Member, IEEE, Shih-Hung Chen,

More information

SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions Patrice Joubert Doriol 1, Aurora Sanna 1, Akhilesh Chandra 2, Cristiano Forzan 1, and Davide Pandini 1 1 STMicroelectronics, Central

More information

PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05

PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05 PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05 Silvaco s What is a PDK? Which people build, use, and support PDKs? How do analog/mixed-signal/rf engineers use a PDK to design ICs? What is an analog/mixed-signal/rf

More information

Physical Implementation

Physical Implementation CS250 VLSI Systems Design Fall 2009 John Wawrzynek, Krste Asanovic, with John Lazzaro Physical Implementation Outline Standard cell back-end place and route tools make layout mostly automatic. However,

More information

Microelectronics Reliability

Microelectronics Reliability Microelectronics Reliability 53 (2013) 208 214 Contents lists available at SciVerse ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel PMOS-based power-rail ESD

More information

ESD Protection Design With Low-Capacitance Consideration for High-Speed/High- Frequency I/O Interfaces in Integrated Circuits

ESD Protection Design With Low-Capacitance Consideration for High-Speed/High- Frequency I/O Interfaces in Integrated Circuits Recent Patents on Engineering 2007, 1, 000-000 1 ESD Protection Design With Low-Capacitance Consideration for High-Speed/High- Frequency I/O Interfaces in Integrated Circuits Ming-Dou Ker* and Yuan-Wen

More information

Lecture 20: Package, Power, and I/O

Lecture 20: Package, Power, and I/O Introduction to CMOS VLSI Design Lecture 20: Package, Power, and I/O David Harris Harvey Mudd College Spring 2004 1 Outline Packaging Power Distribution I/O Synchronization Slide 2 2 Packages Package functions

More information

ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process

ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process Chun-Yu Lin 1, Li-Wei Chu 1, Ming-Dou Ker 1, Ming-Hsiang Song 2, Chewn-Pu Jou 2, Tse-Hua Lu 2, Jen-Chou Tseng

More information

THE trend of IC technology is toward smaller device dimension

THE trend of IC technology is toward smaller device dimension 24 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, NO. 1, MARCH 2004 Abnormal ESD Failure Mechanism in High-Pin-Count BGA Packaged ICs Due to Stressing Nonconnected Balls Wen-Yu Lo and Ming-Dou

More information

CHARGED DEVICE MODEL ELECTROSTATIC DISCHARGE FAILURES IN SYSTEM ON A CHIP AND SYSTEM IN A PACKAGE DESIGNS NICHOLAS ALLEN OLSON DISSERTATION

CHARGED DEVICE MODEL ELECTROSTATIC DISCHARGE FAILURES IN SYSTEM ON A CHIP AND SYSTEM IN A PACKAGE DESIGNS NICHOLAS ALLEN OLSON DISSERTATION CHARGED DEVICE MODEL ELECTROSTATIC DISCHARGE FAILURES IN SYSTEM ON A CHIP AND SYSTEM IN A PACKAGE DESIGNS BY NICHOLAS ALLEN OLSON DISSERTATION Submitted in partial fulfillment of the requirements for the

More information

SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions Patrice Joubert Doriol 1, Aurora Sanna 1, Akhilesh Chandra 2, Cristiano Forzan 1, and Davide Pandini 1 1 STMicroelectronics, Central

More information

Cluster-based approach eases clock tree synthesis

Cluster-based approach eases clock tree synthesis Page 1 of 5 EE Times: Design News Cluster-based approach eases clock tree synthesis Udhaya Kumar (11/14/2005 9:00 AM EST) URL: http://www.eetimes.com/showarticle.jhtml?articleid=173601961 Clock network

More information

I/O and ESD Device Optimization for Nanometer Node CMOS Technologies. IRCC IIT-Bombay industry impact award 2008

I/O and ESD Device Optimization for Nanometer Node CMOS Technologies. IRCC IIT-Bombay industry impact award 2008 I/O and ESD Device Optimization for Nanometer Node CMOS Technologies IRCC IIT-Bombay industry impact award 2008 Team members Mayank Shrivastava (Ph.D. from IIT-Bombay, Graduated in 2010) Faculty Members

More information

ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process

ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process Tao-Yi Hung and Ming-Dou Ker Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan Abstract- ESD protection design

More information

Impact of Voltage Overshoots on ESD Protection Effectiveness for High Voltage Applications

Impact of Voltage Overshoots on ESD Protection Effectiveness for High Voltage Applications 1 technische universität dortmund International ESD Workshop: 2010 Impact of Voltage Overshoots on ESD Protection Effectiveness for High Voltage Applications Yiqun Cao 1,2, Ulrich Glaser 1, Alevtina Podgaynaya

More information

AOZ8882. Ultra-Low Capacitance TVS Diode Array. General Description. Features. Applications. Typical Application

AOZ8882. Ultra-Low Capacitance TVS Diode Array. General Description. Features. Applications. Typical Application Ultra-Low Capacitance TS Diode Array General Description The AOZ8882 is a transient voltage suppressor array designed to protect high speed data lines such as HDMI, MDDI, USB, SATA, and Gigabit Ethernet

More information

Physical Design Implementation for 3D IC Methodology and Tools. Dave Noice Vassilios Gerousis

Physical Design Implementation for 3D IC Methodology and Tools. Dave Noice Vassilios Gerousis I NVENTIVE Physical Design Implementation for 3D IC Methodology and Tools Dave Noice Vassilios Gerousis Outline 3D IC Physical components Modeling 3D IC Stack Configuration Physical Design With TSV Summary

More information

Methodology on Extracting Compact Layout Rules for Latchup Prevention in Deep-Submicron Bulk CMOS Technology

Methodology on Extracting Compact Layout Rules for Latchup Prevention in Deep-Submicron Bulk CMOS Technology IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 16, NO. 2, MAY 2003 319 Methodology on Extracting Compact Layout Rules for Latchup Prevention in Deep-Submicron Bulk CMOS Technology Ming-Dou Ker,

More information

ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS)

ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS) ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS) Objective Part A: To become acquainted with Spectre (or HSpice) by simulating an inverter,

More information

Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits

Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits Ming-Dou Ker, Hsin-Chyh Hsu, and Jeng-Jie Peng * Nanoelectronics and

More information

IN ADVANCED nanoscale CMOS technology, the electrostatic

IN ADVANCED nanoscale CMOS technology, the electrostatic IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 3, JUNE 2013 1011 High Area-Efficient ESD Clamp Circuit With Equivalent RC-Based Detection Mechanism in a 65-nm CMOS Process Chih-Ting Yeh, Student Member,

More information

Investigation of the Gate-Driven Effect and Substrate-Triggered Effect on ESD Robustness of CMOS Devices

Investigation of the Gate-Driven Effect and Substrate-Triggered Effect on ESD Robustness of CMOS Devices 190 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 1, NO. 4, DECEMBER 2002 Investigation of the Gate-Driven Effect and Substrate-Triggered Effect on ESD Robustness of CMOS Devices Tung-Yang

More information

Conference paper Latch-up immune ESD Protection Clamp for High Voltage optimized on TSMC BCD technology

Conference paper Latch-up immune ESD Protection Clamp for High Voltage optimized on TSMC BCD technology Conference paper Latch-up immune ESD Protection Clamp for High Voltage optimized on TSMC BCD technology TSMC Open Innovation Platform 2011 Applications like motor control, power management and conversion,

More information

CMOS Design Lab Manual

CMOS Design Lab Manual CMOS Design Lab Manual Developed By University Program Team CoreEl Technologies (I) Pvt. Ltd. 1 Objective Objective of this lab is to learn the Mentor Graphics HEP2 tools as well learn the flow of the

More information

Ethernet Protection A Whole Solution Han Zou, ProTek Devices

Ethernet Protection A Whole Solution Han Zou, ProTek Devices Ethernet Protection ------ A Whole Solution Han Zou, ProTek Devices Introduction: As Ethernet applications progress from 10BaseT to 10Gigabit and beyond, IC components are becoming more complicated with

More information

HIPEX Full-Chip Parasitic Extraction. Summer 2004 Status

HIPEX Full-Chip Parasitic Extraction. Summer 2004 Status HIPEX Full-Chip Parasitic Extraction Summer 2004 Status What is HIPEX? HIPEX Full-Chip Parasitic Extraction products perform 3D-accurate and 2D-fast extraction of parasitic capacitors and resistors from

More information

HSP series portfolio overview. High-speed port ESD protection

HSP series portfolio overview. High-speed port ESD protection HSP series portfolio overview High-speed port ESD protection Is this presentation suited for you? 2 Where do you stand with high-speed port protection? Beginner? I am not familiar with this subject. I

More information

Hipex Full-Chip Parasitic Extraction

Hipex Full-Chip Parasitic Extraction What is Hipex? products perform 3D-accurate and 2D-fast extraction of parasitic capacitors and resistors from hierarchical layouts into hierarchical transistor-level netlists using nanometer process technology

More information

RClamp TM 0504M RailClamp Low Capacitance TVS Diode Array PRELIMINARY Features

RClamp TM 0504M RailClamp Low Capacitance TVS Diode Array PRELIMINARY Features Description RailClamps are surge rated diode arrays designed to protect high speed data interfaces. The RClamp series has been specifically designed to protect sensitive components which are connected

More information

AOZ8900. Ultra-Low Capacitance TVS Diode Array PRELIMINARY. Features. General Description. Applications. Typical Application

AOZ8900. Ultra-Low Capacitance TVS Diode Array PRELIMINARY. Features. General Description. Applications. Typical Application Ultra-Low Capacitance TS Diode Array General Description The is a transient voltage suppressor array designed to protect high speed data lines from Electro Static Discharge (ESD) and lightning. This device

More information

Case study of Mixed Signal Design Flow

Case study of Mixed Signal Design Flow IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 3, Ver. II (May. -Jun. 2016), PP 49-53 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Case study of Mixed Signal Design

More information

Investigation on seal-ring rules for IC product reliability in m CMOS technology

Investigation on seal-ring rules for IC product reliability in m CMOS technology Microelectronics Reliability 45 (2005) 1311 1316 www.elsevier.com/locate/microrel Investigation on seal-ring rules for IC product reliability in 0.25- m CMOS technology Shih-Hung Chen a * and Ming-Dou

More information

Single Channel Protector in a SOT-23 Package and a MSOP Package ADG465

Single Channel Protector in a SOT-23 Package and a MSOP Package ADG465 Data Sheet Single Channel Protector in a SOT-23 Package and a MSOP Package FEATURES Fault and overvoltage protection up to ±40 V Signal paths open circuit with power off Signal path resistance of RON with

More information

WITH the decrease of the power supply voltage for

WITH the decrease of the power supply voltage for IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 1, MARCH 2009 49 Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes Ming-Dou Ker, Fellow, IEEE, and

More information

PAPER MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process

PAPER MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process IEICE TRANS. ELECTRON., VOL.E88 C, NO.3 MARCH 2005 429 PAPER MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process Ming-Dou KER a), Kun-Hsien LIN, and Che-Hao CHUANG, Nonmembers

More information

Additional Slides for Lecture 17. EE 271 Lecture 17

Additional Slides for Lecture 17. EE 271 Lecture 17 Additional Slides for Lecture 17 Advantages/Disadvantages of Wire Bonding Pros Cost: cheapest packages use wire bonding Allows ready access to front side of die for probing Cons Relatively high inductance

More information

Conference paper ESD Design Challenges in nano-cmos SoC Design

Conference paper ESD Design Challenges in nano-cmos SoC Design Conference paper ESD Design Challenges in nano-cmos SoC Design SoC conference 2008 The Silicon Controlled Rectifier ( SCR ) is widely used for ESD protection due to its superior performance and clamping

More information

Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp

Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp . BRIEF REPORT. SCIENCE CHINA Information Sciences February 2014, Vol. 57 029401:1 029401:6 doi: 10.1007/s11432-013-5016-1 Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power

More information

Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-µm silicide CMOS technology

Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-µm silicide CMOS technology Vol. 30, No. 8 Journal of Semiconductors August 2009 Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-µm silicide CMOS technology Jiang Yuxi(ñŒD), Li Jiao(o),

More information

Comprehensive Place-and-Route Platform Olympus-SoC

Comprehensive Place-and-Route Platform Olympus-SoC Comprehensive Place-and-Route Platform Olympus-SoC Digital IC Design D A T A S H E E T BENEFITS: Olympus-SoC is a comprehensive netlist-to-gdsii physical design implementation platform. Solving Advanced

More information

Stacked IC Analysis Modeling for Power Noise Impact

Stacked IC Analysis Modeling for Power Noise Impact Si2 Open3D Kick-off Meeting June 7, 2011 Stacked IC Analysis Modeling for Power Noise Impact Aveek Sarkar Vice President Product Engineering & Support Stacked IC Design Needs Implementation Electrical-,

More information

Optimization of Broadband RF Performance and ESD Robustness by π-model Distributed ESD Protection Scheme

Optimization of Broadband RF Performance and ESD Robustness by π-model Distributed ESD Protection Scheme Optimization of Broadband RF Performance and ESD Robustness by π-model Distributed ESD Protection Scheme Ming-Dou Ker and Bing-Jye Kuo Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics,

More information

(12) Patent Application Publication (10) Pub. No.: US 2012/ A1

(12) Patent Application Publication (10) Pub. No.: US 2012/ A1 US 20120162831A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2012/0162831 A1 Wang et al. (43) Pub. Date: Jun. 28, 2012 (54) ESD PROTECTION CIRCUIT FOR (22) Filed: Dec. 26,

More information

FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT

FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT DIC1: Schematic Design Entry, Simulation & Verification DIC2: Schematic Driven Layout Drawing (SDL) Design Rule Check (DRC)

More information

Addressable Test Chip Technology for IC Design and Manufacturing. Dr. David Ouyang CEO, Semitronix Corporation Professor, Zhejiang University 2014/03

Addressable Test Chip Technology for IC Design and Manufacturing. Dr. David Ouyang CEO, Semitronix Corporation Professor, Zhejiang University 2014/03 Addressable Test Chip Technology for IC Design and Manufacturing Dr. David Ouyang CEO, Semitronix Corporation Professor, Zhejiang University 2014/03 IC Design & Manufacturing Trends Both logic and memory

More information

Design rule illustrations for the AMI C5N process can be found at:

Design rule illustrations for the AMI C5N process can be found at: Cadence Tutorial B: Layout, DRC, Extraction, and LVS Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Revised by C Young & Waqar A Qureshi -FS08 Document Contents Introduction

More information

Latchup Test-Induced Failure within ESD Protection Diodes in a High-Voltage CMOS IC Product

Latchup Test-Induced Failure within ESD Protection Diodes in a High-Voltage CMOS IC Product Latchup Test-Induced Failure within ESD Protection Diodes in a High-Voltage CMOS IC Product I-Cheng Lin (1), Chuan-Jane Chao (1), Ming-Dou Ker (2), Jen-Chou Tseng (1), Chung-Ti Hsu (1), Len-Yi Leu (1),

More information

SCR Device With Double-Triggered Technique for On-Chip ESD Protection in Sub-Quarter-Micron Silicided CMOS Processes

SCR Device With Double-Triggered Technique for On-Chip ESD Protection in Sub-Quarter-Micron Silicided CMOS Processes 58 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 3, NO. 3, SEPTEMBER 2003 SCR Device With Double-Triggered Technique for On-Chip ESD Protection in Sub-Quarter-Micron Silicided CMOS Processes

More information

On-Chip Electro-Static Discharge (ESD) Protection For Radio-Frequency Integrated Circuits

On-Chip Electro-Static Discharge (ESD) Protection For Radio-Frequency Integrated Circuits On-Chip Electro-Static Discharge (ESD) Protection For Radio-Frequency Integrated Circuits Qiang Cui Juin J. Liou Jean-Jacques Hajjar Javier Salcedo Yuanzhong Zhou Srivatsan Parthasarathy On-Chip Electro-Static

More information

SFC ChipClamp ΤΜ Flip Chip TVS Diode with T-Filter PRELIMINARY Features

SFC ChipClamp ΤΜ Flip Chip TVS Diode with T-Filter PRELIMINARY Features Description The SFC2282-50 is a low pass T-filter with integrated TVS diodes. It is designed to provide bidirectional filtering of EMI/RFI signals and electrostatic discharge (ESD) protection in portable

More information

Microelectronics Reliability 47 (2007) Introductory Invited Paper

Microelectronics Reliability 47 (2007) Introductory Invited Paper Microelectronics Reliability 47 (2007) 27 35 Introductory Invited Paper Overview on ESD protection design for mixed-voltage interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage

More information

VLSI Test Technology and Reliability (ET4076)

VLSI Test Technology and Reliability (ET4076) VLSI Test Technology and Reliability (ET4076) Lecture 8(2) I DDQ Current Testing (Chapter 13) Said Hamdioui Computer Engineering Lab Delft University of Technology 2009-2010 1 Learning aims Describe the

More information

Digital Integrated Circuits (83-313) Lecture 2: Technology and Standard Cell Layout

Digital Integrated Circuits (83-313) Lecture 2: Technology and Standard Cell Layout Digital Integrated Circuits (83-313) Lecture 2: Technology and Standard Cell Layout Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 26 March 2017 Disclaimer: This course

More information

AS ultra-large-scale-integrated (ULSI) circuits are being

AS ultra-large-scale-integrated (ULSI) circuits are being IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 3, SEPTEMBER 2008 549 Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD

More information

Transient Latch-up in Large NFET Switch Arrays. Nathaniel Peachey, RFMD, Inc. Rick Phelps, IBM, Inc.

Transient Latch-up in Large NFET Switch Arrays. Nathaniel Peachey, RFMD, Inc. Rick Phelps, IBM, Inc. Transient Latch-up in Large NFET Switch Arrays Nathaniel Peachey, RFMD, Inc. Rick Phelps, IBM, Inc. Biography Nathaniel (Nate) Peachey received his Ph.D. in Physical Chemistry in 1994 from the University

More information

AOZ8101. Ultra-Low Capacitance TVS Diode Array. General Description. Features. Applications. Typical Application

AOZ8101. Ultra-Low Capacitance TVS Diode Array. General Description. Features. Applications. Typical Application Ultra-Low Capacitance TS Diode Array General Description The AOZ8101 is a transient voltage suppressor array designed to protect high speed data lines from Electro Static Discharge (ESD) and lightning.

More information

Substrate-Triggered Technique for On-Chip ESD Protection Design in a 0.18-m Salicided CMOS Process

Substrate-Triggered Technique for On-Chip ESD Protection Design in a 0.18-m Salicided CMOS Process 1050 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, APRIL 2003 Substrate-Triggered Technique for On-Chip ESD Protection Design in a 0.18-m Salicided CMOS Process Ming-Dou Ker, Senior Member, IEEE,

More information

ELECTROSTATIC (ESD) has been an important reliability

ELECTROSTATIC (ESD) has been an important reliability IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 53, NO. 10, OCTOBER 2006 2187 Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices

More information

Conference paper ESD Protection Solutions for High Voltage Technologies

Conference paper ESD Protection Solutions for High Voltage Technologies Conference paper ESD Protection Solutions for High Voltage Technologies EOS/ESD symposium 4 There is a trend to revive mature technologies while including high voltage options. ESD protection in those

More information

IO & ESD protection 1.8V & 3.3V capable general purpose digital IO pad based on 1.8V devices for TSMC 28nm CMOS technology

IO & ESD protection 1.8V & 3.3V capable general purpose digital IO pad based on 1.8V devices for TSMC 28nm CMOS technology Data sheet IO & ESD protection 1.8V & 3.3V capable general purpose digital IO pad based on 1.8V devices for TSMC 28nm CMOS technology Sofics has verified its TakeCharge ESD protection clamps on TSMC 28nm

More information

8D-3. Experiences of Low Power Design Implementation and Verification. Shi-Hao Chen. Jiing-Yuan Lin

8D-3. Experiences of Low Power Design Implementation and Verification. Shi-Hao Chen. Jiing-Yuan Lin Experiences of Low Power Design Implementation and Verification Shi-Hao Chen Global Unichip Corp. Hsin-Chu Science Park, Hsin-Chu, Taiwan 300 +886-3-564-6600 hockchen@globalunichip.com Jiing-Yuan Lin Global

More information

ELECTROSTATIC discharge (ESD) phenomenon continues

ELECTROSTATIC discharge (ESD) phenomenon continues IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 27, NO. 3, SEPTEMBER 2004 445 ESD Protection Design to Overcome Internal Damage on Interface Circuits of a CMOS IC With Multiple Separated

More information

Low-Power Technology for Image-Processing LSIs

Low-Power Technology for Image-Processing LSIs Low- Technology for Image-Processing LSIs Yoshimi Asada The conventional LSI design assumed power would be supplied uniformly to all parts of an LSI. For a design with multiple supply voltages and a power

More information

RClamp0524PA RClamp0522P

RClamp0524PA RClamp0522P PROTECTION PRODUCTS - RailClamp Description RailClamp TVS arrays are ultra low capacitance ESD protection devices designed to protect high speed data interfaces. This series has been specifically designed

More information

WE05R. Features. Transient Voltage Suppressor IEC COMPATIBILITY (EN ) SOT-143 (Top View) Document: W , Rev: A

WE05R. Features. Transient Voltage Suppressor IEC COMPATIBILITY (EN ) SOT-143 (Top View) Document: W , Rev: A Document: W0005, Rev: A Transient Voltage Suppressor Features 00Watts Peak Power per Line (tp = 8/0μs) Protects two I/O lines Low operating voltage: 5V Ultra Low capacitance(

More information

ESD Protection Device and Circuit Design for Advanced CMOS Technologies

ESD Protection Device and Circuit Design for Advanced CMOS Technologies ESD Protection Device and Circuit Design for Advanced CMOS Technologies Oleg Semenov Hossein Sarbishaei Manoj Sachdev ESD Protection Device and Circuit Design for Advanced CMOS Technologies Authors: Oleg

More information

ECE260B CSE241A Winter Tapeout. Website:

ECE260B CSE241A Winter Tapeout. Website: ECE260B CSE241A Winter 2007 Tapeout Website: http://vlsicad.ucsd.edu/courses/ece260b-w07 ECE 260B CSE 241A Tapeout 1 Tapeout definition What is the definition of the tapeout? There is no standard definition

More information

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 8, AUGUST Ming-Dou Ker, Senior Member, IEEE, and Kun-Hsien Lin, Member, IEEE,

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 8, AUGUST Ming-Dou Ker, Senior Member, IEEE, and Kun-Hsien Lin, Member, IEEE, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 8, AUGUST 2005 1751 The Impact of Low-Holding-Voltage Issue in High-Voltage CMOS Technology and the Design of Latchup-Free Power-Rail ESD Clamp Circuit

More information

RClamp0522P RClamp0524P

RClamp0522P RClamp0524P PROTECTION PRODUCTS - RailClamp Description RailClamps are ultra low capacitance TVS arrays designed to protect high speed data interfaces. This series has been specifically designed to protect sensitive

More information

TO IMPROVE circuit operating speed and performance,

TO IMPROVE circuit operating speed and performance, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 53, NO. 2, FEBRUARY 2006 235 Overview on Electrostatic Discharge Protection Designs for Mixed-Voltage I/O Interfaces: Design Concept and

More information

ELECTROSTATIC discharge (ESD) is a transient process

ELECTROSTATIC discharge (ESD) is a transient process 320 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 2, MAY 2005 SCR Device Fabricated With Dummy-Gate Structure to Improve Turn-On Speed for Effective ESD Protection in CMOS Technology Ming-Dou

More information

A Novel Methodology to Debug Leakage Power Issues in Silicon- A Mobile SoC Ramp Production Case Study

A Novel Methodology to Debug Leakage Power Issues in Silicon- A Mobile SoC Ramp Production Case Study A Novel Methodology to Debug Leakage Power Issues in Silicon- A Mobile SoC Ramp Production Case Study Ravi Arora Co-Founder & CTO, Graphene Semiconductors India Pvt Ltd, India ABSTRACT: As the world is

More information

Design Compiler Graphical Create a Better Starting Point for Faster Physical Implementation

Design Compiler Graphical Create a Better Starting Point for Faster Physical Implementation Datasheet Create a Better Starting Point for Faster Physical Implementation Overview Continuing the trend of delivering innovative synthesis technology, Design Compiler Graphical streamlines the flow for

More information

WITH the migration toward shallower junctions, much

WITH the migration toward shallower junctions, much 328 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 2, MAY 2005 ESD Implantations for On-Chip ESD Protection With Layout Consideration in 0.18-m Salicided CMOS Technology Ming-Dou Ker, Senior

More information

WITH THE continuously scaled-down CMOS technology,

WITH THE continuously scaled-down CMOS technology, 2626 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 10, OCTOBER 2012 Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology Chih-Ting

More information

Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD Protection Arrays for High-Speed Data Interfaces

Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD Protection Arrays for High-Speed Data Interfaces 9-739; Rev 5; 6/ General Description The are low-capacitance ±5kV ESD-protection diode arrays designed to protect sensitive electronics attached to communication lines. Each channel consists of a pair

More information

RClamp3324P. Low Capacitance RailClamp 4-Line Surge and ESD Protection. PROTECTION PRODUCTS Description. Features. Mechanical Characteristics

RClamp3324P. Low Capacitance RailClamp 4-Line Surge and ESD Protection. PROTECTION PRODUCTS Description. Features. Mechanical Characteristics Low Capacitance RailClamp 4-Line Surge and ESD Protection PROTECTION PRODUCTS Description RailClamp provides ESD protection for highspeed data interfaces. It features a high maximum ESD withstand voltage

More information

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices Microelectronics Journal 37 (2006) 526 533 www.elsevier.com/locate/mejo Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices O. Semenov a, *, H. Sarbishaei a, V. Axelrad

More information

Design optimization of ESD protection and latchup prevention for a serial I/O IC

Design optimization of ESD protection and latchup prevention for a serial I/O IC Microelectronics Reliability 44 (2004) 213 221 www.elsevier.com/locate/microrel Design optimization of ESD protection and latchup prevention for a serial I/O IC Chih-Yao Huang a, *, Wei-Fang Chen b, Song-Yu

More information