Comprehensive Layout-based ESD Check Methodology with Fast Full-chip Static and Macro-level Dynamic Solutions
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1 Comprehensive Layout-based ESD Check Methodology with Fast Full-chip Static and Macro-level Dynamic Solutions Norman Chang, Ting-Sheng Ku, Jai Pollayil 26 th International Conference on VLSI January 2013 Pune, India
2 Agenda ESD Overview Verification Solutions Static verification on HBM/MM/CDM and test cases Block/IP-level dynamic ESD analysis and HBM/CDM test cases Summary 1/11/2013 2
3 1/11/ Worsening Trend in ESD Thinner oxide and lower junction thermal breakdown voltages Reduced failure current density limit Worsening CDM issue for high-frequency designs White Paper 2: A case for lowering component level CDM ESD specifications and requirements, April, 2010
4 ESD Models 1/11/2013 4
5 1/11/ Full-chip ESD Protection Methodology Protection Circuit Requirement Consider full permutation Timely and uniform turn-on Low impedance path for discharging No impact on normal operation Protection Coverage Regular I/O Intra-domain Multi-domain High-speed I/O
6 Mapping ESD Verification Flow to IC Design Flow [3] 1/11/ IC design flow needs to be synchronized with ESD development, implementation, and check
7 Agenda ESD Overview Verification Solutions Static verification on HBM/MM/CDM and test cases Block/IP level dynamic ESD analysis and HBM/CDM test cases Summary 1/11/2013 7
8 1/11/ Requirements for Fast Full-chip Static and Macro-level Dynamic Solutions Fast full-chip layout-based checks High-capacity and accurate metal/via resistance extraction Inter- and intra-domain resistance checks Realistic I-V model (snapback included) for diode/clamp in R and current density checks Current density and voltage check, particularly critical for IP Full-chip ESD check required for identifying problems such as inter-block connectivity related Macro-level dynamic ESD solution Transistor-level stress analysis for 1M+ transistor blocks within couple of days Consider substrate effect, clamp modeling with snapback, metal grid RLC, and pogo pin modeling
9 1/11/ Analysis Coverage for SoC ESD Integrity Verification Pad / Clamp Layout Connectivity Wire / Via Current Density Signal to Power(S2P) Ground to Signal(G2S) Power to Ground(P2G) Current Density Violation Map Domain Crossing Checks Signal to Ground (S2G) D1-D4 to Power Clamp D5-D6 to Power Clamp Current density violations Routing congestion, narrow wires Voltage check on all the P/G/S nodes
10 1/11/ Resistance Check Between Gates/Macros to Clamps Sample a subset of cells based on their minimum R path to respective nearby clamps Calculate the smallest loop R from power/ground nodes of the sampled gates Calculate the smallest arc R from the sampled pins of a macro to respective nearby clamps
11 1/11/ Current Density Check Model diode/clamp with I-V curve including snapback characteristics Automatically determines the on/off clamp in the discharging paths on off For disjoint discharging paths, parallel threads used to achieve fast, full-chip run Check current density of wires/vias
12 1/11/ Early ESD Planning Optimize the need and placement of ESD cells early in the design flow Easily insert and/or modify ESD cells, preferably using GUI
13 Full-chip ESD Verification Flow 1/11/
14 1/11/ Full-chip ESD Verification Example Large SoC with ~40M instances 20 power/ground domains 600 signal domains 2000 C4 bumps and 400 package pins Perform HBM on all power/ground/signal domains Perform CDM on sampled instances
15 Run Time and Memory Statistics 1/11/
16 1/11/ Nvidia Examples on Detection of HBM Issues with Static Solution
17 1/11/ Static ESD Check Flow at Nvidia Static Resistance and Current Density Check Apache s PathFinder performed full-chip resistance and current density (CD) checks between diodes and clamps, and also between bumps and clamps Goal is to identify and fix any resistance and current density larger than design target values before tape-out
18 1/11/ Resistance Check Statistics PathFinder took 5.5 hours for fullchip static resistance analysis Calculated resistance between clamp-diode pairs within 2000um moving radius constraint Calculated 826 bump to clamp resistance within 2000um moving radius constraint
19 Nvidia Example #1 HBM Check USB Interface Block in Full-Chip Analysis Detected in pre-tape-out check, saved a metal spin PathFinder calculated effective 2.68 ohm resistance between diode and clamp in USB cell Shortest Resistance Path (SPT) tracing performed to identify the larger than expected resistance paths SPT analysis 1/11/
20 1/11/ Nvidia Example #2 HBM Check HDMI Block in Full-Chip Analysis PathFinder calculated 3.35 ohm resistance between diode and clamp in HDMI cell Highlighted shortest resistance path clearly identified problems buried deep in layout Detected insufficient top-level power connection before tape-out
21 1/11/ Nvidia Example #3 CD Check High Current Density Issue in I/O Area High current density observed from D5->VSS->D2 Current Density Map i Electro-migration Map
22 1/11/ Other Examples on Detection of HBM Issues with Static Solution
23 1/11/ Case Study: ESD Analysis for Analog Chip Very high resistance between I/O bump to clamp causing SI failure on chip, detected by transistor-level static ESD Analysis IO BUMP ESD Analysis GND BUMP CLAMP
24 1/11/ Debugging Shortest Resistance Path on Analog Chip Shortest resistance path through wires/vias can be highlighted and shown on a table
25 Current Density Checks Example Comprehensive verification of all the ESD discharge paths Place core clamps here Routing congestion, narrow wires Identify current crowding in diode/clamp fingers Instance-level differential voltage check for guiding core clamp placement Differential voltage check between driver/receiver pair 1/11/
26 1/11/ Large R Problem Highlighted Between Instance and Clamp (CDM Failure) Long M3 connection (~250um) and stack via (connecting M3 to M1 through M4) causing high VDD ARC resistance
27 Agenda ESD Overview Verification Solutions Static verification on HBM/MM/CDM and test cases Block/IP-level dynamic ESD analysis and HBM/CDM test cases Summary 1/11/
28 1/11/ ESD Dynamic Methodology Perform diagnosis of potential failure mechanisms when silicon failures occur Verify robustness of the fix by comparing differential stressed values of the failed junctions Check potential design weaknesses of CDM events before tape-out on analog / mixed-signal / I/O blocks
29 Target Applications for Dynamic ESD Analysis Target Users: Initially ESD experts Eventually mixed-signal macros designers Transistor Count: ~1M per macro Dynamic ESD check coverage beyond static ESD check Model physically correct CDM discharging behavior Explicitly detect worst transient voltage stressed junctions Evaluate clamp transient effectiveness related to design and placement Perform trade-off on peak vs. duration device failure mode 1/11/
30 Cross-domain CDM Example: Cross-domain Check and Possible Failure Mechanism for PLL + VDD1 VDD2 Power Clamp 1 Vgs Power Clamp 1 VSS1 VSS2 Rbus GND Possible Vgs junction failure due to disparate discharging rate from gate and source nodes to CDM grounded pin 1/11/
31 1/11/ Core Technology Requirements Electrical modeling Substrate RC and well diode extraction Snapback behavior model for ESD clamps P/G RCL extraction Specialized ESD simulation engine Handling of the non-convergence behavior for ESD circuits High performance and large capacity for post-layout designs Layout-based debugging GUI Cross probing between netlist, layout, and voltage waveforms
32 1/11/ Substrate Model for Dynamic ESD Extract substrate well diodes and RC grid GND R mesh VDD R mesh P+ N+ N+ P+ P+ N+ P-well N_well P-substrate
33 1/11/ Block-based ESD Dynamic Flow Import DSPF (Detailed Standard Parasitic Format) of coupled signal RC netlist and create P/G contact pins Extract metal grid RLC, substrate RC, and well diodes Hook up the two netlist above through contact pins and create test bench for HBM or CDM zapping condition Perform the simulation on the final netlist above and generate junction stress report
34 1/11/ Nvidia Examples on Detection of HBM/CDM Issues with Dynamic Solution
35 HBM Case Comparison: Grounded vs. Floating P-well Guard Ring in RC-based Clamp Both test cases with AGND -2000V HBM zap and AVDD grounded Grounded P-well guard ring case failed, while floating P-well guard ring case passed AVDD AVDD sig Pwell guard ring grounded _ sig Pwell guard ring floating _ AGND AGND Failed clamp Passed clamp 1/11/
36 1/11/ Snapshot of HBM Failure Case AVDD sig P-well guard ring grounded _ AGND Failed clamp Lab de-processed result of failed HBM test on I/O with grounded P-well guard ring
37 1/11/ HBM Test Case Device count : 12K subckt (xmos), 6K Diodes Extracted elements: 5.79M RLCs Simulation Conditions: Initialized at -2000V (HBM test) Zap Init at -2000V 3.0u 1525ohm AGND VDD 100pf 0.1f P/G RLC AVDD Macro Block w/ coupled signal RC GND HBM Analysis Setup: 48min Simulation: 2hr Peak memory use: 15GB Substrate RC w/ Well diode
38 Melt-down of Center Finger of RC-based Clamp Due to Parasitic BJT Turn-on (HBM Failure) Center finger furthest from grounded Pwell guard ring result in largest resistance from the AGND zap point Vbs of finger higher due to substrate node distance from Pwell guard ring Higher Vbs of center finger with higher Ids current may turn on parasitic bipolar earlier than other fingers, causing center finger melt down AGND X AVDD Center Finger of RC-based Clamp 1/11/
39 D/G/S/B Node Waveforms of RC-based Clamp Fingers with Grounded Substrate Pwell Guard Ring 1.37ns Vg Vb of different fingers w/ the center finger having largest Vbs Vd Vs Vbs of different clamp fingers have varying amplitude, with center finger having largest Vbs causing non-uniform turn-on of the center finger and triggering its parasitic BJT 1/11/
40 D/G/S/B Node Waveforms of RC-based Clamp Fingers with Substrate Floating Pwell Guard Ring 1.37ns Vg Vd Vb of different fingers Vs Vbs of different clamp fingers have similar amplitude, resulting in uniform turn-on among all fingers 1/11/
41 1/11/ Worst Stress Movie for HBM AGND -2000V Zap with Hot Spot on Center Finger of RC-based Clamp Hot spot at 1.37nsec of the HBM zap at the center finger of RC-based clamp
42 1/11/ Example CDM Test Case Device count : 62,256 subckt (xmos), 541 Diodes Extracted elements: 3,709,648 RLCs Simulation Conditions: Initialized at -500V (ESD class choice) Zap Lpogo Rpogo Cpogo IOP ION P/G RLC VDD VDDP Macro Block w/ coupled signal RC GND CDM Analysis Setup: 1hr Simulation: 2hr Peak Memory Use: 25 GB Substrate RC w/ well diode Cdut of 3pF evenly distributed among substrate Tuned substrate_to_gnd_cap to match expected pogo pin peak current
43 1/11/ CDM Issue Due to Discharging Paths Race Condition Worst Junction Worst junction voltage waveform Pogo pin current waveform Impedance mismatch between I/O (sig) and LDO bias net caused large Vgd junction stress on -500V zap LDO bias net heavily referenced to ground due to large capacitance
44 Stress Movie on CDM Test Case: IOP Zap at -500V -500V Zap at I/O Pin Highest stress occurred at failed junction (Vgd) on the top around 137psec; the 2 nd ranked stressed junction with similar design issue, except the I/O transistor size is much larger 1/11/
45 1/11/ Failure Emission Image for CDM Test Case emission site Lab emission result of failed CDM test on high-speed I/O
46 1/11/ PMOS Passgate Insertion as Proposed Fix for Failed Junction Stress Reduction PMOS passgate PMOS passgate inserted Worst junction voltage waveform PMOS passgate inserted at the gate of the failed NMOS isolates the junction from bias net loading, allowing the junction voltage delta to stay within device tolerance
47 1/11/ PathFinder: SoC and IP ESD Integrity DEF / GDS Technology Spice Netlist/ Clamp Models ESD rules Connectivity Rule based Checks Dynamic Checks Isolated bumps Inter domain clamp checks Resistance Checks Current Density/ IR checks Device stress voltage checks Current discharge waveforms Layout based Flexible check Interactive fixing Early ESD Planning I/O / IP level checks SoC level checks Package Support
48 1/11/ Summary With tighter design margin in 45/28/20/14nm technology nodes, ESD verification is a must for SoC, mixed-signal, and custom designs Static ESD methodology required for sign-off check on large SoC and mixed-signal chips Passing CDM at standard voltage is getting more difficult for high-speed I/O, mixed-signal designs Dynamic ESD methodology required for the diagnosis and predictive simulation of HBM/CDM events
49 1/11/ References [1] N. Chang, Y. Liao, Y. Li, P. Johari, A. Sarkar, Efficient Multi-domain ESD Analysis and Verification for Large SoC Designs, ESD/EOS Symposium, [2] Ting-Sheng Ku, Jau-Wen Chen, George Kokai, Norman Chang, Shen Lin, Yu Liu, Ying-Shiun Li, Bo Hu, ESD Dynamic Methodology for Diagnosis and Predictive Simulation of HBM/CDM Events, ESD/EOS Symposium, [3] Michael Khazhinsky, Victor Cao, Harald Gossner, Gianluca Boselli, Melanie Etherton, Electronic Design Automation (EDA) Solutions for ESD-robust Design and Verification, CICC [4] ESDA Technical Report #TR , ESD Electronic Design Automation Checks, ESDA Committee, 2011.
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