III-V Heterojunction Tunnel FETs Joachim Knoch

Size: px
Start display at page:

Download "III-V Heterojunction Tunnel FETs Joachim Knoch"

Transcription

1 III-V Heterojunction Tunnel FETs Joachim Knoch Micro- and Nanoelectronics Devices Group Micro and Nanoelectronics Devices Group TU Dortmund University, Dortmund, Germany

2 Introduction - TFETs Operation Principle getting rid of f(e) getting rid of k B T J. Knoch, S. Mantl and J. Appenzeller, Solid-State Electron., 51, 572 (2007). J. Appenzeller, Y.-M. Lin, J. Knoch, Z. Chen and Ph. Avouris, IEEE Trans. Electron Dev. 52, 2568 (2005).

3 Introduction - TFETs Operation Principle exponential increase of I d since thinning of tunneling barrier is dominant

4 Introduction - TFETs Operation Principle point slope exponential increase of I d since thinning of tunneling barrier is dominant average slope

5 Introduction - TFETs Operation Principle band-pass filter behavior effective cooling of f(e) J. Knoch, S. Mantl and J. Appenzeller, Solid-State Electron., 51, 572 (2007).

6 Introduction - TFETs Operation Principle band-pass filter behavior effective cooling of f(e) J. Knoch, S. Mantl and J. Appenzeller, Solid-State Electron., 51, 572 (2007).

7 type II heterointerface leads to broken/staggered band alignment e.g. in InAs / Al x Ga 1-x Sb steepest possible p-n junction vertical device structure with heterointerface at nanowire / substrate interface J. Knoch, Proc Internat. Symp. VLSI-TSA, 45 (2009).

8 large source doping concentration yields high on-state current due to screening of the gate fringing fields inverse subthreshold slope always 60mV/dec in case of high source doping J. Knoch, Proc Internat. Symp. VLSI-TSA, 45 (2009). J. Knoch and J. Appenzeller, IEEE EDL, 31, 305 (2010).

9 Injecting Contact high doping level needed to screen gate impact but: large E f yields S 60mV/dec J. Appenzeller, J. Knoch, M.T. Bjoerk, H, Schmid, H. Riel and W. Riess, IEEE Trans. Electron Dev., 55, 2827 (2008).

10 Injecting Contact particularly important in III-V semiconductors with low DOS Sdegradeswith decreasing dop

11 Injecting Contact particularly important in III-V semiconductors with low DOS S degrades with decreasing dop smaller impact due to fringing is advantagous

12 Staggered versus Broken significant density of states in potential notch and inelastic scattering yield S=60mV/dec in broken case J. Knoch and J. Appenzeller, IEEE EDL, 31, 305 (2010).

13 Staggered versus Broken S=60mV/dec in the case of broken band gap optimum S=33mV/dec with staggered band line-up close to broken case and moderate doping J. Knoch and J. Appenzeller, IEEE EDL, 31, 305 (2010).

14 Staggered versus Broken S=60mV/dec in the case of broken band gap optimum S=33mV/dec with staggered band line-up close to broken case and moderate doping highest on/off-ratio at combination with steepest slope J. Knoch and J. Appenzeller, IEEE EDL, 31, 305 (2010).

15 Staggered versus Broken S=60mV/dec in the case of broken band gap optimum S=33mV/dec with staggered band line-up close to broken case and moderate doping highest on/off-ratio at combination with steepest slope for optimized device very high intrinsic performance possible J. Knoch and J. Appenzeller, IEEE EDL, 31, 305 (2010).

16 Conclusion III-V heterojunction ti TFETs allow high h on-state t performance and steep S low density of states in source requires tradeoff between high on-state and steep inverse subthreshold slope staggered band line-up yields better on/off- performance than broken case

Peering into Moore s

Peering into Moore s Peering into Moore s Crystal Ball: Transistor Scaling beyond the 15nm node Kelin J. Kuhn Intel Fellow Director of Advanced Device Technology Portland Technology Development Intel Corporation Kelin Kuhn

More information

Scanning Capacitance Microscopy Investigations of Focused Ion Beam Damage in Silicon

Scanning Capacitance Microscopy Investigations of Focused Ion Beam Damage in Silicon Scanning Capacitance Microscopy Investigations of Focused Ion Beam Damage in Silicon W. Brezna, H. Wanzenböck, A. Lugstein, E. Bertagnolli, E. Gornik, J. Smoliner Institute for Solid State Electronics,

More information

FinFETs: Quo Vadis? Niraj K. Jha Dept. of Electrical Engineering Princeton University

FinFETs: Quo Vadis? Niraj K. Jha Dept. of Electrical Engineering Princeton University FinFETs: Quo Vadis? Niraj K. Jha Dept. of Electrical Engineering Princeton University Talk Outline Quo Vadis FinFET devices? Quo Vadis FinFET standard cells and logic circuits? Addressing the Power Wall

More information

CALCULATION OF POWER CONSUMPTION IN 7 TRANSISTOR SRAM CELL USING CADENCE TOOL

CALCULATION OF POWER CONSUMPTION IN 7 TRANSISTOR SRAM CELL USING CADENCE TOOL CALCULATION OF POWER CONSUMPTION IN 7 TRANSISTOR SRAM CELL USING CADENCE TOOL Shyam Akashe 1, Ankit Srivastava 2, Sanjay Sharma 3 1 Research Scholar, Deptt. of Electronics & Comm. Engg., Thapar Univ.,

More information

Post-Process Process CMOS Front End Engineering With Focused Ion Beams

Post-Process Process CMOS Front End Engineering With Focused Ion Beams Post-Process Process CMOS Front End Engineering With Focused Ion Beams A. Lugstein 1, W. Brezna 1, B. Goebel 2, L. Palmetshofer 3, and E. Bertagnolli 1 1) Vienna University of Technology, Floragasse 7,

More information

Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory

Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.2, APRIL, 2017 ISSN(Print) 1598-1657 https://doi.org/10.5573/jsts.2017.17.2.260 ISSN(Online) 2233-4866 Process Variation on Arch-structured Gate

More information

CMOS Scaling for the Next Decade and Emerging Technologies: SEMATECH Perspective. Accelerating the next technology revolution

CMOS Scaling for the Next Decade and Emerging Technologies: SEMATECH Perspective. Accelerating the next technology revolution US Korea NanoForum April 2009 Accelerating the next technology revolution CMOS Scaling for the Next Decade and Emerging Technologies: SEMATECH Perspective Prashant Majhi Front End Processes, SEMATECH Copyright

More information

Performance Enhancement under Power Constraints using Heterogeneous CMOS-TFET Multicores

Performance Enhancement under Power Constraints using Heterogeneous CMOS-TFET Multicores Performance Enhancement under Power Constraints using Heterogeneous CMOS-TFET Multicores Emre Kultursay, Karthik Swaminathan, Vinay Saripalli Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta The

More information

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Digital Integrated Circuits A Design Perspective Jan M. Rabaey Outline (approximate) Introduction and Motivation The VLSI Design Process Details of the MOS Transistor Device Fabrication Design Rules CMOS

More information

Beyond-CMOS Technology Roadmap. An Chen Emerging Research Devices (ERD), ITRS

Beyond-CMOS Technology Roadmap. An Chen Emerging Research Devices (ERD), ITRS Beyond-CMOS Technology Roadmap An Chen Emerging Research Devices (ERD), ITRS 2 For slides, questions, and comments, please contact me at: an.chen@globalfoundries.com Outline Introduction Emerging logic

More information

Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance

Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance Priyamvada Vijayakumar, Pritish

More information

Three DIMENSIONAL-CHIPS

Three DIMENSIONAL-CHIPS IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) ISSN: 2278-2834, ISBN: 2278-8735. Volume 3, Issue 4 (Sep-Oct. 2012), PP 22-27 Three DIMENSIONAL-CHIPS 1 Kumar.Keshamoni, 2 Mr. M. Harikrishna

More information

Chapter 2 On-Chip Protection Solution for Radio Frequency Integrated Circuits in Standard CMOS Process

Chapter 2 On-Chip Protection Solution for Radio Frequency Integrated Circuits in Standard CMOS Process Chapter 2 On-Chip Protection Solution for Radio Frequency Integrated Circuits in Standard CMOS Process 2.1 Introduction Standard CMOS technologies have been increasingly used in RF IC applications mainly

More information

ESD Protection Scheme for I/O Interface of CMOS IC Operating in the Power-Down Mode on System Board

ESD Protection Scheme for I/O Interface of CMOS IC Operating in the Power-Down Mode on System Board ESD Protection Scheme for I/O Interface of CMOS IC Operating in the Power-Down Mode on System Board Kun-Hsien Lin and Ming-Dou Ker Nanoelectronics and Gigascale Systems Laboratory Institute of Electronics,

More information

+ CS263: Runtime Systems

+ CS263: Runtime Systems + CS263: Runtime Systems Spring 2017 http://www.cs.ucsb.edu/~cs263 Prof. Chandra Krintz Laboratory for Research on Adaptive Computing Environments (RACELab) Computer Science Department Harold Frank Hall

More information

NAND Flash Memory: Basics, Key Scaling Challenges and Future Outlook. Pranav Kalavade Intel Corporation

NAND Flash Memory: Basics, Key Scaling Challenges and Future Outlook. Pranav Kalavade Intel Corporation NAND Flash Memory: Basics, Key Scaling Challenges and Future Outlook Pranav Kalavade Intel Corporation pranav.kalavade@intel.com October 2012 Outline Flash Memory Product Trends Flash Memory Device Primer

More information

Defect Inspection of Liquid-Crystal-Display (LCD) Panels in Repetitive Pattern Images Using 2D Fourier Image Reconstruction

Defect Inspection of Liquid-Crystal-Display (LCD) Panels in Repetitive Pattern Images Using 2D Fourier Image Reconstruction Defect Inspection of Liquid-Crystal-Display (LCD) Panels in Repetitive Pattern Images Using D Fourier Image Reconstruction Du-Ming Tsai, and Yan-Hsin Tseng Department of Industrial Engineering and Management

More information

Analog and Telecommunication Electronics

Analog and Telecommunication Electronics Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics F1 - Power devices: diodes» Switches» pn Junction» Diode models» Dynamic behavior» Zener diodes AY 2015-16 26/04/2016-1

More information

Automatic Device Design Optimization with TCAD Frameworks

Automatic Device Design Optimization with TCAD Frameworks Automatic Device Design Optimization with TCAD Frameworks M. Stockinger and S. Selberherr Institute for Microelectronics, TU Vienna Gusshausstrasse 27-29, A-040 Vienna, Austria, selberherr@tuwien.ac.at

More information

Investigation of the Gate-Driven Effect and Substrate-Triggered Effect on ESD Robustness of CMOS Devices

Investigation of the Gate-Driven Effect and Substrate-Triggered Effect on ESD Robustness of CMOS Devices 190 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 1, NO. 4, DECEMBER 2002 Investigation of the Gate-Driven Effect and Substrate-Triggered Effect on ESD Robustness of CMOS Devices Tung-Yang

More information

Analog and Telecommunication Electronics

Analog and Telecommunication Electronics Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics F2 Active power devices»mos»bjt» IGBT, TRIAC» Safe Operating Area» Thermal analysis AY 2015-16 26/04/2016-1

More information

A Step Ahead in Phase Change Memory Technology

A Step Ahead in Phase Change Memory Technology A Step Ahead in Phase Change Memory Technology Roberto Bez Process R&D Agrate Brianza (Milan), Italy 2010 Micron Technology, Inc. 1 Outline Non Volatile Memories Status The Phase Change Memories An Outlook

More information

Analog and Telecommunication Electronics

Analog and Telecommunication Electronics Politecnico di Torino - ICT School Analog and Telecommunication Electronics F2 Active power devices»mos»bjt» IGBT, TRIAC» Safe Operating Area» Thermal analysis 23/05/2014-1 ATLCE - F2-2014 DDC 2014 DDC

More information

AN EXAMINATION OF POST-CMOS COMPUTING TECHNIQUES USING STEEP SLOPE DEVICE-BASED ARCHITECTURES

AN EXAMINATION OF POST-CMOS COMPUTING TECHNIQUES USING STEEP SLOPE DEVICE-BASED ARCHITECTURES The Pennsylvania State University The Graduate School Department of Computer Science and Engineering AN EXAMINATION OF POST-CMOS COMPUTING TECHNIQUES USING STEEP SLOPE DEVICE-BASED ARCHITECTURES A Dissertation

More information

FLASH MEMORIES SPRINGER-SCIENCE+BUSINESS MEDIA, LLC. Paulo Cappelletti. Carla Golla. PieroOlivo. Enrico Zanoni

FLASH MEMORIES SPRINGER-SCIENCE+BUSINESS MEDIA, LLC. Paulo Cappelletti. Carla Golla. PieroOlivo. Enrico Zanoni FLASH MEMORIES FLASH MEMORIES By Paulo Cappelletti Carla Golla PieroOlivo Enrico Zanoni SPRINGER-SCIENCE+BUSINESS MEDIA, LLC Library of Congress Cataloging-in-Publication Data Flash memories 1 by Paulo

More information

General Purpose, Low Noise NPN Silicon Bipolar Transistor. Technical Data AT AT-41533

General Purpose, Low Noise NPN Silicon Bipolar Transistor. Technical Data AT AT-41533 General Purpose, Low Noise NPN Silicon Bipolar Transistor Technical Data AT-411 AT-433 Features General Purpose NPN Bipolar Transistor 9 MHz Performance: AT-411: 1 db NF,. db G A AT-433: 1 db NF, 14. db

More information

On the Defect Tolerance of Nano-scale Two-Dimensional Crossbars

On the Defect Tolerance of Nano-scale Two-Dimensional Crossbars On the Defect Tolerance of Nano-scale Two-Dimensional Crossbars Jing Huang, Mehdi B. Tahoori and Fabrizio Lombardi Dept of Electrical and Computer Engineering Northeastern niversity Boston, MA 02115 {hjing,mtahoori,lombardi}@ece.neu.edu

More information

6T- SRAM for Low Power Consumption. Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1

6T- SRAM for Low Power Consumption. Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1 6T- SRAM for Low Power Consumption Mrs. J.N.Ingole 1, Ms.P.A.Mirge 2 Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1 PG Student [Digital Electronics], Dept. of ExTC, PRMIT&R,

More information

Code Compression for RISC Processors with Variable Length Instruction Encoding

Code Compression for RISC Processors with Variable Length Instruction Encoding Code Compression for RISC Processors with Variable Length Instruction Encoding S. S. Gupta, D. Das, S.K. Panda, R. Kumar and P. P. Chakrabarty Department of Computer Science & Engineering Indian Institute

More information

ECE 261: Full Custom VLSI Design

ECE 261: Full Custom VLSI Design ECE 261: Full Custom VLSI Design Prof. James Morizio Dept. Electrical and Computer Engineering Hudson Hall Ph: 201-7759 E-mail: jmorizio@ee.duke.edu URL: http://www.ee.duke.edu/~jmorizio Course URL: http://www.ee.duke.edu/~jmorizio/ece261/261.html

More information

Rolling Up Solutions of Wafer Probing Technologies Joey Wu

Rolling Up Solutions of Wafer Probing Technologies Joey Wu Rolling Up Solutions of Wafer Probing Technologies Joey Wu Manager, Global Marketing Drivers of Semiconductor Industry Source: Yole, 2016 Source: Yole, 2016 Source: Yole, 2016 Source: Yole, 2016 Form-factor

More information

STEEP-SLOPE DEVICES: FROM DARK

STEEP-SLOPE DEVICES: FROM DARK ... STEEP-SLOPE DEVICES: FROM DARK TO DIM SILICON... ALTHOUGH THE SUPERIOR SUBTHRESHOLD CHARACTERISTICS OF STEEP-SLOPE DEVICES CAN HELP POWER UP MORE CORES, RESEARCHERS STILL NEED CMOS TECHNOLOGY TO ACCELERATE

More information

PRELIMINARY DATA SHEET C BAND SUPER LOW NOISE HJ FET

PRELIMINARY DATA SHEET C BAND SUPER LOW NOISE HJ FET PRELIMINARY DATA SHEET FEATURES VERY LOW NOISE FIGURE:.5 db TYP at 4 GHz HIGH ASSOCIATED GAIN: 16. db TYP at 4 GHz GATE WIDTH: 8 µm TAPE & REEL PACKAGING OPTION AVAILABLE LOW COST PLASTIC PACKAGE DESCRIPTION

More information

Using only HyCal. Graph. Graph

Using only HyCal. Graph. Graph Live charge weighted ep yield from all the 2GeV empty target runs Scattering angle from.7 to.9 deg, background dominated by upstream collimator (8%) Notice that here uncertainty from the live charge measurement

More information

Programming Characteristics on Three-Dimensional NAND Flash Structure Using Edge Fringing Field Effect

Programming Characteristics on Three-Dimensional NAND Flash Structure Using Edge Fringing Field Effect JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014 http://dx.doi.org/10.5573/jsts.2014.14.5.537 Programming Characteristics on Three-Dimensional NAND Flash Structure Using Edge

More information

Announcements. Advanced Digital Integrated Circuits. No office hour next Monday. Lecture 2: Scaling Trends

Announcements. Advanced Digital Integrated Circuits. No office hour next Monday. Lecture 2: Scaling Trends EE4 - Spring 008 Advanced Digital Integrated Circuits Lecture : Scaling Trends Announcements No office hour next Monday Extra office hours Tuesday and Thursday -3pm CMOS Scaling Rules Voltage, V / α tox/α

More information

CMOS IC Technology Scaling and Its Impact on Burn-in

CMOS IC Technology Scaling and Its Impact on Burn-in CMOS IC Technology Scaling and Its Impact on Burn-in Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi *, and Chuck Hawkins ** Electrical and Computer Engineering Dept., University of Waterloo,

More information

ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process

ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process Chun-Yu Lin 1, Li-Wei Chu 1, Ming-Dou Ker 1, Ming-Hsiang Song 2, Chewn-Pu Jou 2, Tse-Hua Lu 2, Jen-Chou Tseng

More information

THE growing number of sensor and communication systems

THE growing number of sensor and communication systems 2858 IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION, VOL. 53, NO. 9, SEPTEMBER 2005 Interleaved Thinned Linear Arrays Randy L. Haupt, Fellow, IEEE Abstract This paper presents three approaches to improving

More information

CHAPTER 3 SIMULATION TOOLS AND

CHAPTER 3 SIMULATION TOOLS AND CHAPTER 3 SIMULATION TOOLS AND Simulation tools used in this simulation project come mainly from Integrated Systems Engineering (ISE) and SYNOPSYS and are employed in different areas of study in the simulation

More information

Low Current, High Performance NPN Silicon Bipolar Transistor. Technical Data AT AT-32033

Low Current, High Performance NPN Silicon Bipolar Transistor. Technical Data AT AT-32033 Low Current, High Performance NPN Silicon Bipolar Transistor Technical Data AT-311 AT-333 Features High Performance Bipolar Transistor Optimized for Low Current, Low Voltage Operation 9 MHz Performance:

More information

ECE 637 Integrated VLSI Circuits. Introduction. Introduction EE141

ECE 637 Integrated VLSI Circuits. Introduction. Introduction EE141 ECE 637 Integrated VLSI Circuits Introduction EE141 1 Introduction Course Details Instructor Mohab Anis; manis@vlsi.uwaterloo.ca Text Digital Integrated Circuits, Jan Rabaey, Prentice Hall, 2 nd edition

More information

Design and Transient Analysis of high Performance HEMT based DRAM Cell

Design and Transient Analysis of high Performance HEMT based DRAM Cell _ Design and Transient Analysis of high Performance HEMT based DRAM Cell 1 Balwant Raj and 2 Sukhleen Bindra Narang 1 Assistant Professor, UIET, Panjab University SSG Regional Centre Hoshiarpur, Punjab,

More information

RAJIV GANDHI COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ECE QUESTION BANK- EDC SEMESTER - III UNIT I : SEMICONDUCTOR DIODS PART A

RAJIV GANDHI COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ECE QUESTION BANK- EDC SEMESTER - III UNIT I : SEMICONDUCTOR DIODS PART A RAJIV GANDHI COLLEGE OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF ECE QUESTION BANK- EDC SEMESTER - III UNIT I : SEMICONDUCTOR DIODS 1. Define Electronics. 2. What is meant by forbidden energy gap. 3. Classify

More information

Using Excel for Graphical Analysis of Data

Using Excel for Graphical Analysis of Data Using Excel for Graphical Analysis of Data Introduction In several upcoming labs, a primary goal will be to determine the mathematical relationship between two variable physical parameters. Graphs are

More information

ΔΙΑΛΕΞΗ 5: FPGA Programming Technologies (aka: how to connect/disconnect wires/gates)

ΔΙΑΛΕΞΗ 5: FPGA Programming Technologies (aka: how to connect/disconnect wires/gates) ΗΜΥ 408 ΨΗΦΙΑΚΟΣ ΣΧΕΔΙΑΣΜΟΣ ΜΕ FPGAs Χειμερινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 5: FPGA Programming Technologies (aka: how to connect/disconnect wires/gates) (ack: Jurriaan Schmitz, Semiconductor Components) ΧΑΡΗΣ

More information

LOGIC EFFORT OF CMOS BASED DUAL MODE LOGIC GATES

LOGIC EFFORT OF CMOS BASED DUAL MODE LOGIC GATES LOGIC EFFORT OF CMOS BASED DUAL MODE LOGIC GATES D.Rani, R.Mallikarjuna Reddy ABSTRACT This logic allows operation in two modes: 1) static and2) dynamic modes. DML gates, which can be switched between

More information

B4-Flash for Tier 0 SSD Applications

B4-Flash for Tier 0 SSD Applications B4-Flash for Tier 0 SSD Applications More Features for SSD with B4-Flash Moriyoshi Nakashima GENUSION,Inc http://www.genusion.co.jp/ info@genusion.co.jp Santa Clara, CA 1 NAND has been well cooked with

More information

ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process

ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process Tao-Yi Hung and Ming-Dou Ker Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan Abstract- ESD protection design

More information

ESD Protection Design for Mixed-Voltage I/O Interfaces -- Overview

ESD Protection Design for Mixed-Voltage I/O Interfaces -- Overview ESD Protection Design for Mixed-Voltage Interfaces -- Overview Ming-Dou Ker and Kun-Hsien Lin Abstract Electrostatic discharge (ESD) protection design for mixed-voltage interfaces has been one of the key

More information

CMOS Logic Gate Performance Variability Related to Transistor Network Arrangements

CMOS Logic Gate Performance Variability Related to Transistor Network Arrangements CMOS Logic Gate Performance Variability Related to Transistor Network Arrangements Digeorgia N. da Silva, André I. Reis, Renato P. Ribas PGMicro - Federal University of Rio Grande do Sul, Av. Bento Gonçalves

More information

Microelectronics Reliability

Microelectronics Reliability Microelectronics Reliability 52 (2012) 1020 1030 Contents lists available at SciVerse ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel Study of intrinsic characteristics

More information

DESIGN AND IMPLEMENTATION OF UNIVERSAL GATE USING DG-FinFET 32NM TECHNOLOGY

DESIGN AND IMPLEMENTATION OF UNIVERSAL GATE USING DG-FinFET 32NM TECHNOLOGY DESIGN AND IMPLEMENTATION OF UNIVERSAL GATE USING DG-FinFET 32NM TECHNOLOGY SEEMA MEHTA 1, DEVESH KISHORE 2, AASTHA HAJARI 3 PG Scholar 1, Assistant Professor 2,3 Shiv Kumar Singh Institute of Technology

More information

Digital Image Processing

Digital Image Processing Digital Image Processing Image Restoration and Reconstruction (Noise Removal) Christophoros Nikou cnikou@cs.uoi.gr University of Ioannina - Department of Computer Science and Engineering 2 Image Restoration

More information

S 1 S 2. C s1. C s2. S n. C sn. S 3 C s3. Input. l k S k C k. C 1 C 2 C k-1. R d

S 1 S 2. C s1. C s2. S n. C sn. S 3 C s3. Input. l k S k C k. C 1 C 2 C k-1. R d Interconnect Delay and Area Estimation for Multiple-Pin Nets Jason Cong and David Zhigang Pan Department of Computer Science University of California, Los Angeles, CA 90095 Email: fcong,pang@cs.ucla.edu

More information

Routing with Graphene Nanoribbons

Routing with Graphene Nanoribbons Routing with Graphene Nanoribbons Tan Yan Qiang Ma Scott Chilstedt Martin D. F. Wong Deming Chen Department of ECE, University of Illinois at Urbana-Champaign, Urbana, IL 61801, USA Synopsys, Inc., Mountain

More information

INEL-6080 VLSI Systems Design

INEL-6080 VLSI Systems Design INEL-6080 VLSI Systems Design ooooooo Prof. Manuel Jiménez Lecture 1 Introduction Computational Devices The idea of developing computing devices is certainly not new A few chronological examples show the

More information

1.12 Optimal Filters (Wiener Filters)

1.12 Optimal Filters (Wiener Filters) Random Data 75 1.12 Optimal Filters (Wiener Filters) In calculating turbulent spectra we frequently encounter a noise tail just as the spectrum roles down the inertial subrange (-5/3 slope region) toward

More information

EXTREMELY LOW-POWER AI HARDWARE ENABLED BY CRYSTALLINE OXIDE SEMICONDUCTORS

EXTREMELY LOW-POWER AI HARDWARE ENABLED BY CRYSTALLINE OXIDE SEMICONDUCTORS Semiconductor Energy Laboratory: White Paper EXTREMELY LOW-POWER AI HARDWARE ENABLED BY CRYSTALLINE OXIDE SEMICONDUCTORS Semiconductor Energy Laboratory (SEL): Extremely low-power AI chips can be built

More information

Unleashing MRAM as Persistent Memory

Unleashing MRAM as Persistent Memory Unleashing MRAM as Persistent Memory Andrew J. Walker PhD Spin Transfer Technologies Contents The Creaking Pyramid Challenges with the Memory Hierarchy What and Where is MRAM? State of the Art pmtj Unleashing

More information

Comparison of Wafer-level Spatial I DDQ Estimation Methods: NNR versus NCR

Comparison of Wafer-level Spatial I DDQ Estimation Methods: NNR versus NCR Comparison of Wafer-level Spatial I DDQ Estimation Methods: versus Sagar S. Sabade * D. M. H. Walker + Department of Computer Science Texas A&M University College Station, TX 7783-3 Phone: (979) 86-387

More information

Quality versus Intelligibility: Evaluating the Coding Trade-offs for American Sign Language Video

Quality versus Intelligibility: Evaluating the Coding Trade-offs for American Sign Language Video Quality versus Intelligibility: Evaluating the Coding Trade-offs for American Sign Language Video Frank Ciaramello, Jung Ko, Sheila Hemami School of Electrical and Computer Engineering Cornell University,

More information

Math 1020 Objectives & Exercises Calculus Concepts Spring 2019

Math 1020 Objectives & Exercises Calculus Concepts Spring 2019 Section of Textbook 1.1 AND Learning Objectives/Testable Skills Identify four representations of a function. Specify input and output variables, input and output descriptions, and input and output units.

More information

ECE520 VLSI Design. Lecture 1: Introduction to VLSI Technology. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 1: Introduction to VLSI Technology. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 1: Introduction to VLSI Technology Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Course Objectives

More information

Using Excel for Graphical Analysis of Data

Using Excel for Graphical Analysis of Data EXERCISE Using Excel for Graphical Analysis of Data Introduction In several upcoming experiments, a primary goal will be to determine the mathematical relationship between two variable physical parameters.

More information

B.Sc. (Computer Science) (Part 1) EXAMINATION, 2009 COMPUTER PROGRAMMING FUNDAMENTAL

B.Sc. (Computer Science) (Part 1) EXAMINATION, 2009 COMPUTER PROGRAMMING FUNDAMENTAL 1 COMPUTER PROGRAMMING FUNDAMENTAL Attempt any five questions. All questions carry equal marks. 1. Differentiate algorithm and program. How a program is developed? Discribe the importance of algorithm

More information

Micro transductors 08

Micro transductors 08 Micro transductors 8 CMOS Basics Dr.-Ing. Frank Sill Department of Electrical Engineering, Federal University of Minas Gerais, Av. Antônio Carlos 6627, CEP: 327-, Belo Horizonte (MG), Brazil franksill@ufmg.br

More information

Collapsing for Multiple Output Circuits. Diagnostic and Detection Fault. Raja K. K. R. Sandireddy. Dept. Of Electrical and Computer Engineering,

Collapsing for Multiple Output Circuits. Diagnostic and Detection Fault. Raja K. K. R. Sandireddy. Dept. Of Electrical and Computer Engineering, Diagnostic and Detection Fault Collapsing for Multiple Output Circuits Raja K. K. R. Sandireddy Dept. Of Electrical and Computer Engineering, Auburn University, Auburn AL-36849 USA Outline Introduction

More information

Introduction 1. GENERAL TRENDS. 1. The technology scale down DEEP SUBMICRON CMOS DESIGN

Introduction 1. GENERAL TRENDS. 1. The technology scale down DEEP SUBMICRON CMOS DESIGN 1 Introduction The evolution of integrated circuit (IC) fabrication techniques is a unique fact in the history of modern industry. The improvements in terms of speed, density and cost have kept constant

More information

INTERNATIONAL TECHNOLOGY ROADMAP

INTERNATIONAL TECHNOLOGY ROADMAP INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2011 EDITION PROCESS INTEGRATION, DEVICES, AND STRUCTURES THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY

More information

A Single Poly Flash Memory Intellectual Property for Low-Cost, Low-Density Embedded Nonvolatile Memory Applications

A Single Poly Flash Memory Intellectual Property for Low-Cost, Low-Density Embedded Nonvolatile Memory Applications Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002, pp. 846 850 A Single Poly Flash Memory Intellectual Property for Low-Cost, Low-Density Embedded Nonvolatile Memory Applications Jai-Cheol

More information

Low Leakage Bit-Line Sram Design Architectures

Low Leakage Bit-Line Sram Design Architectures Low Leakage Bit-Line Sram Design Architectures Ratan kumar.s.v., Dept. of ECE, Assistant Professor, RGMCET, Nandyal, saneratankumar@gmail.com Mr.S.Kashif Hussain, Asst.Prof in ECE, RGMCET, Nandyal, kashif1919@gmail.com

More information

Advancing high performance heterogeneous integration through die stacking

Advancing high performance heterogeneous integration through die stacking Advancing high performance heterogeneous integration through die stacking Suresh Ramalingam Senior Director, Advanced Packaging European 3D TSV Summit Jan 22 23, 2013 The First Wave of 3D ICs Perfecting

More information

FLASH DATA RETENTION

FLASH DATA RETENTION FLASH DATA RETENTION Document #AN0011 Viking Rev. B Purpose of this Document This application note was prepared to help OEM system designers evaluate the performance of Viking solid state drive solutions

More information

DOWNLOAD OR READ : SEMICONDUCTOR DEVICES EXPLAINED USING ACTIVE SIMULATION PDF EBOOK EPUB MOBI

DOWNLOAD OR READ : SEMICONDUCTOR DEVICES EXPLAINED USING ACTIVE SIMULATION PDF EBOOK EPUB MOBI DOWNLOAD OR READ : SEMICONDUCTOR DEVICES EXPLAINED USING ACTIVE SIMULATION PDF EBOOK EPUB MOBI Page 1 Page 2 semiconductor devices explained using active simulation semiconductor devices explained using

More information

TO IMPROVE circuit operating speed and performance,

TO IMPROVE circuit operating speed and performance, 602 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005 ESD Protection Design of Low-Voltage-Triggered p-n-p Devices and Their Failure Modes in Mixed-Voltage I/O Interfaces

More information

ELECTROSTATIC (ESD) has been an important reliability

ELECTROSTATIC (ESD) has been an important reliability IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 53, NO. 10, OCTOBER 2006 2187 Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices

More information

Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits

Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits Ming-Dou Ker, Hsin-Chyh Hsu, and Jeng-Jie Peng * Nanoelectronics and

More information

AT-41511, AT General Purpose, Low Noise NPN Silicon Bipolar Transistors. Data Sheet. Description. Features. Pin Connections and Package Marking

AT-41511, AT General Purpose, Low Noise NPN Silicon Bipolar Transistors. Data Sheet. Description. Features. Pin Connections and Package Marking AT-4111, AT-4133 General Purpose, Low Noise NPN Silicon Bipolar Transistors Data Sheet Description Avago s AT-4111 and AT-4133 are general purpose NPN bipolar transistors that offer excellent high frequency

More information

An Energy Improvement in Cache System by Using Write Through Policy

An Energy Improvement in Cache System by Using Write Through Policy An Energy Improvement in Cache System by Using Write Through Policy Vigneshwari.S 1 PG Scholar, Department of ECE VLSI Design, SNS College of Technology, CBE-641035, India 1 ABSTRACT: This project presents

More information

Chapter 6. Applications of CLC photonic crystals. Traditional liquid crystal displays use color filters to generate colors. However, only ~33% of

Chapter 6. Applications of CLC photonic crystals. Traditional liquid crystal displays use color filters to generate colors. However, only ~33% of Chapter 6. Applications of CLC photonic crystals Yun Ho Kim 1. Flexible reflective display and dynamic reflector Traditional liquid crystal displays use color filters to generate colors. However, only

More information

Limerock Bearing Ratio Technician Training Course

Limerock Bearing Ratio Technician Training Course Limerock Bearing Ratio Technician Training Course Module 6: Calculating and Reporting LBR Technician Release 10, Module 6 1 - This section will cover the how to use LBR penetration data to determine individual

More information

Power-Optimal Pipelining in Deep Submicron Technology Λ

Power-Optimal Pipelining in Deep Submicron Technology Λ 8. Power-Optimal Pipelining in Deep Submicron Technology Λ Seongmoo Heo and Krste Asanović MIT Computer Science and Artificial Intelligence Laboratory Vassar Street, Cambridge, MA 9 fheomoo,krsteg@csail.mit.edu

More information

Polygonal representation of 3D urban terrain point-cloud data

Polygonal representation of 3D urban terrain point-cloud data Polygonal representation of 3D urban terrain point-cloud data part I Borislav Karaivanov The research is supported by ARO MURI 23 February 2011 USC 1 Description of problem Assumptions: unstructured 3D

More information

Transactions on Device and Materials Reliability. Highly reliable nitride-based LEDs with internal ESD protection diodes

Transactions on Device and Materials Reliability. Highly reliable nitride-based LEDs with internal ESD protection diodes Highly reliable nitride-based LEDs with internal ESD protection diodes Journal: Manuscript ID: Suggested Category: Date Submitted by the Author: TDMR-0--0 Regular Paper 0-Nov-0 Complete List of Authors:

More information

Microelettronica. J. M. Rabaey, "Digital integrated circuits: a design perspective" EE141 Microelettronica

Microelettronica. J. M. Rabaey, Digital integrated circuits: a design perspective EE141 Microelettronica Microelettronica J. M. Rabaey, "Digital integrated circuits: a design perspective" Introduction Why is designing digital ICs different today than it was before? Will it change in future? The First Computer

More information

Business Benefits of Policy Based Data De-Duplication Data Footprint Reduction with Quality of Service (QoS) for Data Protection

Business Benefits of Policy Based Data De-Duplication Data Footprint Reduction with Quality of Service (QoS) for Data Protection Data Footprint Reduction with Quality of Service (QoS) for Data Protection By Greg Schulz Founder and Senior Analyst, the StorageIO Group Author The Green and Virtual Data Center (Auerbach) October 28th,

More information

CMPEN 411 VLSI Digital Circuits. Lecture 01: Introduction

CMPEN 411 VLSI Digital Circuits. Lecture 01: Introduction CMPEN 411 VLSI Digital Circuits Kyusun Choi Lecture 01: Introduction CMPEN 411 Course Website link at: http://www.cse.psu.edu/~kyusun/teach/teach.html [Adapted from Rabaey s Digital Integrated Circuits,

More information

Alternative Erase Verify : The Optimization for Longer Data Retention of NAND FLASH Memory

Alternative Erase Verify : The Optimization for Longer Data Retention of NAND FLASH Memory , pp.137-146 http//dx.doi.org/10.14257/ijca.2017.10.2.12 Alternative Erase Verify : The Optimization for Longer Data Retention of NAND FLASH Memory Juwan Seo 1, Namgi Kim 2 and Min Choi* 1 1 Dept. of Information

More information

Qualification Strategies of Field Programmable Gate Arrays (FPGAs) for Space Application October 26, 2005

Qualification Strategies of Field Programmable Gate Arrays (FPGAs) for Space Application October 26, 2005 Qualification Strategies of Field Programmable Gate Arrays (FPGAs) for Space Application October 26, 2005 Douglas Sheldon Harald Schone Historical FPGAs have been used in spacecraft for over 10 years.

More information

WITH the thriving applications on automotive electronics,

WITH the thriving applications on automotive electronics, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 57, NO. 5, MAY 2010 1039 Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process Wen-Yi Chen, Student

More information

Investigation of Diffusion Rounding for. Investigation of Diffusion Rounding for. Post-Lithography Analysis. Puneet Gupta 1, Andrew B.

Investigation of Diffusion Rounding for. Investigation of Diffusion Rounding for. Post-Lithography Analysis. Puneet Gupta 1, Andrew B. Investigation of Diffusion Rounding for Investigation of Diffusion Rounding for Post-Lithography Analysis Puneet Gupta 1, Andrew B. Kahng 2, Youngmin Kim 3*, Saumil Shah 4, and Dennis Sylvester 3 1 University

More information

Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp

Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp . BRIEF REPORT. SCIENCE CHINA Information Sciences February 2014, Vol. 57 029401:1 029401:6 doi: 10.1007/s11432-013-5016-1 Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power

More information

International Technology Roadmap for Semiconductors

International Technology Roadmap for Semiconductors International Technology Roadmap for Semiconductors 2007 ITRS ORTC [12/5 Makuhari Japan ITRS Public Conference] A.Allan, Rev 0.0 (For IRC Review) 10/29/07 1 Agenda Moore s Law and More Definitions Technology

More information

Announcements. Advanced Digital Integrated Circuits. No office hour next Monday. Lecture 2: Scaling Trends

Announcements. Advanced Digital Integrated Circuits. No office hour next Monday. Lecture 2: Scaling Trends EE24 - Spring 2008 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends Announcements No office hour next Monday Extra office hours Tuesday and Thursday 2-3pm 2 CMOS Scaling Rules Voltage, V

More information

SMAFTI Package Technology Features Wide-Band and Large-Capacity Memory

SMAFTI Package Technology Features Wide-Band and Large-Capacity Memory SMAFTI Package Technology Features Wide-Band and Large-Capacity Memory KURITA Yoichiro, SOEJIMA Koji, KAWANO Masaya Abstract and NEC Corporation have jointly developed an ultra-compact system-in-package

More information

PHASE-CHANGE TECHNOLOGY AND THE FUTURE OF MAIN MEMORY

PHASE-CHANGE TECHNOLOGY AND THE FUTURE OF MAIN MEMORY ... PHASE-CHANGE TECHNOLOGY AND THE FUTURE OF MAIN MEMORY... PHASE-CHANGE MEMORY MAY ENABLE CONTINUED SCALING OF MAIN MEMORIES, BUT PCM HAS HIGHER ACCESS LATENCIES, INCURS HIGHER POWER COSTS, AND WEARS

More information

THE device dimension of transistor has been scaled toward

THE device dimension of transistor has been scaled toward 1934 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 53, NO. 9, SEPTEMBER 2006 Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors Ming-Dou Ker,

More information

Stacked Silicon Interconnect Technology (SSIT)

Stacked Silicon Interconnect Technology (SSIT) Stacked Silicon Interconnect Technology (SSIT) Suresh Ramalingam Xilinx Inc. MEPTEC, January 12, 2011 Agenda Background and Motivation Stacked Silicon Interconnect Technology Summary Background and Motivation

More information

INTEGRATED ANISOTROPIC SIMULATION FOR COMPONENTS MADE FROM GLASS FIBER REINFORCED THERMOPLASTICS

INTEGRATED ANISOTROPIC SIMULATION FOR COMPONENTS MADE FROM GLASS FIBER REINFORCED THERMOPLASTICS INTEGRATED ANISOTROPIC SIMULATION FOR COMPONENTS MADE FROM GLASS FIBER REINFORCED THERMOPLASTICS David Sheridan Ticona, Auburn Hills, Michigan Ulrich Mohr-Matuschek & Anton Grzeschik Ticona, Sulzbach,

More information