Advanced Microprocessors

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1 Advanced Microprocessors Notes #7 I/O Interfacing EE 467/567 Winter 2012 By Avinash Kodi IO.1 Background Materials Textbook: See Web Other: IA-32 Intel Architecture Software Developer s Manual Volume 1 I/O: Sections 13.1, 13.2, 13.3, 13.4 Interrupts: Sections 6.4 IA-32 Intel Architecture Software Developer s Manual Volume 3a Interrupts: Sections 5.1, 5.2, 5.3, 5.4, 5.5, 5.10, 8.1, 8.2, 8.3, 8.4.1, Handout IO.2 1

2 So Far Instruction Set Architecture 2,3,4 Memory Management: Segmentation & Paging Processor Core DRAM Memory IO.3 So Far SRAM Memory: Cache 6 IO.4 2

3 These Slides I/O Programmed I/O Interrupt-driven I/O Direct Memory Access Interrupts & Exceptions Programmable Interrupt Controller (PIC) Advanced PIC (APIC) IO.5 Input / Output (I/O) Subcategories Programmed I/O: I/O occurs under the direct and continuous control of the program requesting the I/O operation Interrupt-driven I/O: Program issues an I/O command and continues to execute, until it is interrupted by the I/O hardware to signal a required I/O operation Direct Memory Access (DMA): A specialized I/O processor takes over the control of an I/O operation to move a large block of data IO.6 3

4 Input / Output (I/O) Front Side Bus - DMA I/O does not go through the CPU IO.7 Input / Output (I/O) Programmed I/O Isolated I/O Treat the I/O devices separately from memory. In other words, they have their own address space: The I/O address space. Hybrid I/O Memory 0xFFF Memory-Mapped I/O Treat the I/O devices similarly to memory by placing them in the memory address space. 0xFFF Memory 0x000 I/O 0xFFF Memory 0x000 I/O (Pentium, P6, Pentium 4) 640k-1M 0x000 I/O (386,486) (PowerPC) IO.8 4

5 Isolated I/O Selection A 0 A A 31 D 0 Pentium A 31 D 0 D 32 IO/M W/R RDY D 63 IO/M W/R RDY 0: A 0 -A 15 - I/O Address 1: A 0 -A 31 Memory Address BE 0 BE 2 BE 3 BE 4 BE 0 BE 7 IO.9 Isolated I/O I/O Ports FFFF 16 Port I/O Address Space (Map) 00FF 16 00FE 16 Port 255 Port Port Port 3 Port 2 Port 1 Port 0 Port 1 (16-bit port) Port 0 (16-bit port) Port 0 (32-bit port) IO.10 5

6 Memory Mapped I/O I/O Ports FFFFF 16 E0FFF 16 Port 255 E0FFE 16 Port 254 Memory Address Space (Map) E E E E Port 3 Port 2 Port 1 Port 0 I/O Addresses IO.11 Input / Output (I/O) Front Side Bus - Programmed I/O I/O via the FSB IO.12 6

7 I/O Instructions Isolated I/O Note that the address of the port is and immediate value ( imm8 ) or located in DX MOV DX, 3F0h ; Setup the port s address as 3F0h OUT DX, AX ; Write a word to the 16-bit port IO.13 I/O Instructions Isolated I/O String Operations Followed by an increment of SI or DI similar to: Prefix REP can be used for all these instructions (see Notes #4) IO.14 7

8 I/O Instructions Isolated I/O String Operations Example: Program segment reads 100 bytes from I/O port with address 3F0h and stores them in an array at memory location var1 MOV DX, 3F0h MOV CX, 100 ; Initialize the counter MOV EDI, var1 ; Source index points to series origin CLD ; REPINSB Considered a complex instruction: will be broken into multiple micro-operations in the processor core! Clear the data direction flag (DF = 0) for auto-increment of DI! IO.15 I/O Instructions Memory Mapped I/O Use the MOV instruction and all related instructions such as the string instructions MOV SI, 13F0h ; Suppose memory-mapped port is at 13F0h MOV CX, 100 ; Initialize the counter MOV DI, var1 ; Source index points to series origin CLD ; NXT: MOV AL, [SI] MOV [DI], AL INC DI LOOP NXT Note: ((DX)) The port address is stored in DX Compare Memory access: MOV AX, [DX] ; AX ((DX)) with I/O access: IN AX, DX ; AX ((DX)) IO.16 8

9 Example: PC I/O Map 0 1F DMA Controller (8237) 20 3F Interrupt controller (8259) 40-5F Timer (8253/4) 60-6F Parallel interface (8255) 70-7F Real-time clock (AT) 80-9F DMA page register A0-BF NMI mask register or second interrupt controller C0-DF Second DMA controller E0-EF Reserved F0-FF Math-coprocessor (AT) 1F0-1F8 Fixed disk (AT) F Game controller Expansion unit F Reserved F Second parallel printer port 2F0-2F7 Reserved 2F8-2FF COM F Prototype card F Fixed disk F Reserved F Parallel printer port (LPT1) Second bi-sync communications 3A0-3A9 Bi-sync communications 3B0-3BF Monochrome display 3C0-3CF Reserved 3D0-3DF CGA 3E0-3E7 Reserved 3F0-3F7 Floppy disk 3F8-3FF COM 1 Example: A joystick is mapped into the I/O space via the Game Port at address 201H. The bits in the byte at that location represent: 0: coordinate X of joystick A 1: coordinate Y of joystick A 2: coordinate X of joystick B 3: coordinate Y of joystick B 4: button #1 of joystick A 5: button #2 of joystick A 6: button #1 of joystick B 7: button #2 of joystick B What does the following program check? MOV IN AND JNZ DX, 201H AL, DX AL, 10H GO_TO_SUBROUTINE IO.17 I/O Interfacing Similar to memories: Use decoder circuitry to map I/O devices into the I/O or Memory address space. Input and output of data can be accomplished using latches and buffers. Memory devices often have internal latches and/or buffers, I/O devices may require external latches and/or buffers Why buffers and latches?? Buffer: a device placed between two other devices that provides isolation and current amplification. Latch: a device that is able to hold a particular digital state even after the input is removed. IO.18 9

10 I/O Interfacing Latches Example: 74LS373 D 0 D Q Q 0 From CPU Input Data Bus Output Data Bus To I/O device D 7 Q 7 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 IOW G OC Latch Enable pin How does one write something to this output port? OUT 98H, AL IO.19 Example: I/O Interfacing Buffers 74LS244 D 0 Q 0 From I/O Device D 4 Input Data Bus To system Data Bus To CPU D 7 Q 7 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 G1 G2 How does one read something from this output port? IN AL, 5FH IOR IO.20 10

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