Interfacing Fundamentals

Transcription

1 CHAPTER Interfacing Fundamentals 3.1 Introduction There is no doubt that the microcomputer revolution will continue into the future and many will be required to specify and integrate microprocessors into products or systems in their own disciplines. Therefore, well-designed flexible interfaces will be required to ensure compatibility with other equipments and to extend design options. Interfaces are the last items to be seriously considered in the race of new technology, and it deals with the systematic study of microprocessor interfaces and their applications in many diversified fields. In this subject students learn how to interface microprocessors, and hence microcomputers and other related equipments, to external digital or analog devices. The microprocessor progress has advanced at a pace perhaps unparallel in scientific history. Since the introduction of the first microcomputer chip in 1971, there have been four generations of microprocessors, and the number of devices per chip has increased by a factor of 2000, the clock frequency by a factor of 1000, and the overall throughput of the microprocessor has increased by hundred or several hundreds of magnitudes. Developing a microprocessor (μp)-based system represents one of the most difficult tasks that can confront an engineer. Advances in microprocessor architectures and capabilities are forcing changes in development systems and the ways in which they develop microcode instructions. Also, all μp architectures are not created equal when it comes to providing designers with the tools they need for effective systems resource management. Therefore, well designed Compiled by : Dr.. Manoj V.N.V. Page 105

2 flexible interfaces will be required to ensure compatibility and extend design options. Interface Definitions Interface -A shared boundary between system elements defined by common physical interconnection characteristics, signal characteristics, and meanings of interchanged signals. Interface Device -A device that meets the interface specifications on one side of an interface. The term is usually applied to a device through which a system or equipment works to meet interface specifications. Interface EIA Standard RS-232 B or C -A standardized method adopted by the Electronic Industries Association to insure uniformity of interface between data communication equipment and data processing terminal equipment. Has been generally accepted by most manufacturers for data transmission. Interface Specification -A set of technical requirements that must be met at an interface. Direct memory access -A technique that permits a peripheral device to enter or extract blocks of data from the memory without involving the central processing unit. In some cases, the CPU can perform other functions while the data transfers occur. Components of Interface Interfacing Device (ID 1) Interface Signals Interfacing Standards & Converters Interface Signals Interfacing Device (ID 2) Fig: Important Components of Interface A shared interconnection between system elements defined by common physical interconnection characteristics, signal characteristics, and meanings of Compiled by : Dr.. Manoj V.N.V. Page 106

3 interchanged signals. Interfacing of two IDs require the following components. Processing the interfacing signals normally based on the type of devices that are used. Most of the time if the IDs are computer terminals RS-232 standard is used. RS-232 standard uses a totally different signal representation. This uses high positive voltage for binary 0 and high negative voltage for binary 1. These signals are called as standard CMOS signals. But most of the other motherboard signals and interfacing circuit signals use TTL signals. So it is mandatory to make use of a CMOS to TTL converter at these interfaces. Also based on the type of devices to be interfaced, various ADC and DAC devices are required. Some of the complex interfaces need to be controlled by stored program circuits. This makes use of EPROM programmers to permanently store the control program in the circuit board. The interfacing devices should make use of standard data transfer schemes for the efficient exchange of data. Following discussion will give the detailed analysis on the different data transfer schemes. Data Transfer Schemes The data transfer schemes refers to the method of data transfer between the processor and peripheral devices. In a typical microcomputer, data transfer takes place between any two devices: microprocessor and memory; microprocessor and I/O devices; memory and I/O devices. For effective data transfer between these devices, the timing parameters of the devices should be matched. But most of the devices have incompatible timings. For example, an I/O device may be slower than the processor due to which, it cannot send data to the processor at the expected time. The semiconductor memories are available with compatible timings. Moreover, slow memories can be interfaced using additional hardware to introduce wait states in machine cycles. The microprocessor system designer often face difficulties while interfacing I/O devices & magnetic memories (like floppy or hard disk) to achieve effective data transfer to or from microprocessor. Several Compiled by : Dr.. Manoj V.N.V. Page 107

4 data transfer schemes have been developed to solve the interfacing problems with I/O devices. The data transfer schemes have been broadly classified into the following two categories. 1. Programmed data transfer. 2. Direct memory access data transfer. In programmed data transfer, a memory resident routine (subroutine) requests the device for data transfer to or from one of the processor register. Programmed data transfer scheme is used when a relatively small amount data are to be transferred. In these schemes, usually one byte or word of data is transferred at a time. Examples of devices using parallel data transfer are ADC,DAC, Hex-keyboard, 7-segment LED's, etc. The programmed data transfer scheme can be further classified into the following three types. 1. Synchronous data transfer scheme. 2. Asynchronous data transfer scheme. 3. Interrupt driven data transfer scheme. In DMA data transfer, the processor is forced to hold state by an I/O device until the data transfer between the device and the memory is completed. The processor does not execute any instructions during the hold period. The DMA data transfer is used for large block of data transfer between I/O device and memory. Typical examples of devices using DMA are CRT controller, floppy disk, hard disk, high speed line printer, etc. The different types of DMA data transfer schemes are 1. Cycle stealing DMA. 2. Block or Burst mode DMA. 3. Demand transfer mode DMA. The fig below shows the various types of data transfer schemes. Compiled by : Dr.. Manoj V.N.V. Page 108

5 Fig : Types of Data Transfer Schemes All the data transfer schemes discussed above requires both software and hardware for their implementation. Within a microcomputer, more than one scheme can be used for interfacing different I/O devices. However, some of these schemes require specific hardware features in the microprocessor for implementing the scheme. PROGRAM CONTROLLED TRANSFER In this scheme, the transfer of data is completely under the control of the microprocessor program. i.e an i/o operation takes place only when an i/o instruction is encountered in the execution of the program. Data transfers can take place synchronously or asynchronously. Synchronous transfers mean transfers occurring at the same time. The sender and the receiver are synchronized to operate at the same clock speed. This is preferred when the speeds of both the sender and the receiver match. Synchronous transfers are used in high-speed transmission. Asynchronous transfers mean transfers taking place at irregular intervals. These are used in low -speed transmission. Compiled by : Dr.. Manoj V.N.V. Page 109

6 Data transfers between the microprocessor and the peripherals are primarily asynchronous. Program controlled data transfers can take place under several conditions. They are:- Unconditional: The microprocessor assumes that a peripheral is always available. For example, to display data at an LED port,. The microprocessor simply enables the port, transfers data and goes on to execute the next instruction. Polling: The microprocessor is kept in a loop to check whether data are available. The KYCLO loop in the matrix keyboard program is an example of polling the input device for data availability. Interrupt: The microprocessor is interrupted from its normal execution of program by an I/O device, when the latter is ready. Then the microprocessor suspends execution of the program, & branches to service the interrupt. After completing the I/O transfer, the microprocessor returns to the main program and continues. This scheme eliminates the need for the microprocessor to wait in a loop until the device gets ready and hence is more efficient. With ready signal: When peripheral response time is slower than the microprocessor execution time, READY signal is used. The microprocessor samples this signal during T2 of every Read/ writes machine cycle. If it is high, The I/O device is ready and the microprocessor goes ahead with transfer. If READY is low, it means that the peripheral is not ready and additional T states will be inserted in the, execution cycle by external hardware. These T -states are called WAIT states. They prolong the instruction execution; this scheme is generally used with slow memory devices. With handshake Signals: Handshake signals are signals exchanged prior to data transfer. Their purpose is ensure readiness of the peripheral and to synchronize timing of data transfer For example the IBF, STB, OBF signals in mode 1 operation of A are handshake signals. These are called STATUS CHECK Compiled by : Dr.. Manoj V.N.V. Page 110

7 signals. INTR is an interrupt signal, A generates in response to.stb, and IBF. This can be used to interrupt the microprocessor for I/O transfer. Synchronous data transfer scheme The synchronous data transfer scheme is the simplest of all data transfer schemes. In this scheme the processor does not check the readiness of the device. The I/O device or peripheral should have matched timing parameters. Whenever data is to be obtained from the device or transferred to the device, the user program can issue a suitable instruction for the device. At the end of the execution of this instruction, the transfer would have been completed. The synchronous data transfer scheme can also be implemented with small delay (if the delay is tolerable) after the request has been made. The sequence of operations for synchronous data transfer scheme is shown in figure below. The mode-o input or output in 8155 or 8255 is an example of synchronous data transfer. Asynchronous Data Transfer Schemes The asynchronous data transfer scheme is employed when the speed of processor and I/O device does not match. In this scheme the processor ends a request to the device for read/write operation. Then the processor keeps on polling the status of the device. Once the device is ready, the processor executes a data transfer instruction to complete the process. To implement this scheme, the device should provide a signal which may be tested by the processor to ascertain whether it is ready or not. The sequence of operations for asynchronous data transfer is shown in the figure below. The handshake data transfer without interrupt (mode-l and mode-2) of8155 or 8255 is an example of synchronous data transfer. Compiled by : Dr.. Manoj V.N.V. Page 111

8 Fig (a): Synchronous Data Transfer Scheme (b): Asynchronous Data Transfer Scheme Interrupt driven data transfer scheme The interrupt driven data transfer scheme is the best method of data f transfer for effectively utilizing the processor time. In this scheme, the processor first initiates the I/O device for data transfer. After initiating the device, the processor will continue the execution of instructions in the program. Also at the end of an instruction the processor will check for a valid interrupt signal. If there is no interrupt then the processor will continue the execution. When the IO device is ready, it will interrupt the processor. On receiving an interrupt sigt1al the processor will complete the current instruction execution and saves the processor status in stack. Then the processor call an interrupt service routine (ISR) to service the interrupted device. At the end of ISR the processor status is retrieved from stack and the processor starts executing its main program. The sequence of operations for an interrupt driven data transfer scheme is shown in the figure below. Compiled by : Dr.. Manoj V.N.V. Page 112

9 Fig (a) Main Program Execution Sequence Fig (b): ISR Execution Sequence In polled and status check I/O, the microprocessor is kept in a loop to check for data availability at the I/O Port. This scheme is inefficient because the microprocessor is unnecessarily tied up in a loop. Instead, it is more efficient to let the microprocessor carry on with its main job of executing programs without having concern for the I/O device readiness, and let the I/O device send a signal o the microprocessor as and when it gets ready. Such a signal is called an INTERRUI signal. On receiving the interrupt signal, the microprocessor takes the following sequence of steps to process the requirement of the VO device, which sent the signal. The microprocessor P acknowledges the receipt of interrupt signal. The microprocessor completes execution of the current instruction. Compiled by : Dr.. Manoj V.N.V. Page 113

10 It saves the status of program on the stack. It also saves the return address on the stack. Then the microprocessor branches to a predetermined location in the memory (ROM). At this location, either a program to service the interrupt resides or a JMP instruction resides. The program is called INTERRUPT SERVICE ROUTINE. The microprocessor executes this routine and at the end, retrieves the status of the main program and the return address from the stack and returns to the point in the main program from where it branched on interrupt. Then it continues execution of the main program. PROGRAM CONTROLLED DMA TRANSFERS In programmed data transfer, a memory resident routine requests the device for data transfer to and from one of the microprocessor registers. In DMA transfer, the microprocessor is forced to hold on by an I/O device until the data transfer is complete. Programmed data are used when relatively small amounts of data are transferred using relatively slow I/O devices such AID, D/A converters, and peripheral floating point arithmetic unit. DMA is preferred when a large block of data is to be transferred. This scheme is generally employed for transferring data between the microprocessor and peripheral mass storage devices like hard disk or a high-speed line printer. Programmed transfer schemes are further classified into synchronous, asynchronous and interrupt driven transfers. All these schemes require both hardware and software for their implementation. Compiled by : Dr.. Manoj V.N.V. Page 114

11 Programmable Peripheral Interface(PPI) Introduction to Programmable Peripheral Interface IC PPI The Intel 8255A is a high-performance, general purpose programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. The 82C55A is pin compatible with the NMOS 8255A and 8255A-5. In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or outputs. In MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used for handshaking and interrupt control signals. MODE 2 is a strobed bi-directional bus configuration. The 8255A is fabricated on Intel's advanced CHMOS III technology which provides low power consumption with performance equal to or greater than the equivalent NMOS product. The 8255A is available in 40-pin DIP and 44-pin plastic leaded chip carrier (PLCC) packages. 8255A BLOCK DIAGRAM AND FUNCTIONAL DESCRIPTION Compiled by : Dr.. Manoj V.N.V. Page 115

12 The 8255A is a programmable peripheral interface device designed for use in Intel microcomputer systems. Fig: 8255 PPI- Function Block Diagram Its function is that of a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. The functional configuration of the 8255A is programmed by the system software so that normally no external logic is necessary to interface peripheral devices or structures. Data Bus Buffer This 3-state bidirectional 8-bit buffer is used to interface the 8255A to the system data bus. Data is transmitted or received by the buffer Compiled by : Dr.. Manoj V.N.V. Page 116

13 upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU outputs a control word to the 8255A. The control word contains information such as mode, bit set, bit reset, etc., that initializes the functional configuration of the 8255A. Each of the Control blocks (Group A and Group B) accepts ``commands'' from the Read/Write Control Logic, receives ``control words'' from the internal data bus and issues the proper commands to its associated ports. Control Group A - Port A and Port C upper (C7-C4) Control Group B - Port B and Port C lower (C3-C0) The control word register can be both written and read as shown in the address decode table in the pin descriptions. Figure 6 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic ``1'', as this implies control word mode information. Ports A, B, and C The 8255A contains three 8-bit ports (A, B, and C). All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhances the power and flexibility of the 8255A. Port A: One 8-bit data output latch/buffer and one 8-bit input latch buffer. Port B: One 8-bit data input/output latch/buffer. Port C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode Compiled by : Dr.. Manoj V.N.V. Page 117

14 control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B. 8255A OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software: Mode 0 Basic input/output Mode 1 Strobed Input/output Mode 2 Bi-directional Bus When the reset input goes ``high'' all ports will be set to the input mode with all 24 port lines held at a logic ``one'' level by the internal bus hold devices. After the reset is removed the 8255A can remain in the input mode with no additional initialization required. During the execution of the system program, any of the other modes may be selected by using a single output instruction. This allows a single 8255A to service a variety of peripheral devices with a simple software maintenance routine. The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be ``tailored'' to almost any I/O structure. For instance; Group B can be programmed in Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis. The mode definitions and possible mode combinations may seem confusing at first but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the 8255A has taken into account things such as efficient PC board layout, control signal definition vs PC Compiled by : Dr.. Manoj V.N.V. Page 118

15 layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins. Bit Set/Reset Feature Any of the eight bits of Port C can be Set or Reset using a single Output instruction. This feature reduces software requirements in Control-based applications. When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were data output ports. CONTROL WORD: -The control word format for I/O mode is shown in fig below. It is essential to understand this format. In interfacing applications we have to determine the control word for programming the ports for input or output and write it into the CONTROLREGISTER before the data transfer program. This way of determining and writing the CONTROL WORD is called I/O programming. The purpose and meaning of the bits in the control-word are clearly specified in the figure below. Fig: 8255 Control Word Compiled by : Dr.. Manoj V.N.V. Page 119

16 necessary. To communicate with periphera1s, through: 8255A, three steps: are 1. Determine the addresses of ports & control register from the chip select logic. 2. Write a control word into the contro1.register. 3. Write instructions to transfer data to the peripherals through ports A. B & C. Mode 0: Simple Input or.output. The I/O features of this mode are: Ports A, B &C are programmed for simple I/O. Outputs are latched. Inputs are -not latched. Ports do not have handshake or interrupt capability. Example: -twelve DIP switches are interfaced to 8085A via port B and port CL. Twelve LEDs are interfaced via port A and port C L as shown below. Fig: Interfacing 8255 I/O Ports in Mode 0 Compiled by : Dr.. Manoj V.N.V. Page 120

17 1. Identify the port addresses. 2. Determine the control word to configure port A-& port Cu for output and port B and port C L or input. 3. Write a program to read the DIP switches from port B and port C L and to display the readings at port A and port Cu respectively. From the circuit, observe-that the control--signals MEMR and MEMW axe connected. This indicates to us that the devices-are interfaced in MEMORY MAPPED MODE.. So, they will have 16-bit addresses. CS is connected to Al-5 through an inverter. So A15 must be at logic high level for the 8255A to be selected. The other 13 lines Al4 -A2 are left with-out connection they can considered as don't cares. Assuming these don't care lines to be at logic 0. The addresses of the-port are: A15 A14 -A2 A1 A PortA (8000) H PortB (8001) H Port C (8002) H Control Reg (8003) H To determine the control word we know that: D7 = 1 for I/O mode; D6, D5 = 0,0 for mode 0 group A D4 = 0 port A for output D3 = 0 port Cu for output D2 = 0 for mode 0 group B D1 = 1 port B for input Do = 1 port CL for input. Putting these bit values, we get the control word as: D7 D6 D5 D4 D3 D2 D1 D => (83)H. Program for reading the switches and displaying LED Ports: Will be discussed in the class BSR Mode This mode is concerned only with the 8 bits of port C which can be set or reset by writing appropriate control word into the control register. Compiled by : Dr.. Manoj V.N.V. Page 121

18 BSR control word has D7 = 0; BSR control word does not affect any previously transmitted I/O control word with D7 = 1. ; BSR CONTROL WORD This is shown in fig below. it sets or resets port C bits, one bit at a time. Fig: BSR Control Word Format in the BSR Mode In this mode, individual bits of port C can be used for applications such as on On/Off switch. Example -Consider the interface circuit shown in fig (a) below write a BSR control word subroutine to set PC7 and PC3 and reset them after 10 ms. Assume that delay routine is available. Solution: BSR CONTROL WORDS for: D7 D6 Ds D4 D3 D2 D1 D0 i) Setting PC7 0 X X X (OF)H ii) Setting PC6 0 X X X (O7)H iii) Resetting PC7 0 X X X (OE)H iv) Resetting PC3 0 X X X (06)H Compiled by : Dr.. Manoj V.N.V. Page 122

19 fig: Interface Circuit Example on Interfacing will be discussed in the class along with the hardware and software part. Mode 1 Input/Output with Handshake In mode 0, which is used for simple I/O, it is assumed that the peripheral devices are always ready. The microprocessor, therefore, need not ascertain their status before transferring data to and fro. However this is not the case always. In order to check the-status, the ~p and the peripherals exchange a few signals prior to actual data transfer. These signals are called hand shake signals. The 8255A's capability to transfer data with handshake is provided in its mode 1 operation. We shall study this operation in this section. Feature of Mode 1: Port A and port B function as 8-bit I/O ports. Each port uses three bits from port C as handshake signals. The remaining two bits from port C can be used for simple I/O. Input-data and output data are latched. Interrupt logic is supported. Mode 1 input Control Signals: When port A and port B are configured as input ports, they use three bits each from port C as handshake signals. Port A uses PC3, PC4 and PCs bits and port Buses PC0, PC1 and PC2 bits. These are shown in figure. These control signals are named STB, IBF and INTR. The purpose, of these signals is as follows. Compiled by : Dr.. Manoj V.N.V. Page 123

20 Mode 1 Input Configuration STB (Strobe Input): This is-an active low signal, generated by the input device, when a byte of data is transmitted. On receipt of this signal, the 8255 generates two signals, IBF and INTR. IBF is routed to the input device and INTR to the microprocessor. IBF (Input Buffer Full): This is an active high signal. It tells the peripheral device that the previous byte sent by the device is there in the buffer and the microprocessor is yet to read the same. This kind of acknowledgement and information enables the peripheral t<> defer sending the next data byte until the buffer is empty, which is indicated by IBF going low: INTR (Interrupt Request): This is an output signal generated by 8255 in response to IBF, 8TB and INTE (Interrupt enable). This is used to interrupt the microprocessor to read the data byte from the buffer. Compiled by : Dr.. Manoj V.N.V. Page 124

21 INTE: It is an internal flip-flop for enabling or disabling INTR signal. The two flip-flops INTEA and INTEB are set/reset by using the BSR mode. MODE 1 Control word and status-words: To configure port A and port B as input ports, the mode 1 control word is as follows. The status word is constituted by port C bits. When the microprocessor reads port C, the status word is placed in accumulator. Then the microprocessor can examine the bits to determine the status. The status word is shown below. Fig: STATUS WORD MODE 1 MODE 1 Output Control Signals: When port A and/or port B are configured as output ports, both of them use bits from port C as handshake signals. These handshake signals -are as follows, and are shown in below. Fig : Mode 1 Output Configuration Compiled by : Dr.. Manoj V.N.V. Page 125

22 OBF: (Output Buffer Full) -This is an active low signal generated by 8255A to indicate to the peripheral that the microprocessor has written one byte of data into the output port and that it is ready to be read by the device from the port. ACK: (Acknowledge): This is an input signal from the peripheral to 8255, indicating that it has received the byte from the port. It is active low. INTR: (Interrupt Request) - This is an output signal generated by It is set by OBF, ACK and 1NTE. It can be used to interrupt the MPU for the next data byte. INTE: (Interrupt Enable): This is an internal flip-flop to enable interrupts. The two flip-flows INTEA and INTEB are controlled by the bits PC6 and PC2 respectively through BSR mode. PC4, PC5: These two lines can be setup either as input or output. Fig: Control Word Fig: Status Word Example: Analyze the interface circuit shown in the figure. Find the port addresses. Write initialization instructions to set up port A as input port, and Port B as output Port. Write a printer subroutine to output characters that are stored in memory. Compiled by : Dr.. Manoj V.N.V. Page 126

23 Fig: Interfacing the 8255A in Mode 1 (Strobed input/output) Solution: 1 to Determine Port Address: From the decode logic, we find that CS is connected to the output of the NAND gate. Therefore all the inputs to the NAND gate must be at logic 1 for CS to be low. A7 A6 A5 A4 A3 A2 Al A =>(FC)H PortA =>(FD)H Port B =>(FE)H Port C =>(FF)H CONTL REG. We find from the circuit diagram that Port A is configured as input port for keyboard in mode 1 and that Port B is configured as output Port for printer in mode 1. Looking at the handshake signals, we observe that, the keyboard is interfaced for Interrupt I/O and the printer is interfaced for status check I/O. To write initialization instruction, we need to determine.the control word to set up C port A for input and Port B for output in mode 1. The BSR control word to set lnte A. The status word to check OBF B B line. These are determined as follows: 1. Control word: D7 D6 D5 D4 D3 D2 D1 D0 Compiled by : Dr.. Manoj V.N.V. Page 127

24 x 1 0 x = B4H 2. BSR Control word to set INTE A : INTEA is controlled by PC 4. To set PC4, the control word in BSR mode is: D7 D6 D5 D4 D3 D2 D1 D0 0 X X X x = 09H 3. Status Word to Check OBF B : B OBFB is indicated by PC 1. Therefore, the masking byte to check PC 1 is: D7 D6 D5 D4 D3 D2 D1 D = 02H Now the Initialization instructions and, the printer subroutine are as follows. Driver Program (Will be discussed in the class) Stepper motor control system: The stepper motors are popularly used in computer peripherals1 plotters1 printers1 robots1 and machine tools for precise incremental rotation. In stepper motor 1 the stator windings are excited by electrical pulses and for each pulse the motor shaft advances by one angular step. The step size in motor is determined by the number of poles in the rotor and the number of pairs of stator windings (One pair of stator winding is called one phase). The stator windings are also called control windings. Switching ON/OFF the control winding controls the motor. The popular stepper motor used for demonstration in laboratories has a step size of 1.8 degree (i.e. 200 steps for resolution). This motor consists of four-stator winding and requires four switching sequences as shown below. By altering the switching sequence, the motor can be made to run with incremental motion of half the full-step value. Compiled by : Dr.. Manoj V.N.V. Page 128

25 Clock wise rotation PA3 PA2 PA1 PA Anti clock wise rotation PA3 PA2 PA1 PA Another Standard Stepper Motor s Excitation Sequence PA3 PA2 PA1 PA0 HEX A Table: Shows two standard excitation sequences for stepper motors. The second one is followed for our discussions. A typical stepper motor control system is shown in fig. This is 2-phase four winding stepper motor. The system consists of 8085 microprocessor as CPU, EPROM and RAM memory for program and data storage for stack. Using Intel 8279, a keyboard and six numbers of 7-segment LED displays have been interfaced in the system. Though the keyboard operator can issue commands to control the system. The LED displays have been provided to display messages to the operator. The windings of stepper motor are connected to the collector of Darlington pair transistor. The transistors are switched ON (OFF by the microprocessor through the ports of 8255 and buffer (74LS245). A free wheeling diode is connected across each winding for fast switching. The processor has to out put a switching sequence and wait for the 1 to 5 mille seconds before sending the next switching sequence. A typical stepper motor control system is shown in fig below. The system consists of 8085 microprocessor as CPU, EPROM and RAM memory for program & data storage and for stack. Using INTEL 8279, a keyboard and six number of 7-segment LED display has been interfaced in the system. Through the keyboard the operator can issue commands to control the system. The LED display has been provided to display messages to the operator. Compiled by : Dr.. Manoj V.N.V. Page 129

26 The windings of stepper motor are connected to the collector of Darlington pair transistors. The transistors are switched ON/OFF by the microprocessor through the ports of 8255 and buffer (74LS245). A free-wheeling diode is connected across each winding for fast switching. Fig: 8085 Microprocessor Based Stepper Motor Control System Fig: Flow Chart for the Stepper Motor Control Program Compiled by : Dr.. Manoj V.N.V. Page 130

27 Traffic light control system: The traffic lights placed at the road crossing can be automatically switched ON/OFF in the desired sequence using the microprocessor system. The system can also have a manual control option, so that during heavy traffic the operator can vary the duration of ON/OFF time. The system has been developed using 8085 as CPU. The system has EPROM memory for system program storage and RAM memory for stack operation. For manual control a keyboard have been provided. It will be helpful for the operator if the direction of the traffic flow is displayed during manual control. Hence the 7- segment LED's are interfaced to display the direction of traffic flow both during manual and automatic mode. The primary function of the microprocessor in the system is to switch ON/OFF the Red/Yellow/Green lights in the specified sequence. The LED's are interfaced to the system through the buffer (74 LS245) and ports of In the practical implementation schema the lights can be turned ON/OFF using driver transistors and relays. In practical implementation the output of buffer can be connected to -the driver transistor. A relay placed at the collector of the transistor can be used to switch ON/OFF the lights. The microprocessor sends HIGH through a part line to switch on the light and low to switch off the light. A switching schedule is can be developed as shown in fig. In this switching sequence it is assumed that the traffic is allowed in one direction at a time. '1' represents ON condition and "0" represents OFF condition. These one's and zero's can be directly output to 8255 ports to switch ON/OFF the light. The processor can output the codes for switching the lights for schedulel and then waits. After a specified time delay the processor output the codes for schedule-ii. For each schedule the processor can wait for specified time. After the schedule-xii, the processor can again returned to schedule-i. On observing The Compiled by : Dr.. Manoj V.N.V. Page 131

28 schedule we can conclude those three different delay routines is sufficient for implementing the twelve switching schedules. Fig: 8085 Microprocessor Based Traffic Control Demonstration System The systems can be designed using or without using the FR and FL lights ( FR- Free Right, FL- Free Left). The time delays between the sequences have to be chosen as per the traffic and also based on the traffic rules of the country. In an actual system the output of the ports are connected to a powerful relay circuit which drives high current lights which can be viewed from a far distance. Compiled by : Dr.. Manoj V.N.V. Page 132

29 Fig: Relay connection to each of the 230 V Lights ( Traffic Control System) Fig: Switching Schedule for Traffic Lights( With FR and FL) Note: The programs with FR/FL and without FR/FL will be discussed in the class. The programs have to be written for both 8085 and 8086 based systems. This can be implemented using Microcontrollers also. Temperature control system: The microprocessor base temperature control system can be used for automatic control of the temperature of a boiler. The system consists of 8085 as a CPUr EPROM, and RAM memory for programming and data storage. Intel 8279 for key board and display interface, ADC, DAC, INTEL 8255 for I/O ports, Amplifiers, Signal conditioning circuit, temperature sensor and supply control circuit. In this system controlling the power input to the heating element controls the temperature. Compiled by : Dr.. Manoj V.N.V. Page 133

30 The system has been designed to accept the desired temperature and various control commands through the keyboard. The 7-segment display has been provided to display the temperature of the boiler at any time. The temperature of the body is measured using a temperature sensor that can be used for temperature measurements are Thermo-couples, Thermistors, PN junctions, IC sensors like AD 590. These sensors will convert the input temperature to proportional analog voltage or current. The output signal of the sensor will be a weak signal and so it has to be amplified using high input impedance op-amp. Then the analog signal is scaled to suitable level by the signal conditioning circuit. The microprocessor can process only digital signals and so the analog signal from signal conditioning circuit cannot read by the processor directly. The system has an analog-to-digital converter (ADC) to convert the analog signal to proportional digital data. In this system the ADC is interfaced to 8085 microprocessor through port-a of The 8085 processor send signal to ADC to start conversion and at the end 0 conversion it read the digital data from the port-a of The 8085 processor calculates the actual temperature using the input data and displays it on the 7-segment LED. Also, the processor compares the desired temperature with actual temperature (the operator can enter the desired temperature through the keyboard) and calculate the error that is the difference between actual temperature and desired temperature. Compiled by : Dr.. Manoj V.N.V. Page 134

31 Serial Communication and USART 8251 To handle the data transfer between computer to computer and computer to other input and output device a dedicated peripheral is required. The peripheral should be designed in such a fashion that it can reduce the load on microprocessor and it should support both synchronous and asynchronous data transfer handling features. For this purpose a dedicated chip is developed by the Intel Corporation is called programmable serial communication interface Serial Data Transmission Methods and Standards: RS-232. Although the parallel port is slowly gaining acceptance as a peripheral communication port, early PCs used the parallel port almost exclusively for local printers. As more and more peripherals became available for the PC, alternative methods of communication were required that were ill-suited for parallel connections at the time. The Electronics Industry Association (EIA) developed a standard for serial communication. Instead of sending eight bits at a time over a set of data lines, only two data lines were used: one to transmit data and one to receive data. The EIA denoted its serial standard as RS-232 (or simply the serial port). A serial port offers several distinct advantages over early parallel ports. First, the serial port was designed to be bi-directional, right from the start. This made serial the preferred method for interactive devices, such as modems, mice, etc. Second, the serial port used fewer physical signal lines than the parallel port. This made cabling less expensive and reduced potential connector problems. Where a printer cable is generally limited to two meters in length, a serial cable can easily exceed 60 meters. This difference opened the way for basic local networking. A serial port must be capable of several important operations. It must convert parallel data from the PC system bus into a sequence of serial bits, add the appropriate framing bits (which might be changed for different serial connections), then provide each if those bits to the data line at the proper rate. The serial port must also work in reverse, accepting serial data at a known rate, Compiled by : Dr.. Manoj V.N.V. Page 135

32 stripping off the framing bits, converting the serial data bits back into bus form, and checking blocks of data for accuracy. The heart of the serial port is a single IC the Universal Synchronous Asynchronous Receiver/Transmitter (USART). The UART connects directly to the PC bus architecture either added to the motherboard or incorporated on an expansion board. A UART IC contains all of the internal circuitry necessary to process, transmit, and receive data between the serial line and the PC bus. Fig : The RS-232 Interface Cards Since the UART is programmable, its configuration (i.e., framing format and baud rate) can be set through DOS or Windows communication software. All data output, data input, and handshaking signals needed by the serial port are generated within the UART itself. It is interesting that the UART is powered by +5 Vdc only, just like any other ASIC in the system. This means that data and handshaking signals entering and leaving the UART are all TTLcompatible. Transmitted data is converted to bi-polar signals through a line-driver IC. Bipolar data that appears on the receive line is converted back to TTL levels through a liner receiver IC. All that remains is the port connector itself. The original serial-port design used a 25-pin male sub-miniature D-type connector, but newer ports have abandoned the extra handshaking signals to accommodate a 9-pin male sub-miniature D-type connector. Compiled by : Dr.. Manoj V.N.V. Page 136

33 IBM and compatible PCs implement a serial port as either a 25-pin or 9-pin subminiature D-type connector (Fig. 40-3). Both ends of the serial cable are identical. Be concerned with three types of signals in a serial connection: data lines, control (or handshaking) lines, and ground lines. Table 40-3 identifies the name and description of each conductor for both 25-pin and 9-pin serial connections. Remember that all data and control signals on the serial port are bi-polar. Fig: The Serial Port Pins and Signals TX AND RX Rx and Tx are simply the data lines into and out of the port. Tx is the Transmit line, which outputs serial data from the PC, and Rx is the Receive line, which accepts serial data from the serial peripheral. RTS AND CTS The RTS (Request to Send) signal is generated by the DTE. When asserted, it tells the DCE (i.e., the modem) to expect to receive data. However, the DTE can t just dump data to DCE. The DCE must be ready to receive the data, so after the RTS Compiled by : Dr.. Manoj V.N.V. Page 137

34 line is asserted, the DTE waits for the CTS (Clear to Send) signal back from the DCE. Once the DTE receives a valid CTS signal, it can begin transferring data. This RTS/CTS handshake forms the basis for data flow control. DTR AND DSR When the DTE is turned on or initialized and ready to begin serial operation, the DTR (Data Terminal Ready) line is asserted. This tells the DCE (i.e., modem) that the DTE (i.e., computer) is ready to establish a connection. When the DCE has initialized and is ready for a connection, it will assert the DSR (Data Set Ready) line back to the DTE. Once the DTE is ready and recognizes the DSR signal, a connection is established. This DTR/DSR handshake is established only once when the DTE and DCE devices are first initialized, and it must remain active throughout the connection. If either the DTR or DSR signal should fall, the communication channel will be interrupted (and the RTS/CTS handshake will no longer have any effect). DCD The DCD (Data Carrier Detect) signal is particularly useful with modems. It is produced by the DCE when a carrier is detected from a remote target, and the DCE is ready to establish a communications pathway. The DCD signal is then sent back to the DTE. Once the DCD line is asserted, it will remain so as long as a connection is established. RI The RI (Ring Indicator) signal is asserted by the DCE, and is also particularly useful with modems. It is produced by the DCE when a telephone ring is detected. This becomes a vital signal if it is necessary for a remote user to call in and access your computer (i.e., a BBS configuration) Progammable Communication Interface The 8251 A is a programmable chip designed for synchronous and asynchronous serial data communication, packaged in.a 28-pin DIP. The 8251A is the enhanced version of its predecessor, the and is compatible with the Figure Compiled by : Dr.. Manoj V.N.V. Page 138

35 shows the block diagram of the 8251A. It includes five sections: Read/Write Control Logic, Transmitter, Receiver, Data Bus Buffer, and Modem Control. The control logic interfaces the chip with the MPU, determines the functions of the chip according to the control word in its register (to be explained below), and monitors the data flow. The transmitter section converts a parallel word received from the MPU into serial bits and transmits them over the TxD line to a peripheral. The receiver section receives serial bits from a peripheral, converts them into a parallel word, and transfers the word to the MPU. The modem control is used to establish data communication through modems over telephone lines. Fig : 8251 Block Diagram Compiled by : Dr.. Manoj V.N.V. Page 139

36 The 8251A is a complex device, capable of performing various functions. The asynchronous mode is often used for data communication between the MPU and serial peripherals such as terminals and floppy disks. Figure above shows an expanded version of the 8251A block diagram. The block diagram shows all the elements of a programmable chip; it includes the interfacing signals, the control register, and the status register. The functions of various blocks are described below. READ/WRITE CONTROL LOGIC AND REGISTERS This section includes R/W control logic, six input signals, control logic, and three buffer registers: data register, control register, and status register. The input signals to the control logic are as follows. Input Signals CS-Chip Select: When this signal goes low, the 8251 A is selected by the MPU for communication. This is usually connected to a decoded address bus. C/D-Control/Data: When this signal is high, the control register or the status register is addressed; when it is low, the data buffer is addressed. The control register and the status register are differentiated by WR: and RD signals, respectively. WR-Write: When this signal goes low, the MPU either writes in the control register or sends output to the data buffer. This is connected to row or MEMW. Compiled by : Dr.. Manoj V.N.V. Page 140

37 RD-Read: When this signal goes low, the MPU either reads a status from the status register or accepts (inputs) data from the data buffer. This is connected to either IOR or MEMR. RESET -Reset: A high on this input resets the 8251A and forces it into the idle mode. CLK-Clock: This is the clock input, usually connected to the system clock. This clock does not control either the transmission or the reception rate. The clock is necessary for communication with the microprocessor. Control Register This 16-bit register for a control word consists of two independent bytes: the first byte is called the mode instruction (word) and the second byte is called command instruction (word). This register can be accessed as an output port when the C/D pin is high. Status Register This input register checks the ready status of a peripheral. This register is addressed as an input port when the C/D pin is high; it has the same port address as the control register. Data Buffer This bidirectional register can be addressed as an input port and an output port when the CID pin is low. Table 16.4 summarizes all the interfacing and control signals. TRASMITTER SECTION Compiled by : Dr.. Manoj V.N.V. Page 141

38 The transmitter accepts parallel data from the MPU and converts them into serial data. It has two registers: a buffer register to hold eight bits and an output register to convert eight bits into a stream of serial bits. The MPU writes a byte in the buffer register; whenever the output register is empty the contents of the buffer register are transferred to the output register. This section transmits data on the TxD pin with the appropriate framing bits (Start and Stop). Three output signals and one input signal are associated with the transmitter section. Fig: Expanded Block Diagram of Control Logic and Registers Compiled by : Dr.. Manoj V.N.V. Page 142

39 TxD- Transmit Data: Serial bits are transmitted on this line. TXC- Transmitter Clock: This input signal control~ the rate at which bits are transmitted by the USART. The clock frequency can be I, 16, or 64 times the baud. TxRDY -Transmitter Ready: This is an output signal. When it is high, it indicates that the buffer register is empty and the USART is ready to accept a byte. It can be used either to interrupt the MPU or to indicate the status. This signal is reset when a data byte is loaded into the buffer. TxE- Transmitter Empty: This is an output signal. Logic 1 on this line indicates that the output register is empty. This signal is reset when a byte is transferred from the buffer to the output registers. fig: Expanded Block Diagram of Transmitter and Receiver Sections RECEIVER SECTION The receiver accepts serial data on the RxD line from a peripheral and converts them into parallel data. The section has two registers: the receiver input register and the buffer register. When the RxD line goes low, the control logic assumes it is a Start bit; waits for half a bit time, and samples the line again. If the line is still low, the input register Compiled by : Dr.. Manoj V.N.V. Page 143

40 accepts the following bits, forms a character, and loads it into the buffer register. Subsequently, the parallel byte is transferred to the MPU when requested. In the asynchronous mode, two input signals and one output signal are necessary, as described below. RxD-Receive Data: Bits are received serially on this line and converted into a parallel byte in the receiver input register. RXC-Receiver Clock: This is a clock signal that controls the rate at which bits are received by the USART. In the asynchronous mode, the clock can be set to I, 16, or 64 times the baud. RxRDY -Receiver Ready: This is an output signal. It goes high when the USART has a character in the buffer register and is ready to transfer it to the MPU. This line can be used either to indicate the status or to interrupt the MPU. INITIALIZING THE 8251A Fig (a) : Mode Word Format (b) Command Word Format Compiled by : Dr.. Manoj V.N.V. Page 144

41 To implement serial communication, the MPU must inform the 8251A of all details, such as mode, baud, Stop bits, parity, etc. Therefore, prior to data transfer, a set of control words must be loaded into the 16-bit control register of the 8251A. In addition, the MPU must check the readiness of a peripheral by reading the status register. The control words are divided into two formats: mode words and command words. The mode word specifies the general characteristics of operation (such as baud, parity, number of Stop bits), the command word enables data transmission and/or reception, and the status word provides the information concerning register status and transmission errors. Fig : The status Word Format To initialize the 8251A in the asynchronous mode, a certain sequence of control words must be followed. After a Reset operation (system Reset or through instruction), a mode word must be written in the control register followed by a command word. Any control word written into the control register immediately Compiled by : Dr.. Manoj V.N.V. Page 145

42 after a mode word will be interpreted as a command word; that means a command word can be changed anytime during the operation. However, the 8251A should be reset prior to writing a new mode word, and it can be reset by using the Internal Reset bit (D6) in the command word. Interfacing an RS-232 Terminal Using the 8251A PROBLEM STATEMENT 1. Identify the port addresses of the control register, the status register, and the data register in Figure 2. Explain the RS-232 signals and the operations of the line driver (MC 1488) and the line receiver (MC 1489) shown in the figure below. Fig: Interfacing an RS-232 Terminal with an 8085 system using Specify the initialization instructions and the status word to transmit characters with the following parameters if the transmitter clock frequency (TxC) is khz. Asynchronous mode with 9600 baud Character length = seven bits and two Stop bits No parity check Compiled by : Dr.. Manoj V.N.V. Page 146

43 4. Write instructions to initialize the 8251A to read the status word, and set up a loop until the transmitter (TxRDY) is ready. PORT ADDRESS a. The Chip Select line of the 8251A is enabled when the address lines A7 through Al are at logic 1. To select the control register or the status register, the cif5 line should be high, which means that address line Ao should be 1. Therefore, the port address of the control register and the status register = FFH. The control register is an output port and the status register is an input port; they are identified by WR and RD signals, even if their port addresses are the same. b. The data register is selected when the cif5 line goes low; thus, Ao should be low. The port address of the data register = FEH. The register i~ bidirectional, and the same address is used to receive or transmit data. The input and output functions are identified by RD and WR signals. 2. RS-232C Signals, LINE DRIVERS, AND LINE RECEIVERS Figure shows that three RS-232 signals- TxD, RxD, and Ground-are being used for serial communication between the CRT terminal and the 8085 system. The terminal transmits data on pin 2 and receives on pin 3; on the other hand, the 8085 system receives on pin 2 and transmits on pin 3 using the 8251A. Therefore, the terminal is connected as the DTE and the system plays the role of the DCE; the 8251A is part of the 8085 system. Data transmitted over the TxD line (pin 19 of the 8251A) are at the 1TL logic level. These bits are converted to RS-232 voltage levels and negative logic by line driver MC Data received by the 8251A over the RxD line (pin 3) should be at the 1TL logic level. Therefore, the RS-232 signals at pin 2 of the connector are converted to the positive logic level by line receiver MC The line driver and receiver are described here briefly. Line Driver: MC This is a quad line driver that converts TTL input levels to a maximum + 15 Voc output signal. Typically, it is used with t 12 V power supply. For logic 0 input (< 0.8 V DC ) the output is around + 10 V, and for logic I Compiled by : Dr.. Manoj V.N.V. Page 147

44 input ( > +2.4 V DC ) the output is around -10 V; thus, the positive true logic is converted into negative true logic for RS-232C signals. The internal circuit of the MC 1488 functions much like a comparator. For an input lower than the threshold voltage, the output approaches positive power supply voltage, and for an input higher than the threshold voltage, the output approaches negative power supply voltage. Line Receiver: MC 1489 this is a quad line receiver that converts high voltage signals (+ 15 V) into TTL logic levels. Output voltages usually range from 0.2 V (low) to 4.0 V (high). The internal circuit functions as an on/off transistor. When the transistor base has a negative input voltage, the transistor is turned off and the collector voltage (the output of the MC 1489) is high. When the transistor base has a positive input voltage, the transistor is driven into saturation to 0.2 V. TIALIZATION The control words necessary for the given specifications are as follows: Mode Word = CAH Stop Bits Parity Character = k/16 Command Word = 11H Status Word = 01H Programmable Interval Timer (8253) The Intel 8253 is a programmable counter / timer chip designed for use as an Intel microcomputer peripheral. It uses nmos technology with a single +5V supply and is packaged in a 24-pin plastic DIP. It is organized as 3 independent 16-bit counters, each with a counter rate up to 2 MHz. All modes of operation are software programmable. The 82C54 is pin compatible with the HMOS 8254, and is a superset of the Compiled by : Dr.. Manoj V.N.V. Page 148

45 Block diagram I'll examine the block diagram and next we'll explore the internal registers and operating modes of this device. Take note, the timer has three independent, programmable counters and they are all identical. Six programmable timer modes allow the 82C54 / 8253 to be used as an event counter, elapsed time indicator, programmable one-shot, and in many other applications. The block labeled data bus buffer contains the logic to buffer the data bus to / from the microprocessor, and to the internal registers. The block labeled read / write logic controls the reading and the writing of the counter registers. The final block, the control word register, contains the programmed information that is sent to the device from the microprocessor. In effect this register defines how the 8253 logically works. Each counter in the block diagram has 3 logical lines connected to it. Two of these lines, clock and gate, are inputs. The third, labeled OUT is an output. The function of these lines changes and depends on how the device is initialized or programmed. Compiled by : Dr.. Manoj V.N.V. Page 149

46 PIN configuration The following picture shows the pin configuration of the 8253 and a general definition of the lines follows: Clock This is the clock input for the counter. The counter is 16 bits. The maximum clock frequency is 1 / 380 nanoseconds or 2.6 megahertz. The minimum clock frequency is DC or static operation. Out This single output line is the signal that is the final programmed output of the device. Actual operation of the out line depends on how the device has been programmed. Gate This input can act as a gate for the clock input line, or it can act as a start pulse, depending on the programmed mode of the counter. Signal Low or going low Rising High Status Mode 0 Disables counting - - Enables counting ) Initiates - - counting 2) Resets output after next clock 2 1) Disables counting 2) Sets output immediately high 1) Reloads counter 2) Initiates Enables counting 3 1) Disables counting 2) Sets output immediately high counting Initiates counting Enables counting 4 Disables counting - - Enables counting Initiates counting - - Compiled by : Dr.. Manoj V.N.V. Page 150

47 Internal 8253 registers Here is a list of the internal 8253 registers that will program the internal counters of the 8253: RD WR A0 A1 function COUNTER Load counter Read counter 0 COUNTER Load counter Read counter 1 COUNTER Load counter Read counter 2 MODE WORD or Write mode CONTROL WORD word No-operation Counter #0, #1, #2 Each counter is identical, and each consists of a 16-bit, presettable, down counter. Each is fully independent and can be easily read by the CPU. When the counter is read, the data within the counter will not be disturbed. This allows the system or your own program to monitor the counter's value at any time, without disrupting the overall function of the Control Word Register This internal register is used to write information to, prior to using the device. This register is addressed when A0 and A1 inputs are logical 1's. The data in the register controls the operation mode and the selection of either binary or BCD ( binary coded decimal ) counting format. The register can only be written to. You can't read information from the register. Control Word Register All of the operating modes for the counters are selected by writing bytes to the control register. This is the control word format. Bits D7 and D6 are labeled SC1 and SC0. These bits select the counter to be programmed, it is necessary to define, using the control bits D7 and D6, which counter is being set up. Compiled by : Dr.. Manoj V.N.V. Page 151

48 Once a counter is set up, it will remain that way until it is changed by another control word. CONTROL BYTE D7 - D0 D7 D6 D5 D4 D3 D2 D1 D0 SC1 SC0 RL1 RL0 M2 M1 M0 BCP D7 D6 Counter Select SC1 SC0 0 0 counter counter counter illegal value D5 D4 R / L Definition RL1 RL0 0 0 Counter value is latched. This means that the selected counter has its contents transferred into a temporary latch, which can then be read by the CPU. 0 1 Read / load least-significant byte only. 1 0 Read / load most-significant byte only. 1 1 Read / load least-significant byte first, then most-significant byte. Bits D5 and D4 ( RL1 / RL0 ) of the control word shown above are defined as the read / load mode for the register that is selected by bits D7 and D6. Bits D5 and D4 define how the particular counter is to have data read from or written to it by the CPU. These bits are defined as: The 1st value,00, is the counter latch mode. If this mode is specified, the current counter value is latched into an internal register at the time of the I/O write operation to the control register. When a read of the counter occurs, it is this latched value that is read. Caution: If the latch mode is not used, then it is possible that the data read back may be in the process of changing while the read is occurring. This could result in invalid data being input by the CPU ( see the timing diagrams to the 8253 by intel's site or go to page "Memory mapped I/O" ). To read the counter value while the counter is still in the process of counting, one must first issue a latch Compiled by : Dr.. Manoj V.N.V. Page 152

49 control word, and then issue another control word that indicates the order of the bytes to be read. An alternative method of obtaining a stable count from the timer is to externally inhibit counting while the register is being read. To this, an external logic to the 8253 controlled by the Z80 to inhibit count during an input read operation is to connect. Each technique has certain disadvantages. The first, the latching method, may give the CPU a reading that is "old" by several cycles, depending on the speed of the count and which byte of the counter is being read. The second method, the external inhibiting function, requires additional hardware. In addition, it may change the overall system operation. The input to counter 0 is MHz. The next 3 bits of the control word are D3, D2, and D1. These bits determine the basic mode of operation for the selected counter. The mode descriptions follows: D3 D2 D1 Mode value M2 M1 M mode 0: interrupt on terminal count mode 1: programmable one-shot x 1 0 mode 2: rate generator x 1 1 mode 3: square wave generator mode 4: software triggered strobe mode 5: hardware triggered strobe The final bit D0 of the control register determines how the register will count: The maximum values for the count in each count mode are 104 ( 10,000 decimal ) in BCD, and 216 ( 65,536 decimal ) in binary. D0 counts down in 0 binary 1 BCD Compiled by : Dr.. Manoj V.N.V. Page 153

50 Programmable Interrupt Controller The Intel 8259 is a family of Programmable Interrupt Controllers (PICs) designed and developed for use with the Intel 8085 and Intel bit and 16-bit microprocessors. The family originally consisted of the 8259, 8259A, and 8259B PICs, though a number of manufactures make a wide range of compatible chips today. The 8259 acts as a multiplexer, combining multiple interrupt input sources into a single interrupt output to interrupt a single device. The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a single a5v supply. Circuitry is static, requiring no clock input. The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has several modes, permitting optimization for a variety of system requirements. The 8259A is fully upward compatible with the Intel Software originally written for the 8259 will operate the 8259A in all 8259 equivalent modes (MCS- 80/85, Non-Buffered, Edge Triggered). Fig: Block Diagram Of 8259 Compiled by : Dr.. Manoj V.N.V. Page 154

51 Pin Description The most common method of servicing such devices is the Polled approach. This is where the processor must test each device in sequence and in effect ``ask'' each Compiled by : Dr.. Manoj V.N.V. Page 155