Hardware Manual PC1630 Coaxlink Mono PC1631 Coaxlink Duo PC1632 Coaxlink Quad PC1633 Coaxlink Quad G3

Transcription

1 Hardware Manual PC630 Coaxlink Mono PC63 Coaxlink Duo PC63 Coaxlink Quad PC633 Coaxlink Quad G3 EURESYS s.a Document version built on

2 Coaxlink Hardware Manual Disclaimer EURESYS s.a. shall retain all property rights, title and interest of the documentation of the hardware and the software, and of the trademarks of EURESYS s.a. All the names of companies and products mentioned in the documentation may be the trademarks of their respective owners. The licensing, use, leasing, loaning, translation, reproduction, copying or modification of the hardware or the software, brands or documentation of EURESYS s.a. contained in this book, is not allowed without prior notice. EURESYS s.a. may modify the product specification or change the information given in this documentation at any time, at its discretion, and without prior notice. EURESYS s.a. shall not be liable for any loss of or damage to revenues, profits, goodwill, data, information systems or other special, incidental, indirect, consequential or punitive damages of any kind arising in connection with the use of the hardware or the software of EURESYS s.a. or resulting of omissions or errors in this documentation.

3 Contents Coaxlink Hardware Manual 3 Contents About This Document... 5 Document Scope... 5 Document Revision History...6 Mechanical Specification... 7 Product Pictures... 7 Dimensions and Weight... 9 Components Location...0 Connectors... CoaXPress Host Connector Indicator Lamps... 8 Board Status Lamp... 0 FPGA Status Lamp... Firmware Recovery Switch... CC Link Cable... PC65 I/O Cable Adapter... 3 Electrical Specification... 5 CoaXPress Host Interface...5 PCI Express Interface... 6 PCI Express End-point... 6 Power Distribution... 8 PCI Express Power Input Auxiliary Power Input...3 System I/O Power Output Specification... 3 System I/O Ports... 3 Differential Input...3 TTL Input/Output...34 Isolated Input Isolated Output...37 Environmental Specification Environmental Conditions...39 Thermal Design... 40

4 4 Coaxlink Hardware Manual Contents CE Compliance (EMC Class B)...40 FCC Compliance (Class B)...4 RoHS Compliance... 4 WEEE... 4

5 About This Document Coaxlink Hardware Manual 5 About This Document Document Scope This document describes the hardware specifications of the following Coaxlink products: Product Code Product Name S/N Prefix Icon 630 Coaxlink Mono KMO Mono 63 Coaxlink Duo KDU Duo 63 Coaxlink Quad KQU Quad 633 Coaxlink Quad G3 KQG Quad G3 Note: The S/N prefix is a 3-letter string at the beginning of the card serial number. Note: Icons are used in this document for tagging titles of card-specific content. The hardware specification document is composed of 3 main sections: The mechanical specification section provides the product pictures, the physical dimensions, the s description and the pin assignments, the lamps description, etc. The electrical specification section provides the electrical characteristics of all input/output ports, a description of the power distribution, power requirements, etc. The environmental specification section provides the climatic requirements and CE/FCC/RoHS/WEEE compliance statements. For a description of the product functionalities, refer to the Coaxlink Functional Guide.

6 6 Coaxlink Hardware Manual About This Document Document Revision History Date Document Version Description First product: Coaxlink Quad Initial version for Coaxlink Driver New products: Coaxlink Mono Coaxlink Duo Change CE/FCC EMC compliance to level B For delivery with Coaxlink Driver version.0 (or higher) Editorial corrections Specification update: Connectors on page : External System I/O : Change the description of pin 5 PCI Express End-point on page 6: Add maximum payload size specification of the PCI Express.0 end-point Specification update: PCI Express Power Input on page 30 Add/revise PCI Express typical power requirements for all cards New product: Coaxlink Quad G3 For delivery with Coaxlink Driver version 4.0 (or higher) Editorial corrections. Add CC Link Cable on page Add PC65 I/O Cable Adapter on page 3

7 Mechanical Specification Coaxlink Hardware Manual 7 Mechanical Specification Mechanical specifications of the product(s) including: product pictures, physical dimensions, s description and pin assignments, lamps description, switches description, etc. Product Pictures PC630 Coaxlink Mono

8 8 Coaxlink Hardware Manual Mechanical Specification PC63 Coaxlink Duo PC63 Coaxlink Quad

9 Mechanical Specification Coaxlink Hardware Manual PC633 Coaxlink Quad G3 Dimensions and Weight Value Unit Card length (excluding bracket and bracket s) mm Card height (including PCI Express ).5 mm PC630 Coaxlink Mono weight 50 grams PC63 Coaxlink Duo weight 60 grams PC63 Coaxlink Quad weight 70 grams PC633 Coaxlink Quad G3 weight 80 grams Characteristic 9

10 0 Coaxlink Hardware Manual Mechanical Specification A/- FPGA status lamp Board status lamp CC link Auxiliary power input Internal I/O External I/O CoaXPress Host indicator lamp Components Location Firmware J4 recovery switch Push pin ( plc s) Fan FP A Heatsink with fan J3 GA CoaXPress Host PCI Express A/B FPGA status lamp Board status lamp Internal I/O CC link Auxiliary power input Internal I/O Firmware J4 recovery switch Push pin ( plc s) Fan 9 mm B Heatsink with fan J3 GA A CoaXPress Host FP External I/O CoaXPress Host indicator lamps PC630 Coaxlink Mono components location PCI Express PC63 Coaxlink Duo components location

11 A/B C/D FPGA status lamp Board status lamp Internal I/O Coaxlink Hardware Manual Auxiliary power input CC link Internal I/O External I/O CoaXPress Host indicator lamps Mechanical Specification B C 9 mm (3 plc s) D Firmware J4 recovery switch Fan GA A Push pin ( plc s) Heatsink with fan J3 FP CoaXPress Host PCI Express A/B C/D FPGA status lamp Board status lamp A B C D CoaXPress Host 9 mm (3 plc s) Internal I/O Internal I/O External I/O CoaXPress Host indicator lamps PC63 Coaxlink Quad components location Auxiliary power input CC link Fan Heatsink with fan J3 Firmware J4 recovery switch FPGA PCI Express PC633 Coaxlink Quad G3 components location Related Links Board Status Lamp on page 0 FPGA Status Lamp on page Firmware Recovery Switch on page Push pin ( plc s)

12 Coaxlink Hardware Manual Mechanical Specification Connectors CoaXPress Host Connector Quad Quad G3 A B C D inner outer CoaXPress DIN4 (4 x DIN.0/.3 female receptacles) Pin Signal A Inner CXP_A A Outer B Inner CXP_B B Outer C Inner CXP_C C Outer D Inner CXP_D D Outer CoaXPress Host Connector Usage CoaXPress Host Connection A CoaXPress Host Connection B CoaXPress Host Connection C CoaXPress Host Connection D Duo A B inner outer CoaXPress DIN ( x DIN.0/.3 female receptacles) Pin Signal A Inner CXP_A A Outer B Inner CXP_B B Outer Usage CoaXPress Host Connection A CoaXPress Host Connection B

13 Mechanical Specification CoaXPress Host Connector Coaxlink Hardware Manual 3 Mono inner outer CoaXPress DIN ( x DIN.0/.3 female receptacle) Pin Signal Inner CXP_A Outer Usage CoaXPress Host Connection A

14 4 Coaxlink Hardware Manual Mechanical Specification External IO Connector pin 3-row high-density female sub-d Pin Signal Usage DIN+ High-speed differential input # Positive pole 3 IIN+ Isolated input # Positive pole 4 IIN3- Isolated input #3 Negative pole 5 IIN4- Isolated input #4 Negative pole 6 IOUT- 7 Isolated contact output # Negative pole Not connected DIN- High-speed differential input # Negative pole IIN- Isolated input # Negative pole 3 IIN+ Isolated input # Positive pole 4 IIN3+ Isolated input #3 Positive pole 5 IIN4+ Isolated input #4 Positive pole 6 IOUT+ Isolated contact output # Positive pole 7 TTLIO TTL input/output # 8 9 DIN- High-speed differential input # Negative pole 0 DIN+ High-speed differential input # Positive pole IIN- IOUT- Isolated contact output # Negative pole 3 IOUT+ Isolated contact output # Positive pole 4 5 TTLIO TTL input/output # 6 +V + V Power output Isolated input # Negative pole

15 Mechanical Specification Coaxlink Hardware Manual 5 Internal IO Connector pin dual-row 0." pitch pin header with shrouding Pin Signal Usage 3 DIN+ High-speed differential input # Positive pole 4 DIN- High-speed differential input # Negative pole 5 DIN+ High-speed differential input # Positive pole 6 DIN- High-speed differential input # Negative pole 7 IIN+ Isolated input # Positive pole 8 IIN- Isolated input # Negative pole 9 IIN+ Isolated input # Positive pole 0 IIN- Isolated input # Negative pole IIN3+ Isolated input #3 Positive pole IIN3- Isolated input #3 Negative pole 3 IIN4+ Isolated input #4 Positive pole 4 IIN4- Isolated input #4 Negative pole 5 IOUT+ Isolated contact output # Positive pole 6 IOUT- Isolated contact output # Negative pole 7 IOUT+ Isolated contact output # Positive pole 8 IOUT- Isolated contact output # Negative pole 9 TTLIO TTL input/output # 0 TTLIO TTL input/output # Not connected V + V Power output 6 +V_RTN

16 6 Coaxlink Hardware Manual Internal IO Connector Duo Mechanical Specification Quad Quad G pin dual-row 0." pitch pin header with shrouding Pin Signal Usage 3 DIN+ High-speed differential input # Positive pole 4 DIN- High-speed differential input # Negative pole 5 DIN+ High-speed differential input # Positive pole 6 DIN- High-speed differential input # Negative pole 7 IIN+ Isolated input # Positive pole 8 IIN- Isolated input # Negative pole 9 IIN+ Isolated input # Positive pole 0 IIN- Isolated input # Negative pole IIN3+ Isolated input #3 Positive pole IIN3- Isolated input #3 Negative pole 3 IIN4+ Isolated input #4 Positive pole 4 IIN4- Isolated input #4 Negative pole 5 IOUT+ Isolated contact output # Positive pole 6 IOUT- Isolated contact output # Negative pole 7 IOUT+ Isolated contact output # Positive pole 8 IOUT- Isolated contact output # Negative pole 9 TTLIO TTL input/output # 0 TTLIO TTL input/output # Not connected V + V Power output 6 +V_RTN

17 Mechanical Specification Coaxlink Hardware Manual 7 CC Link Connector pin dual-row 0." pitch pin header with shrouding Pin Signal CSync 3 4 CSync 5 6 CSync3 Usage Card-to-card synchronization bus Signal Card-to-card synchronization bus Signal Card-to-card synchronization bus Signal 3 Auxiliary Power Input Connector pin PCI Express x6 Graphics 50W ATX power socket Pin Signal Usage +VIN Auxiliary + V input +VIN Auxiliary + V input 3 +VIN Auxiliary + V input 4 5 SenseIN 6 Power source presence detection

18 8 Coaxlink Hardware Manual Mechanical Specification CoaXPress Host Connector Indicator Lamps Each of the CoaXPress Host Interface is associated with a CoaXPress Host Indicator Lamp. CoaXPress Host Connector Indicator Lamps Locations CoaXPress Host indicator lamps External I/O CoaXPress Host A A PC630 Coaxlink Mono bracket CoaXPress Host indicator lamps External I/O B A CoaXPress Host A B PC63 Coaxlink Duo bracket CoaXPress Host indicator lamps External I/O B D A C CoaXPress Host A B C D PC63 Coaxlink Quad bracket CoaXPress Host indicator lamps B D A C External I/O CoaXPress Host A B C PC633 Coaxlink Quad G3 bracket D

19 Mechanical Specification Coaxlink Hardware Manual 9 CoaXPress Host Connector Indicator Lamps States Lamp State Symbol Meaning Off The Coaxlink card is not powered Solid orange System booting Slow pulse red The Coaxlink card is powered, but nothing connected to the CoaXPress Host Fast flash alternate green / orange The connection detection is in progress; PoCXP is active. Fast flash orange The connection detection is in progress; PoCXP is off. This state is shown for a minimum of s even if the connection detection is faster This state is shown for a minimum of s even if the connection detection is faster Slow flash alternate red / green Slow flash alternate red / orange The Device and the Host are incompatible; PoCXP is active. + The Device and the Host are incompatible; PoCXP is off. + Solid red The PoCXP over-current protection has tripped. Solid green The Device to Host connection is established, but no data being transferred Slow pulse orange The Device to Host connection is established, but the Host is waiting for a trigger. Fast flash green. The Device to Host connection is established and image data is being transferred 500ms red pulse One (or more) transmission errors (e.g. CRC error, single bit error detected) occurred during data transfer. In case of multiple errors, there shall be at least two green fast flash pulses before the next error is indicated Slow flash alternate green / orange The Host is sending connection test packets to the Device. +

20 0 Coaxlink Hardware Manual Mechanical Specification Symbol Lamp State Meaning System error (e.g. internal error) Fast flash red Flashing Lamp States Timing Definitions Timing Indication Fast duty cycle: 0 ms on, 60 ms off Fast flash alternate (color /color duty cycle: 0 ms on (color ), 60 ms off, 0 ms on (color ), 60 ms off Slow flash duty cycle: second on, second off Slow pulse (red orange) 0% duty cycle: 00ms on, 800ms off 500 ms pulse 500 ms on Board Status Lamp Board status lamp indicator states Lamp state Off Symbol Meaning No power. The board is not powered or the power distribution network is not functional. Solid green Board status OK. Solid red Board status NOK. The main power distribution network is operational and the FPGA start-up procedure has successfully completed. Possible causes are: There is no power delivered on the + V rail of the PCI Express slot The FPGA start-up procedure is not completed. The normal completion time is around 00 milliseconds. At least one power converter of the main power distribution network is unable to operate properly. This might be caused by excessive temperature due to inadequate board cooling, accidental short-circuits having blown one (or more) protection fuses, inappropriate supply voltages, etc. Related Links Components Location on page 0

21 Mechanical Specification Coaxlink Hardware Manual FPGA Status Lamp FPGA status lamp indicator states Lamp state Symbol Meaning Off Board not powered. Solid green FPGA status OK. Solid red FPGA status NOK. All the FPGA clock networks and the DDR memory are operating normally. Possible causes are: At least one FPGA clock network is not operating normally. This might be caused by excessive jitter on external clock signals of the CoaXPress or the PCI Express interfaces. The DDR memory controller has not been able to successfully perform the calibration procedure. Related Links Components Location on page 0 Firmware Recovery Switch Firmware recovery switch positions Meaning Switch position Normal mode. (Factory default) OR At next power on, the FPGA will boot with the latest uploaded firmware. Recovery mode. At next power on, the FPGA will boot with the last but one uploaded firmware. Note: The recovery mode must be used only in case of emergency situations: i.e. when the latest uploaded firmware is not functional and the card is no more detected by the Host PC. Refer to the Coaxlink functional guide for a description of the firmware recovery procedure. Related Links Components Location on page 0

22 Coaxlink Hardware Manual Mechanical Specification CC Link Cable Cable length Polarization key 6 wires 0." 0.05" Connector pitch Pin If the application requires the synchronization of multiple cameras attached to multiple cards, it is mandatory to assemble and install a CC link cable to establish the card to card bus connections. Cable Assembly Instructions The CC link cable is not supplied with the Coaxlink card; it must be built, according, to the application needs, with: A piece of a 6-conductor 0.05-in pitch ribbon cable. For instance: Belden s (9L80XX Series) Two or more pieces of a x 3-pin female ribbon cable s. For instance: TE connectivity The CC link cable has: A maximum of 4 s allowing up to 4 cards to share the same CC link. A maximum length of 30 cm. The pitch(es) must be determined according to the actual card to card spacing in the Host PC. Cable Installation The CC link female s must be inserted into the CC link pin header of the participating Coaxlink cards. Note: Interconnecting Coaxlink cards not belonging to the same PC motherboard is currently not supported!

23 Mechanical Specification Coaxlink Hardware Manual 3 PC65 I/O Cable Adapter Internal I/O External I/O 00 mm 5-pin Sub-D female 6-conductor.05" pitch ribbon cable 6-pin dual-row."-pitch IDC female Standard profile PC bracket The PC65 I/O Cable Adapter connects all the pins (but the pin ) of a 6-pin dual-row 0." pitch to a 5pin Sub-D fitted into a standard-profile PC bracket. When used,with the Internal IO of a Coaxlink Duo, Quad or Quad G3 card, it connects the second half of System I/O lines to a second External I/O.

24 4 Coaxlink Hardware Manual Mechanical Specification The pin assignments are as follows: Internal IO External IO Pin # Pin # Signal Usage 3 4 DIN+ High-speed differential input # Positive pole 4 DIN- High-speed differential input # Negative pole 5 5 DIN+ High-speed differential input # Positive pole 6 3 DIN- High-speed differential input # Negative pole 7 6 IIN+ Isolated input # Positive pole 8 4 IIN- Isolated input # Negative pole 9 7 IIN+ Isolated input # Positive pole 0 5 IIN- Isolated input # Negative pole 8 IIN3+ Isolated input #3 Positive pole 6 IIN3- Isolated input #3 Negative pole 3 9 IIN4+ Isolated input #4 Positive pole 4 7 IIN4- Isolated input #4 Negative pole 5 0 IOUT+ Isolated contact output # Positive pole 6 8 IOUT- Isolated contact output # Negative pole 7 IOUT+ Isolated contact output # Positive pole 8 9 IOUT- Isolated contact output # Negative pole 9 TTLIO TTL input/output # TTLIO V + V Power output 6 3 +V_RTN TTL input/output # Not connected

25 Electrical Specification Coaxlink Hardware Manual 5 Electrical Specification Electrical specification of the product(s) including: electrical characteristics of all the input/output ports, description of the power distribution, power requirements, etc. CoaXPress Host Interface Each connection of the CoaXPress Host interface implements a Host Transceiver (HT) and a Power Transmitting Unit (PTU). Host Transceiver The Host transceiver implements a high-speed cable receiver and a low-speed cable driver for CXP-6 speeds. It fulfills the electrical specification of the CoaXPress. standard. Namely: The cable receiver requirements for the high-speed connection described in Table of the Annex B of the CoaXPress Standard. The cable driver requirements for the low-speed connection described in Table 3 of the Annex B of the CoaXPress Standard. Host Transceiver Specification High-speed connection bit rate Min. Typ Low-speed connection bit rate Max. Unit 6.5 GT/s MT/s Cable length BELDEN GT/s 30 m Cable length BELDEN GT/s 0 m Cable length BELDEN 3.5 GT/s 00 m Cable length BELDEN 5 GT/s 60 m Cable length BELDEN 6.5 GT/s 40 m Power Transmitting Unit The Power Transmitting Unit implements Power over CoaXPress (PoCXP) as specified in section 7 of the CoaXPress Standard.. If fulfills all the requirements for a Host; namely: Over-current protection (OCP)

26 6 Coaxlink Hardware Manual Electrical Specification PoCXP CoaXPress Device detection In addition: it provides the user with an AUTO/OFF control: Setting the control to AUTO initiates a new PoCXP device detection; the power will be applied only if the detection succeeds Setting the control to OFF forces the PTU to disconnect. The control is OFF after power on, and, if providing power to the camera is required, has to be set to AUTO by the application. Power Transmitting Unit Specification Min. Typ. Max. Unit DC output voltage 4 6 V Available output power 7 W OCP holding current 790 ma 5 A,000 µa OCP nominal trip current 550 PoCXP Device detection sensing current Note: The above specification applies over the whole operating temperature range of the Coaxlink card. PCI Express Interface The PCI Express Interface implements a PCIe end-point interface and provides electrical power to the Coaxlink card. PCI Express End-point PCI Express end-point vs. product. PCIe end-point Product PC630 Coaxlink Mono 4-lane Rev.0 PC63 Coaxlink Duo 4-lane Rev.0 PC63 Coaxlink Quad 4-lane Rev.0 PC633 Coaxlink Quad G3 4-lane Rev lane Rev.0 PCIe end-point Mono Duo Quad The 4-lane Rev.0 PCIe end-point: complies with Revision.0 of the PCI Express Card Electromechanical specification. supports -lane, -lane, and 4-lane link width supports PCIe Rev.0 link speed (.5 GT/s with 8b/0b coding)

27 Electrical Specification Coaxlink Hardware Manual 7 supports PCIe Rev.0 link speed (5.0 GT/s with 8b/0b coding) supports payload size up to 5 bytes offers the optimal performance when it is configured for 4-lane PCIe Rev.0 link speed (5 GT/s) PCIe end-point to PC memory data transfer performance Min. Sustainable output data rate Typ. Max. Unit,600 Megabyte/s 800 Megabyte/s 5 GT/s (PCIe Rev.0) Sustainable output data rate 5 GT/s (PCIe Rev.0) GT/s (PCIe Rev.0) 4-lane Rev 3.0 PCIe end-point Quad G3 The 4-lane Rev 3.0 PCIe end-point: complies with Revision 3.0 of the PCI Express Card Electromechanical specification. supports -lane, -lane, and 4-lane link width supports PCIe Rev.0 link speed (5.0 GT/s with 8b/0b coding) supports PCIe Rev 3.0 link speed (8.0 GT/s with 8b/30b coding) supports payload size up to 5 bytes offers the optimal performance when it is configured for 4-lane PCIe Rev 3.0 link speed (8 GT/s) doesn't support the PCIe Rev.0 link speed (.5 GT/s with 8b/0b coding) PCIe end-point to PC memory data transfer performance Sustainable output data rate Min. Typ. Max. Unit 3,00 Megabyte/s,600 Megabyte/s 800 Megabyte/s 8 GT/s (PCIe Rev 3.0) Sustainable output data rate 8 GT/s (PCIe Rev 3.0) 5 GT/s (PCIe Rev.0) Sustainable output data rate 8 GT/s (PCIe Rev 3.0) 5 GT/s (PCIe Rev.0)

28 8 Coaxlink Hardware Manual Electrical Specification Power Distribution PC630 Coaxlink Mono power distribution scheme Main power distribution network Auxiliary power distribution network PCI Express slot 6-pin PEG cable plug PCI Express Auxiliary Power Input +3.3 V + V 3A fuse 3A fuse + V 4 V DC Power converter.5 A PTC On-board electronics CoaXPress Host PoCXP Transmitter Unit A fuse Electronic fuse.5 A PTC Electronic fuse/switch +4 V A System I/O Internal System I/O +V PC63 Coaxlink Duo power distribution scheme Main power distribution network Auxiliary power distribution network PCI Express slot 6-pin PEG cable plug PCI Express Auxiliary Power Input +3.3 V 3A fuse + V 3A fuse PoCXP Transmitter Units & + V.5 A PTC A fuse 4 V DC Power converter On-board electronics.5 A PTC Electronic fuse.5 A PTC +V Electronic fuse/switch +4 V Electronic fuse/switch +4 V CoaXPress Host A B System I/O Internal System I/O Internal System I/O

29 Electrical Specification Coaxlink Hardware Manual 9 PC63 Coaxlink Quad power distribution scheme Main power distribution network Auxiliary power distribution network PCI Express slot 6-pin PEG cable plug PCI Express Auxiliary Power Input +3.3 V + V 3A fuse 3A fuse PoCXP Transmitter Units..4.5 A PTC.5 A PTC + V.5 A PTC A fuse.5 A PTC 4 V DC Power converter.5 A PTC On-board electronics Electronic fuse CoaXPress Host Electronic fuse/switch +4 V Electronic fuse/switch +4 V Electronic fuse/switch +4 V Electronic fuse/switch +4 V A B C D System I/O Internal System I/O Internal System I/O +V PC633 Coaxlink Quad G3 power distribution scheme Main power distribution network Auxiliary power distribution network PCI Express slot 6-pin PEG cable plug PCI Express Auxiliary Power Input +3.3 V 6A fuse + V 6A fuse PoCXP Transmitter Units..4.5 A PTC.5 A PTC + V.5 A PTC A fuse 4 V DC Power converter On-board electronics.5 A PTC Electronic fuse.5 A PTC +V CoaXPress Host Electronic fuse/switch +4 V Electronic fuse/switch +4 V Electronic fuse/switch +4 V Electronic fuse/switch +4 V A B C D System I/O Internal System I/O Internal System I/O The power distribution scheme of a Coaxlink card has two distinct distribution networks: The main power distribution network The auxiliary power distribution network Main power distribution network The main power distribution network delivers power to all the on-board electronic devices including FPGA, memory chips, CoaXPress transceivers, I/O drivers and receivers, fan motor. The network is fed by the Host PC motherboard through the +3.3 V and the + V power rails of the PCI Express slot. Protection fuses inserted at the input side of each power rail prevent potential fire hazards. The board status LED lamp reflects the global status of all the power converters of the main distribution network.

30 30 Coaxlink Hardware Manual Electrical Specification Auxiliary power distribution network The auxiliary power distribution network delivers power to the external devices including: CoaXPress cameras using the PoCXP capability available on all connections of the CoaXPress Host System devices using the + V power output available on all System I/O s The network is fed by a V external power supply attached to the auxiliary power input using a power cable terminated by a 6-pin PEG plug. A protection fuse inserted at the input side prevents potential fire hazards. A 4-volt DC power converter provides power to each camera connection through a PoCXP transmitter unit. Each PoCXP transmitter unit implements an electronic fuse/switch. A PTC fuse inserted at the input of each transmitter unit prevents potential fire hazards. The + V power is distributed from a common electronic fuse to all the System I/O s. A PTC fuse inserted at the input of prevents potential fire hazards. The CoaXPress Host Connector Indicator Lamps on page 8 reflect the state of each CoaXPress host connection. The following auxiliary power distribution network status are reported to the application: Presence of a PEG cable and a PEG compliant power supply Valid V voltage measured after the A fuse. 4 V DC power converter status Output voltage of each PoCXP transmitter Output current of each PoCXP transmitter Note: The protection fuses are not serviceable! When blown, the card must be returned to the factory. Note: The PTC fuses are self-resettable. Note: The Coaxlink card can be operated without applying power to the auxiliary power distribution network. PCI Express Power Input The Coaxlink Card consumes power from both the +3.3 V and the + V power rails of the PCI Express. PCIe power supply voltage requirements Min. Typ. Max. Units +3.3 V voltage V + V voltage V Typ. Max. Units PC630 Coaxlink Mono PCIe power supply power requirements Min. Mono +3.3 V power. W + V power 7. W Total power 9.3 W

31 Electrical Specification PC63 Coaxlink Duo PCIe power supply power requirements Coaxlink Hardware Manual 3 Duo Min. Typ. Max. Units +3.3 V power.7 W + V power 8.7 W Total power.4 W PC63 Coaxlink Quad PCIe power supply power requirements Quad Min. Typ. Max. Units +3.3 V power.5 W + V power 9.6 W Total power. W PC633 Coaxlink Quad G3 PCIe power supply power requirements Min. Quad G3 Typ. Max. Units +3.3 V power 3.8 W + V power 3.0 W Total power 6.8 W Note: The typical power values were measured under following conditions: Acquiring image data using all CoaXPress Host Interface connections operating at their maximum speed Delivering image data on the PCI Express configured for the largest link width and the highest link speed C [77 F] ambient temperature and nominal supply voltages Auxiliary Power Input Auxiliary Power Supply requirements Voltage Min. Typ. Max. Units 3 V Note: The sense input is intended for power source cable presence detection. It should be grounded at the power supply level. Note: The power rating of the power source is application dependent. 4-V power converter performance Power conversion total PoCXP output power Min. 9.5 Typ. Max. Units %

32 3 Coaxlink Hardware Manual Electrical Specification System I/O Power Output Specification A non-isolated + V power output is available on all System I/O s. The power originates from an external V power supply plugged into the Auxiliary Power Input. It is distributed from a common electronic fuse to all the System I/O s. The electronic fuse provides the following protections: Limits the inrush current during power on sequence Protects the Coaxlink card and the power source against overload Protects the Coaxlink card the power source against short-circuits. The sum of the load currents drawn from all the V outputs of the I/O s must be lower or equal to the specified maximum output current. System I/O + V power output specification Min. Max. Units Aggregated output current over the whole temperature operating range.0 A Voltage drop across the electronic output current 0. V Typ. Note: The above specification applies over the whole operating temperature range of the Coaxlink card. System I/O Ports Differential Input 3.3V IN+ IN- KΩ 50Ω AM6LV3E 5 pf Data In KΩ Differential input Simplified schematic AC/DC Characteristics The receiver complies with the ANSI/TIA/EIA-4B specification.

33 Electrical Specification Coaxlink Hardware Manual 33 DC characteristics Min. Typ. -7 Common mode voltage Differential sensitivity Max. Units +7 V 00 mv 0 Input impedance Ohm ESD protection Human Body Model (HBM) 5 kv ESD protection Contact discharge 8 kv ESD protection Air gap discharge 5 kv AC characteristics Min. Typ. Max. 00 Pulse width ns 0 Pulse rate 0%-90% rise/fall time Logical map The state of the port is reported as follows: Differential Input voltage Logical State (VIN+ - VIN-) > +00 mv HIGH (VIN+ - VIN-) < - 00 mv LOW Unconnected input port HIGH Compatible drivers and receivers The following drivers are compatible with the high-speed differential input ports: ANSI/EIA/TIA-4/485 differential line drivers Complementary TTL drivers Units 5 MHz µs

34 34 Coaxlink Hardware Manual Electrical Specification TTL Input/Output 74LVT5 TTLIO Data In/Out Direction 5 Ω 5V 74LVT5 TTL input/output Simplified schematic AC/DC characteristics The receiver is LVTTL and 5 V TTL compliant. The driver is a 3.3 V TTL driver DC characteristics Common mode input voltage Min. Typ. 0 Low-level output current Max. Units 5 V 64 ma Low-level output 6 ma 0.64 V Low-level output 3 ma 0.98 V Low-level output 64 ma.5 V -3 High-level output current ma High-level output ma.8 V High-level output ma.5 V kv ESD protection Human Body Model (HBM) Note: The I/O port includes a latch-up protection. AC characteristics Pulse width Pulse rate 0%-90% rise/fall time Min. Typ. Max Units ns 5 MHz µs

35 Coaxlink Hardware Manual 35 Electrical Specification Logical Map The state of the port is reported as follows: Logical State Input voltage VIN >.0 V HIGH VIN < 0.8 V LOW Undetermined Unconnected input port Compatible drivers and receivers The following drivers are compatible: Totem-pole LVTTL, TTL, 5 V CMOS drivers The following receivers are compatible: LVTTL, TTL, 3-Volt CMOS receivers Isolated Input IN+ Opto-coupler Comparator Current limiter Vref Data In IN- TTL input/output Simplified schematic AC/DC characteristics The input port implements an isolated current-sense input.

36 36 Coaxlink Hardware Manual Electrical Specification DC characteristics Min. Typ. -30 Differential voltage (VIN+ - VIN-) Max. Units 30 V Input current threshold.5 Differential ma ma.65.9 V Input - VIN-) =.65 V ma Input - VIN-) =.5 V ma Input - VIN-) = 5 V.3 ma Input - VIN-) = V 3 ma Input - VIN-) = 30 V 5 ma Input - VIN-) < V 0 µa 50 V Isolation voltage AC 70 VRMS 3 Iin [ma] Isolation voltage DC.3 Threshold Vin [Volt] Input Current vs. Input Voltage Characteristics AC characteristics Min. Pulse width 0 Pulse rate 0 Typ. Max. µs 50 Logical map The state of the port is reported as follows: Input current Units Logical State IIN > ma HIGH IIN < ma LOW Unconnected input port LOW khz

37 Electrical Specification Coaxlink Hardware Manual 37 Compatible drivers and receivers The following drivers are compatible with the isolated current-sense inputs: Totem-pole LVTTL, TTL, 5 V CMOS drivers RS-4 Differential line drivers Potential free contact, solid-state relay, or opto-isolators V and 4 V signaling voltages are also accepted Note: The + V power supply on the SYSTEM I/O (s) can be used for powering drivers requiring a power supply. Note: No external resistors are required. However, to obtain the best noise immunity with V and 4 V signaling, it is recommended to insert a series resistor in the circuit. The recommended resistor values are: 4.7kΩ for V signaling and 0kΩ for 4 V signaling. Isolated Output OUT+ 3.3V Input OUT- Turn-off time enhancement circuit TTL input/output Simplified schematic AC/DC characteristics The output port implements an isolated contact output. DC characteristics Max. Units 00 ma 30 V Differential voltage (VIN+ - VIN-) Closed ma 0.4 V Differential voltage (VIN+ - VIN-) Closed 00 ma.0 V Min. Current Differential voltage (VIN+ - VIN-) Open state -30 Typ. Isolation voltage DC 50 V Isolation voltage AC 70 VRMS Note: The output port in the closed state having no current limiter, the user circuit must be designed to avoid excessive currents that can destroy the output port. Note: The output port remains in the OFF-state until it is under control of the application.

38 38 Coaxlink Hardware Manual Electrical Specification AC characteristics Min. Max. Units 00 khz Turn-on time 5 µs Turn-off time 5 µs Typ. 0 Pulse rate Typical switching 5 C Current [ma] Turn ON time [µs] Turn OFF time [µs] Logical map The state of the output port is determined as follows: Output port state Logical State HIGH The contact switch is closed (ON) LOW The contact switch is open (OFF) Compatible loads The following loads are compatible with the isolated contact output ports: Any load within the 30V / 00 ma envelope is accepted. The power originates from an external power source or alternatively from the power delivered through the V and pins of the system I/O s.

39 Environmental Specification Coaxlink Hardware Manual 39 Environmental Specification Environmental specification of the product(s) including: climatic requirements, electromagnetic standards compliance statements, safety standards compliance statements, etc. Environmental Conditions Storage Conditions The following requirements are applicable only when the product is not powered, for instance, during storage conditions: Storage Conditions Requirements Ambient air temperature Ambient air humidity Min Max Units -0 [-4] 70 [58] C [ F] 0 90 % RH non-condensing Operating Conditions The following requirements are applicable when the product is in operation: Operating Conditions Requirements Min Max Units 80 [76] C [ F] 0 [3] 50 [] C [ F] 0 90 % RH non-condensing FPGA die temperature Ambient air temperature Ambient air humidity Note: The Coaxlink cards are equipped with a temperature sensor that reports the temperature of the FPGA die. Note: An event is reported to the application when the FPGA die temperature reaches the limit. Note: The thermal design of the host PC must ensure that, at any time, the FPGA die temperature never exceeds the recommended limit. Note: Exceeding the upper limit of the FPGA die temperature can permanently damage the card.

40 40 Coaxlink Hardware Manual Environmental Specification Thermal Design Heat sources The main heat contributors are: The electronic devices of the Coaxlink card including the losses of the power converters of the main power distribution network. The losses of the 4 V power converter of the auxiliary power distribution network. The amount of heat of the first contributor is equal to the electronic power delivered by the PCI Express. Refer to the PCI Express Interface topic for typical power consumptions. The amount of heat of the second distributor is equal to (- converter_efficiency) x Delivered _PoCXP_power. Refer to Auxiliary Power Input on page 3 for the converter efficiency. A PC630 Coaxlink Mono delivering the maximum electrical power to the camera(s) must dissipate around TBD Watts of heat to the ambient air! A PC63 Coaxlink Duo delivering the maximum electrical power to the camera(s) must dissipate around TBD Watts of heat to the ambient air! A PC63 Coaxlink Quad delivering the maximum electrical power to the camera(s) must dissipate about 5 Watts of heat to the ambient air! A PC633 Coaxlink Quad G3 delivering the maximum electrical power to the camera(s) must dissipate about 0 Watts of heat to the ambient air! Heat extraction The heat produced by the board is dissipated into the ambient air inside the Host PC. The heat exchange is facilitated by a heat sink and a fan mounted on the FPGA (the component having the largest heat source). The thermal design must ensure sufficient air flow along both sides to keep the FPGA die temperature below the upper limit of the allowed temperature range. The application is responsible for regularly checking the temperature and for taking the appropriate action in case of excessive temperature. CE Compliance (EMC Class B) Notice for Europe This product is in conformity with the Council Directive 004/08/EC This equipment has been tested and found to comply with EN550/CISPR and EN5504/CISPR4. To meet EC requirements, shielded cables must be used to connect a peripheral to the card. This product has been tested in a typical class B compliant host system. It is assumed that this product will also achieve compliance in any class B compliant unit.

41 Environmental Specification Coaxlink Hardware Manual 4 FCC Compliance (Class B) Notice for USA Compliance Information Statement (Declaration of Conformity Procedure) DoC FCC Part 5 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 5 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation or when the equipment is operated in a commercial environment. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/tv technician for help. RoHS Compliance This product is in conformity with the European Union RoHS 0/65/EU Directive, that stands for "the restriction of the use of certain hazardous substances in electrical and electronic equipment". WEEE According the European directive 0/9/EU, the product must be disposed of separately from normal household waste. It must be recycled according to the local regulations.