Developing Measurement and Control Applications with the LabVIEW FPGA Pioneer System

Transcription

1 Developing Measurement and Control Applications with the LabVIEW FPGA Pioneer System

2 Introduction National Instruments is now offering the LabVIEW FPGA Pioneer System to provide early access to the new LabVIEW FPGA Module and Reconfigurable I/O hardware. With the LabVIEW FPGA Module, you use graphical programming to configure FPGAs (Field Programmable Gate Arrays) on National Instruments Reconfigurable I/O devices. Together, the LabVIEW FPGA Module and the Reconfigurable I/O devices provide a flexible platform for creating sophisticated measurement and control systems that were previously possible only with custom-designed hardware. An FPGA is a chip that consists of many unconfigured logic gates. Unlike the fixed, vendor-defined functionality of an application-specific integrated circuit (ASIC) chip, you can configure and reconfigure the FPGA for each application. FPGAs are used in applications where either the cost of developing and fabricating an ASIC is prohibitive, or the hardware will need to be reconfigured after being placed into service. Because FPGAs can be used for implementation of custom algorithms in hardware, they offer benefits such as precise timing and synchronization, rapid decision making, and simultaneous execution of parallel tasks. Today, FPGAs appear in such devices as instruments, consumer electronics, automobiles, aircraft, copy machines, and application-specific computer hardware. FPGAs are often used in products for measurement and control, but the end users of these systems generally shy away from developing their own FPGA-based systems. Configuring FPGAs has historically required expertise in VHDL programming or complex design tools used more by hardware design engineers than test and control engineers. Now with the LabVIEW FPGA Pioneer System, you can use LabVIEW, a graphical development environment designed specifically for measurement and control applications, to create measurement and control systems that take advantage of the benefits of FPGAs. No other design tool knowledge is required to configure the FPGA on the Reconfigurable I/O device in the system. Because your LabVIEW FPGA Module logic executes in hardware, your system can process and generate synchronized analog and digital signals rapidly and deterministically. Because the LabVIEW FPGA Pioneer System is based on LabVIEW and PXI, you can enhance system capabilities by integrating components such as data acquisition, image acquisition and analysis, motion control, and industrial communication such as CAN and RS ni.com

3 Components of the LabVIEW FPGA Pioneer System The LabVIEW FPGA Pioneer System includes all the hardware and software necessary for development with the LabVIEW FPGA Module and Reconfigurable I/O hardware. NI created the LabVIEW FPGA Pioneer System to allow early access to the tools, even though some of the required software is in beta release. The LabVIEW FPGA Pioneer System includes LabVIEW, the LabVIEW Real-Time Module, and the LabVIEW FPGA Module. All owners of the LabVIEW FPGA Pioneer System will be entitled to free upgrades when the software components are released. Figure 1 shows the key hardware components of the LabVIEW FPGA Pioneer System. The system contains an NI PXI-8176 embedded controller (with a 1.2 GHz Intel Pentium III processor), an NI PXI slot chassis, a USB CD-ROM drive, and an NI PXI-7831R reconfigurable I/O plug-in device, as well as three SCB-68 shielded connector blocks and three SH68-C68-S cables. The NI PXI-8176 was selected because it offers the highest level of performance. The NI PXI-1042 is an 8-slot chassis, which is the most popular configuration. The NI PXI-7831R, the first NI Reconfigurable I/O device, includes the following features: 8 Independent 16-bit analog inputs, 4.3 µs conversions, ±10 V 8 Independent 16-bit analog outputs, 1.0 µs updates, ±10 V 96 digital I/O lines Onboard Flash memory LabVIEW-configurable FPGA PXI trigger interface for synchronizing two or more NI PXI-7831R modules Figure 1. The LabVIEW FPGA Pioneer System includes the NI PXI-8176 controller, the NI PXI slot chassis, the NI PXI-7831R reconfigurable I/O module, and shielded cables and connector blocks. You define the measurement and control functionality of the NI PXI-7831R by creating a LabVIEW VI and downloading it. Figure 2 shows a high-level block diagram of the NI PXI-7831R. The user-configurable FPGA handles the timing, synchronization, and decision-making defined in your LabVIEW VI. The FPGA interfaces to the analog and digital I/O and to the NI MITE ASIC chip. The NI MITE interfaces with the PXI backplane to transfer data between the NI PXI-7831R and other modules on the PXI bus, such as other I/O devices and the controller. National Instruments Corporation 3

4 Figure 2. Block Diagram of PXI-7831R You can use the LabVIEW FPGA Module to handle each of the I/O signal lines independently, or to synchronize any lines with any other lines. The Reconfigurable I/O device clock regulates the execution of all operations. With a device clock setting of 40 MHz, you can control the timing of your operations with a resolution of 25 ns. You can configure the DIO lines as custom counter/timers, PWM channels, or as ports for user-defined protocols. Using the Flash memory on the NI PXI-7831R, you can to store your device configuration and configure automatic loading and running when the module receives power. There are several key differences between the NI PXI-7831R Reconfigurable I/O module and data acquisition (DAQ) devices such as the National Instruments E Series. For example, an E Series device includes a fixed number of counter/timers and triggering functionality, handles waveforms, and uses high-level driver software with defined functions to control these operations. In contrast, the NI PXI-7831R offers a flexible number of counter/timers, and user-definable timing, triggering, and I/O synchronization. It also performs high-speed, single-point analog input and output, and provides low-level hardware control of the I/O. 4 ni.com

5 I/O Control Custom onboard decision making Timing and Synchronization Analog Input Table 1. Comparison of a Typical Multifunction I/O Device and the NI PXI-7831R Typical Multifunction DAQ Device ASICs for counter/timer operations, triggering, etc. N/A Driver functions for signal routing, clock sharing, triggering, pulse measurement/generation 16 single-ended or 8 differential, multiplexed NI PXI-7831R Configured with LabVIEW FPGA Module software Configured with LabVIEW FPGA Module software LabVIEW constructs such as while loops, sequence frames, wait functions, etc. implemented in hardware in real time 8 differential, independent. Can be synchronized. Analog Output 2 differential, independent 8 differential, independent. Can be synchronized. Digital I/O 8 static lines, independently configurable as input or output 96 lines, independently configurable as input or output static or synchronous Counter/timers 2 general-purpose counter/timers Any of 96 lines easily configured as custom counters. LabVIEW FPGA Module Functionality With the LabVIEW FPGA Module, you configure the operation of FPGA hardware by programming in LabVIEW. Your LabVIEW block diagram is implemented in hardware, which gives you direct control over the I/O of the NI PXI-7831R. This feature makes it possible to analyze and manipulate I/O signals in ways not possible with fixed I/O hardware. Figure 3 shows the block diagram for a simple rising-edge counter from one of the LabVIEW FPGA Module example programs. The fact that the U16 data type is used makes this a 16-bit counter. On a typical DAQ device, the counter logic is implemented in a fixed ASIC chip such as the DAQ-STC, and you write your application using the NI-DAQ counter VIs. With the LabVIEW FPGA Module, you write your own counter implementation in LabVIEW, and configure your own counter chip on a portion of the FPGA. You would probably never implement a counter in this way with LabVIEW or even with the LabVIEW Real-Time Module because a software-based counter would only be able to count very low-frequency edges. Because the LabVIEW FPGA Module uses the block diagram to implement your application in hardware, this counter has similar performance to the defined counters on a data acquisition device. National Instruments Corporation 5

6 Figure 3. Sample LabVIEW FPGA Program 16-Bit Counter The LabVIEW FPGA Pioneer System is shipped with example LabVIEW VIs for a variety of common functions. These examples can be modified to meet the needs of your custom application. Some topics covered in the examples include the following: Pulse-width modulation (PWM) Timed, synchronized operations Custom counter and encoder interface Custom triggering methods Application Development Flow Figure 4 shows the typical development flow for LabVIEW FPGA Module applications. The first step is to develop the VI that will be deployed to your FPGA target on the NI PXI-7831R. Before you compile, you can test in emulated mode, which runs your algorithm on the host PC processor. After you develop, debug, and compile your FPGA VI, you will develop your host interface VI(s). You can use a computer running either Microsoft Windows or a real-time operating system for your host computer. If you are using an RT Series target for your host computer, you will develop a separate user interface in LabVIEW for Windows. Figure 4. Application Development Flow 6 ni.com

7 Developing the FPGA VI The first step in developing your application is to create the LabVIEW block diagram that will be used to configure the FPGA on the NI PXI-7831R. This is where you will implement your logic for synchronizing signals, custom digital protocol communication, PWM communication, and onboard decision making for control and alarm handling. The LabVIEW FPGA Module adds to and uses many of the same functions as the LabVIEW development environment. As shown in Figure 5, the Functions palette when you target a Reconfigurable I/O device is very similar to LabVIEW for Windows. There is an FPGA Device I/O palette instead of a Data Acquisition palette, because NI-DAQ is not used with Reconfigurable I/O devices. The functions on the Time & Dialog palette offer resolution selection of ms, µs, and ticks. As discussed before, there are several options for Reconfigurable I/O device clock speed. The smallest achievable tick is 5 ns. When creating your FPGA VI, you will use the same basic program constructs such as While Loops, For Loops, Case Structures, and Sequence Structures from the standard LabVIEW environment to create your application. Because floating-point operations are not available on the FPGA, the Functions palette when you target a Reconfigurable I/O device has fewer operators and analysis functions than the LabVIEW Full Development Software for Windows. In addition, there are no functions available for file I/O or ActiveX because there is no hard drive or operating system on the NI PXI-7831R. Figure 5. LabVIEW FPGA Module Functions Palette When Targeting a Reconfigurable I/O Device You have access to the modified Functions palette when your target selection is either FPGA or the FPGA Emulator. Emulation mode uses the I/O of the Reconfigurable I/O device, but executes the logic on the development computer processor. You can verify the execution flow of your VI, although you will not achieve hardware determinism in this mode. There are two reasons to use emulation mode: Debugging emulation mode offers all the debugging tools of LabVIEW, such as execution highlighting, probes, and breakpoints with single-stepping; these features are not available after compilation Testing test your VI without waiting for it to compile National Instruments Corporation 7

8 Just as with other FPGA development tools, the compile step can take minutes or hours depending on application complexity and PC resources. When you need to test the FPGA VI with the speed and determinism of hardware performance, you will need to compile rather than use emulation mode. You can begin compiling simply by clicking the Run button while the LabVIEW target selection is set to FPGA. Because the VI targeted to the NI PXI-7831R runs in hardware without the overhead of an operating system, execution is completely deterministic. Developing the Host Application After you create and debug your FPGA VI, you will create one or more VIs for host interaction. You can use a computer running either Microsoft Windows or a real-time operating system as your host computer for your Reconfigurable I/O device. With LabVIEW for Windows, you can take advantage of Windows-related functions directly in the host VI(s), but your host application does not execute deterministically. A National Instruments RT Series target is a deterministic host computer that fully controls all the I/O in your system and communicates with LabVIEW for Windows running on your user interface machine. The host computer is where you perform floating-point operations such as FFTs or model-based control and simulation. When you install the LabVIEW FPGA Module, the FPGA Interface palette, shown in Figure 6, is installed as a subpalette of the Functions palette when you target LabVIEW for Windows or an RT Series target. Figure 6. FPGA Interface Palette The FPGA Interface palette contains VIs for communicating with your FPGA VI and handling interrupts. By defining how your host VIs and your FPGA VI interact, you are defining your own driver-level software. Developing Your User Interface Application Your user interface application is where you will typically perform the tasks that are not time-critical, such as configuring system parameters, generating reports, and managing data. If your Windows PC is your FPGA host computer, you can use the same machine for your user interface. If you use an RT Series target for your FPGA host computer, you will need to create a Windows-based user interface on your host computer. Figure 7 shows the interaction between platforms in this type of system. 8 ni.com

9 Windows Computer RT PXI Controller PXI 7831R Windows VI RT VI(s) FPGA VI Figure 7. Example Deployment Strategy Another deployment option is to create an embedded system that does not require a user interface display or monitor. To create this option, you use both the LabVIEW Real-Time Module and the LabVIEW FPGA Module. Performance Benefits Because the hardware itself runs the algorithms, performance is typically much greater than that of software-based systems. For example, consider an application with eight PID control loops. Using an RT Series target to perform the eight PID calculations and the NI PXI-7831R simply for I/O, you can achieve a loop rate of 28 khz. When you implement an integer-based PID algorithm on the FPGA of the NI PXI-7831R, you can achieve loop rate of 100 khz for all eight loops. The speed limitation for executing the PID control loop on the NI PXI-7381R is due to the settling time of the A/D to 16 bits, not to the PID calculation. Control loops for digital I/O such as PWM can be performed at several MHz. Another benefit of targeting your LabVIEW code to the FPGA on the NI PXI-7381R is that you can achieve true simultaneous, parallel processing. There is no operating system on the module that must divide CPU time between several tasks. For example, consider a LabVIEW block diagram with two parallel While Loops, each implementing a counter, as shown in Figure 3. This application actually creates two separate hardware processors on the FPGA that operate simultaneously, but can be synchronized to the NI PXI-7831R clock. Even within the same While Loop or other structure, you can achieve speed improvements by performing operations in parallel using a pipelining architecture. You can accomplish this in a LabVIEW block diagram by dividing up your processing and performing the pieces on subsequent iterations of your While Loop. In Figure 8 below, the control algorithm is divided into two pieces. Figure 8. Pipelining Architecture National Instruments Corporation 9

10 Each iteration of the While Loop updates the control output, but the AI and Control 1 operations are performed in parallel with the AO and Control 2 operations, which executes the algorithm more quickly than an inline processing architecture would. This simultaneous, parallel processing would not be possible on a platform with a microprocessor and operating system. Applications Analog Control By using the LabVIEW FPGA Module and the NI PXI-7831R, you can create custom hardware to empower a wide variety of applications for many industries. Examples include discrete control and analog control for manufacturing and scientific research, and simulation for electronic control module (ECM) development. There are many types of analog control applications that can benefit from the NI PXI-7381R hardware and the LabVIEW FPGA Module. The analog input channels of the PXI-7381R are capable of sampling a 16-bit value every 4.3 µs, and the analog output channels can perform updates every 1.0 µs. Additionally, with the flexibility of the LabVIEW FPGA Module, you can implement common control algorithms, such as PID, as well as develop customized algorithms for your application. Some examples of analog control include: Dynamometer control (speed/load) Servo-hydraulic or electrodynamic shaker control Motor speed or position control Simulation In addition to performing as a complete control system as described above, you can use the NI PXI-7381R in systems for rapid control prototyping (RCP) and hardware-in-the-loop (HIL) simulation testing of controllers under development. Electronic controllers are common in many products such as vehicles and household appliances. In the early stages of development, before the controller is built, the control algorithms must be tested with the plant, i.e., the system to be controlled. To accomplish this, the RCP system behaves as the controller and uses specifically designed algorithms to test the control of the plant. After the preliminary version of the controller is built, it must be validated. For extensive testing, it is often more convenient to then to simulate the plant and test the controller. This is often referred to as HIL testing. The LabVIEW FPGA Module extends the LabVIEW platform by building on the capabilities of LabVIEW and the LabVIEW Real-Time Module. Typically, for an HIL or RCP application, you will use an RT Series target as your FPGA host computer. Here you will execute the main model and complex processing algorithms. You use LabVIEW FPGA to configure the NI PXI-7381R to handle the I/O and synchronize with external events. Just as with a fixed-functionality I/O device, the hardware processing happens at a much higher speed than the software processing on the host computer. With the NI PXI-7381R, you can customize your own hardware processing, including simulating sensor outputs, generating and decoding PWM signals, and performing onboard decision making 10 ni.com

11 based on measured values. With this type of architecture, you can greatly reduce the need for multiprocessor systems that are often used to handle both the simulation and I/O in many systems today. Digital Protocol Emulation Many applications require that systems interface to devices that speak an uncommon digital protocol. Often, hardware for this is either not available or not affordable. With the LabVIEW FPGA Module and the NI PXI-7831R, you can take advantage of the high-speed digital processing in hardware to decode and encode messages with a high degree of flexibility. In this way, you configure the NI PXI-7381R to become an interface device for your communication protocol. Flexible Encoder Interface PWM Communication Discrete Control Unique Measurements An encoder is a device for measuring speed or position. As a shaft rotates, pulses are generated indicating degrees of rotation. There are many different types of encoders available, and often several types must be used in the same application. With the LabVIEW FPGA Module, you can configure the NI PXI-7381R to interface to different types of encoders on different digital lines, and reconfigure the device for different applications. You can add your own custom functionality, such as reading the counters synchronously with other signals, rather than reading based on input signals to the counters themselves. Pulse-width modulated (PWM) signals are common in many industries, such as automotive and telecommunications. In a PWM pulse train, the frequency is held constant, and the information is conveyed by the duty cycle, the percentage of time the pulse is high. Many fixed-functionality I/O devices do not adequately handle rapidly changing duty cycles, or allocate a fixed number of channels for static PWM or other operations. With the LabVIEW FPGA Module, you can configure any of the digital lines on the NI PXI-7381R to read or write PWM signals as required by your application. Manufacturing applications require fast, robust control systems. By using the FPGA to execute the logic of your application, the LabVIEW FPGA Module provides a platform for developing such systems. The NI PXI-7381R is able to scan and set multiple digital lines, while making control decisions in a fraction of a microsecond. Because the NI PXI-7381R running an FPGA VI does not have the overhead of operating system software, such as a real-time operating system, or a modification of the Windows kernel, there is no possibility of unanticipated latency. The LabVIEW FPGA Module brings a new level of timing control and synchronization capability to measurement and control system development. You now have the capability to design your own I/O device, simply by drawing a LabVIEW block diagram. As an example of this, consider a real-time measurement of spark timing of an automotive engine. This is the time delay from when the engine crankshaft rotates through the zero degree National Instruments Corporation 11

12 Conclusions mark, referred to as top dead center (TDC), and the firing of a particular spark plug. To make this measurement, you must measure the crankshaft position, and the ignition coil voltage. The typical built-in automotive crank sensor is magnetic and counts the teeth in a gear on the crankshaft, sending out pulses that you can read on a digital input line. There are missing teeth at TDC. Thus to measure spark timing, you must determine, in real-time, when the signal from the crank sensor indicates the missing teeth. Now, also in real-time, you must measure the delay from this event on the digital input, and the analog event of spark firing. By implementing this logic with the LabVIEW FPGA Module and the NI PXI-7831R, you create a custom I/O device. Whereas most I/O devices return a voltage or a pulse width to the host computer, this device returns spark timing calculated from mixed signal inputs. By using the LabVIEW FPGA Module and the NI PXI-7831R, your applications can benefit from the speed and synchronization capability of FPGAs, as well as traditional capabilities such as DAQ, image acquisition and processing, motion control, industrial communication, and others. Early users of the LabVIEW FPGA Module report that the dataflow model and inherent parallelism of the LabVIEW graphical programming language provide a highly intuitive environment for developing measurement and control applications for execution in hardware. Using the LabVIEW FPGA Module with LabVIEW and the LabVIEW Real-Time Module, you can address new applications and gain the most performance from your system. For More Information For more information on the LabVIEW FPGA Pioneer System, contact Geoff Hoekstra at geoff.hoekstra@ni.com or visit ni.com/info and enter infocode: fpga *342329A-01* A-01 May North Mopac Expressway Austin, TX USA Tel: (512) Fax: (512) info@ni.com 2003 National Instruments Corporation. All rights reserved. LabVIEW, National Instruments, and ni.com are trademarks of National Instruments Corporation. Product and company names mentioned herein are trademarks or trade names of their respective companies. For patents covering National Instruments products, refer to the appropriate location: Help»Patents in your software, the patents.txt file on your CD, or ni.com/patents.