A Test-Centric Approach to ASIC Development for MEMS

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1 A Test-Centric Approach to ASIC Development for MEMS MÅRTEN VRÅNES DIRECTOR, CONSULTING SERVICES CONSULTING SERVICES GROUP MEMS JOURNAL, INC. C: th Annual MTR Conference October 2012

2 Outline Introduction ASIC Development Alternative Strategies SSCs Stepwise FPGA Summary

3 Introduction Definition: ASIC for MEMS = Application Specific Integrated Circuit for Micro Electro Mechanical Systems Purpose: To convert analog sensor output to the digital real realm and often a real-world value Note: ASIC is not a standard, off-the-shelf IC Standard ICs for MEMS here referred to as Sensor Signal Conditioner (SSC)

4 ASIC/SSC Block Diagram External Sensor Source: ZMDI

5 Introduction ASIC vs. SSC ASIC SSC High Volume, >10M per year X Low to Medium Volume, < 10M per year X X Proof-of-concept, customer/investor sampling X Monolithic or wafer-level packaging X Size sensitive applications X Cost sensitive applications X Special functionality, eg. sensor fusion, proprietary algorithms X Special application, eg. packaging, harsh environments X Multiple sensor integration X Lowest NRE X Analog output/ uncompensated sensors X

6 ASIC Sourcing In-House Develop the ASIC using predominantly internal resources Full control over test Integrated Device Manufacturer (IDM) IDM supplier's ASIC product is based in large part on proprietary technology such as design tools, IP, packaging, and usually, but not necessarily the process technology IDM responsible for production test Fabless Fabless ASIC suppliers rely largely on outside suppliers for their technology Test responsibilities can vary

7 Outline Introduction ASIC Development Alternative Strategies SSCs Stepwise FPGA Summary

8 ASIC Development Custom Design Define all litho layers Tailor functionality, performance, layout and unit cost High risk and resource intensive development Examples: development cost/time, ASIC to MEMS mismatch, IP infringement issues and testability IP Block Design Use pre-existing, proven IP blocks Examples: analog sensor interface, uc, NVM, I2C/SPI Cost depending on block availability and price Existing blocks are fab dependent Testability already designed into each block

9 ASIC Development Cycle Does the ASIC fit the MEMS? Design Test Simulation Tapeout Layout

10 Does the ASIC fit the MEMS?

11 Ensuring MEMS / ASIC fit Meeting the Design Specification Design, simulation, know-how and existing IP blocks MEMS and ASIC tradeoffs Minimizing Risk Seasoned analog designers Multi-project wafer (MPW) for proof of concept Corner simulations using SPICE and Monte Carlo analysis Multifunctional design and tapeout reviews Test resources should be involved throughout the design process Strict source control Re-using existing, proven IP blocks Design for Test (DFT)

12 Design for Test Analog Circuitry Digitally controlled, analog switches enable monitoring of input and output signals to an analog block.

13 Design for Test Analog Circuitry Digitally controlled, analog switches enable with input test signal. Can be used as self-test and product testing.

14 Example ASIC Development Sensing Pressure Temperature Voltage Motion/Acceleration Control Microcontroller Firmware: State Machine Sensor Interface (ADC) and Processing Oscillators Timers Watchdog Memory RAM, ROM & EEPROM LV Sensors ASIC Inputs Sensor Inputs LF Pick-Up Coil Automatic Gain Control Command Decoder Outputs RF Transmitter 315MHz / 434MHz ASK / FSK Modulation Power Management Battery Management Low-Power Operation

15 Example ASIC Development Design, Integration & Layout Custom RF and LF fabless 3 rd party Custom multi-channel sensor interface in-house Custom analog sensor conditioning in-house Custom (size) NVM IDM Standard uc IDM Integration & layout fabless 3 rd party Layout fabless 3 rd party Test Related Issues Test coverage and testability LV Sensors TPMS Product Design optimized for power, not test. Scan and IDDQ not possible. Unproven design, very comprehensive automotive characterization scheme (-40 C to 125 C) Is it the MEMS or ASIC issues

16 ASIC Development Challenges Design & Application Increasing functionality and complexity Tiny analog signals Signal integrity and noise Integration of multiple sensors Sensor algorithms and sensor fusion Environmental factors: light, humidity, mechanical stress etc. When to tape-out? With ASICs becoming more complex, the time to market shrinking and the expected unit cost declining, how can the ASIC design be improved by testing upstream in the product development?

17 Outline Introduction ASIC Development Alternative Strategies SSCs Stepwise FPGA Summary

18 Alternative Strategies Overview Standard Use an off-the-shelf SSC Test existing MEMS Integrated product Stepwise A step-by-step approach to ASIC development Verify ASIC blocks before taping out the entire chip FPGA Leverage the programmability and versatility of FPGA NI PXI-7813R RIO FPGA Source: National Instruments

19 Alternative Strategies Standard Pros Cons Proof of concept Cost, cost and cost Rapid prototyping Customer and investor samples MEMS characterization Performance benchmarking Tested and proven development platform Feature and functionality limitations Overkill Limited programmability Predefined calibration algorithms Unpredictable availability Use as basis for custom ASIC Fixed layout and form factor Launch into a standalone product High-volume limitations

20 Alternative Strategies Standard Development Platform Hardware Main Development Board Daughter / Plug-In Boards Satellite Boards Software Application Development Software Firmware Calibration Software (eg. DLL) Source: ACAM

21 Alternative Strategies Standard R&D Test Engineering Test DLL Production Test

22 Alternative Strategies Standard Supplier Provided Calibration DLL Seamless integration with SSC Implemented in firmware, dedicated circuitry, ROM or other Linking R&D, Engineering and Production testing DLL with calibration algorithm Can be used from a range of programming languages Eg. C, C++, VB, NI LabView, NI LabWindows/CVI Test Data, Ref. Data Scaling Factors etc. INPUTS Supplier Provided Calibration DLL Calibration Coefficients, Calibration Fit, Errors etc. OUTPUTS

23 Example Calibration DLL 1. Configure NVM Calibration Algorithm Output Sensor Resolution Clear Calibration Coefficients 1 2. Collect sensor and reference measurement data 2 3. Scale measurement data 3 Source: ZMDI

24 Example Calibration DLL 4. Set calibration mask 4 5. Call calibration function - Inputs: - # data points - Calibration coefficients - Raw sensor data (scaled) - Ref. data (scaled) - Output - Calculated calibration coefficients - Error code 6. Write calibration coefficients to EEPROM 5 6 Source: ZMDI

25 Standard SSC Example 1 ZMDI s ZSSC3026 Low Power 16 Bit Sensor Signal Conditioner IC Integrated 18-bit calibration math DSP Fully corrected signal at digital output Minimize calibration costs through the one-pass calibration concept No external trimming components required Highly integrated CMOS design Excellent for low-voltage and low-power battery applications Source: ZMDI

26 Standard SSC Example 1 How to use? Test samples MEMS + SSC Digital raw counts Test operating range Multiple temperatures, voltages etc. Plug data into development SW Click and choose calibration algorithms/coefficients Optimize calibration points Evaluate calibration fit and error, calculated automatically by dev. SW Calibrate samples and verify real measurement errors Source: ZMDI

27 Standard SSC Example 2 Si-Ware s Development platform for capacitive MEMS accelerometers and gyros. Integrated SSC, SWS1110 Key Features 1X gyro or accel. interface High-res ADC Gyro drive actuation loop High voltage actuation option Temperature compensation Source: Si-Ware

28 Standard SSC Example 2 How to use? Custom sensor boards plug directly into the main development board. Sensor board can be used as standalone unit for testing on shaker, rate table or other fixture. Source: Si-Ware

29 Alternative Strategies Stepwise Analog Sensor Front-End Design Analog to digital converter (ADC) OPAMPs Comparators CIC Filter Temperature sensor Bandgap references Switches Filters Clock Scheme Source: National Instruments

30 Alternative Strategies Stepwise Analog Sensor Front-End Tapeout Multi-project wafer shuttle (MPW) Analog Sensor Front-End Test High pin count package with test pins available Analog measurements Noise, resolution, range Use known passives Digital simulation/emulation FPGA test setup Real measurements Algorithm development Application testing Source: E2V

31 Alternative Strategies Stepwise FPGA Test Setup Develop and simulate digital circuitry MEMS Front End FPGA Connectors Connectors for power, USB programmer, PC etc.

32 MEMS & FPGA Field Programmable Gate Arrays (FPGAs) are programmable semiconductor devices that are based on a matrix configuration with configurable interconnects. SRAM based FPGAs can be programmed and reprogrammed many times Perfect match for MEMS product development Main Advantages Use of hardware based timing Simulate ASIC design Develop and test sensor algorithms Connect to and test individual ASIC blocks Aid ASIC design for testability Source: Xilinx

33 Alternative Strategies FPGA Factory-integrate analog front-end with an FPGA Ideal for new product development & testing Solution for early ramp-up production, <1M Requires: Partnering with an FPGA provider Xilinx Alterra Lattice or the release of a MEMS FPGA development platform Source: Altera

34 Alternative Strategies FPGA Endless Possibilities Low-cost versions Integrated products Low-volume production ramp-up Value-added versions Product development Multi-sensor input Proof of concept Investor / customer samples Engineering samples Software Development Platform FPGA Analog Front End MEMS Sensors

35 Alternative Strategies FPGA Development Platform Example FPGA with multiple analog input channels Resistive interface Wheatstone bridge Voltage/current driven Capacitance interface Gain/offset based interface Ratiometric based interface Single-ended sensors Differential sensors Use for a multitude of sensors Sensor integration / fusion Develop ASIC for high-volume applications Source: Si-Ware

36 Outline Introduction ASIC Development Alternative Strategies SSCs Stepwise FPGA Summary

37 Summary Limitations with typical ASIC development projects have been presented with a particular focus on test. Three distinct strategies have been discussed as alternatives to: Test upstream in the product development cycle Leverage existing market offerings & technology Minimize product development risk Speed up time to market

38 Consulting Services Strategic Marketing Developed branding and strategic marketing presentations for industry-leading ASIC and SSCs solutions. Competitive Analysis Evaluation and industry benchmarking of sensor interface ASIC devices. Industry analysis Developed detailed production test requirements analysis for a major multinational contactor solutions company. Whitepapers & Marketing Reports Reports on MEMS testing Whitepapers for leading ASIC and SSCs Whitepapers for MEMS processing

39 Contact Information Mårten Vrånes Director, MEMS Testing and Reliability Consulting Services Group MEMS Journal, Inc. C:

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