Memory Management. Motivation

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1 Memory Management Vera Goebel Department of Informatics University of Oslo Basic memory management: Mono- and multi-programming Fixed and variable memory partitioning Swapping Paging Segmentation Virtual memory (paging) Page replacement algorithms Design issues for paging systems Implementation issues 1 Motivation In project assignments so far Program code is linked to kernel Physical addresses are well-known Not realistic In the real world Programs are loaded dynamically Physical addresses it will get are not known to program Program size at run-time is not known to kernel 2 1!

2 Memory Management Ideally programmers want memory that is large fast non volatile Memory hierarchy small amount of fast, expensive memory cache some medium-speed, medium price main memory gigabytes of slow, cheap disk storage Memory manager handles the memory hierarchy 3 Computer Hardware Review Typical memory hierarchy numbers shown are rough approximations 4 2!

3 Memory Management for Monoprogramming Only one user program loaded Program is entirely in memory No swapping or paging Three simple ways of organizing memory Some PDAs, embedded systems! C64, ZX8,! User program! OS in ROM! x! xfff.! OS in RAM! Old mainframes and minicomputers! User program! x! xfff.! OS in RAM! User program! MS-DOS,! Devs in ROM! x! xfff.! 5 Multiprogramming Processes have to wait for I/O Goal Do other work while a process waits Give CPU to another process Processes may be concurrently ready So If I/O waiting probability for all processes is p Probable CPU utilization can be estimated as CPU utilization = 1 - p n 6 3!

4 Job# Arriv al time CPU use time IO wait time 1 1: : : :2 2 8 Multiprogramming Arrival and work requirements of 4 jobs CPU utilization for 1-4 jobs with 8% I/O wait Remaining CPU time! 1! 2! 3! 4! 2.! 1.1!.3! 3.! 2.1! 1.2! 1.!.1! 2.! 1.1!.9! 2.! 1.7!.7!.8! # processors % CPU idle CPU busy CPU per process ! 2! 3! 4! 2.!.9!.9!.8!.8!.8!.3!.3!.3!.3!.9!.9!.9!.1!.1!.7!! 1! 15! 2! 22! 27.6! 28.2! Sequence of events as jobs arrive and finish Note numbers show amount of CPU time jobs get each interval 31.7! time! 7 Multiprogramming Degree of multiprogramming CPU utilization as a function of number of processes in memory 8 4!

5 Multiprogramming Several programs Concurrently loaded into memory OS must arrange memory sharing Memory partitioning Memory Needed for different tasks within a process Shared among processes Process memory demand may change over time Use of secondary storage Move (parts of) blocking processes from memory Higher degree of multiprogramming possible Makes sense if processes block for long times 9 Memory Management for Multiprogramming Process may not be entirely in memory Reasons Other processes use memory Their turn Higher priority Process is waiting for I/O Too big For its share For entire available memory Approaches Swapping Paging Overlays Paging Swapping Overlays Registers Cache(s) DRAM Disk 2x 1x 1 9 x 1 5!

6 Memory Management for Multiprogramming Swapping Remove a process from memory With all of its state and data Store it on a secondary medium Disk, Flash RAM, other slow RAM, historically also Tape Paging Remove part of a process from memory Store it on a secondary medium Sizes of such parts are fixed Page size How to use these! with! Virtual Memory! Overlays Manually replace parts of code and data Programmer s rather than OS s work Only for very old and memory-scarce systems 11 Memory Management Techniques Before details about moving processes out Assign memory to processes Memory partitioning Fixed partitioning Dynamic partitioning Simple paging Simple segmentation Virtual memory paging Virtual memory segmentation 12 6!

7 Multiprogramming with Fixed Partitions Fixed memory partitions separate input queues for each partition single input queue 13 Fixed Partitioning Divide memory Into static partitions At system initialization time (boot or earlier) Advantages Very easy to implement Can support swapping process in and out 14 7!

8 Fixed Partitioning Two fixed partitioning schemes Equal-size partitions Unequal-size partitions Equal-size partitions Big programs can not be executed Unless program parts are loaded from disk Small programs use entire partition A problem called internal fragmentation Operating system! x! x fff! 15 Fixed Partitioning Two fixed partitioning schemes Equal-size partitions Unequal-size partitions Unequal-size partitions Bigger programs can be loaded at once Smaller programs can lead to less internal fragmentation Advantages require assignment of jobs to partitions Operating system! Operating system! 2MB! 4MB! 6MB! 12MB! 16MB! 16 8!

9 Fixed Partitioning Approach Has been used in mainframes Uses the term job for a running program Jobs run as batch jobs Jobs are taken from a queue of pending jobs Problem with unequal partitions Choosing a job for a partition Operating system! 2MB! 4MB! 6MB! 12MB! 16MB! 17 Fixed Partitioning One queue per partition Internal fragmentation is minimal Jobs wait although sufficiently large partitions are available Operating system! 2MB! 4MB! 6MB! 12MB! 16MB! 18 9!

10 Fixed Partitioning Single queue Jobs are put into next sufficiently large partition Waiting time is reduced Internal fragmentation is bigger A swapping mechanism can reduce internal fragmentation Move a job to another partition Operating system! 2MB! 4MB! 6MB! 12MB! 16MB! 19 Problems: Relocation and Protection Cannot be sure where program will be loaded in memory address locations of variables, code routines cannot be absolute must keep a program out of other processes partitions Use base and limit values address locations added to base value to map to physical addr address locations larger than limit value is an error 2 1!

11 2 Registers: Base and Bound virtual address + physical address bound base > error Built in Cray-1 A program can only access physical memory in [base, base+bound] On a context switch: save/ restore base, bound registers Pros: Simple Cons: fragmentation, hard to share, and difficult to use disks Swapping (1) Memory allocation changes as processes come into memory leave memory Shaded regions are unused memory 22 11!

12 Dynamic Partitioning Divide memory Partitions are created dynamically for jobs Removed after jobs are finished External fragmentation Problem increases with system running time Occurs with swapping as well Addresses of process 2 changed External! fragmentation! Solutions to address! change with! Address Translation! Operating system! Swapped in! Process 5! Process 1! 2! 2MB 14MB! free! 2MB! 14MB! 6MB 6MB! free! Process 4! Process 2! 56MB 14MB 14MB! free! 6MB free! 36MB free! Process 3! 22MB 1 free! 4MB free! 23 Dynamic Partitioning Reduce external fragmentation Compaction Compaction Takes time Consumes processing resources Reduce compaction need Placement algorithms Operating system! Swapped in! Process 2! 14MB! Process 6MB! 4! Process 4! 6MB free! Process 3! 6MB free! 1 Process 3! 6MB free! 1 16MB free! free! 4MB free! 24 12!

13 Dynamic Partitioning: Placement Algorithms Use most suitable partition for process Typical algorithms First fit Next fit Best fit First! Next! Best! 4MB! 16MB! 16MB! 16MB! 6MB! 4MB! 4MB! 4MB! 6MB! 6MB! 6MB! 4MB! 16MB! 16MB! 16MB! 12 4MB! MB! 6MB! 16MB! 16MB! 32MB! 32MB! 32MB! 25 Dynamic Partitioning: Placement Algorithms Use most suitable partition for process First! 4MB! 12MB! 4MB! 6MB! 16MB! Best! 6MB! 4MB! 4MB! 16MB! Typical algorithms First fit Next fit Best fit 12 12MB! 16MB! 32MB! 1MB! 12 12MB! 16MB! 32MB! 12MB! 1MB! 26 13!

14 Dynamic Partitioning: Placement Algorithms Comparison of First fit, Next fit and Best fit Example is naturally artificial First fit Simplest, fastest of the three Typically the best of the three Next fit Typically slightly worse than first fit Problems with large segments Best fit Slowest Creates lots of small free blocks Therefore typically worst 27 Memory Management with Bit Maps Part of memory with 5 processes, 3 holes tick marks show allocation units shaded regions are free Corresponding bit map Same information as a list 28 14!

15 Memory Management with Linked Lists Four neighbor combinations for the terminating process X 29 Buddy System Mix of fixed and dynamic partitioning Partitions have sizes 2 k, L k U Maintain a list of holes with sizes Assign a process Find smallest k so that process fits into 2 k Find a hole of size 2 k If not available, split smallest hole larger than 2 k Split recursively into halves until two holes have size 2 k Process 32kB! Process! Process! 128kB! 256kB! Process! 128kB! 128kB! 256kB! 32kB! 64kB! 32kB! 128kB! 64kB! 512kB! Process 32kB! Process! 256kB! 256kB! 1MB! Process! 256kB! 256kB! 512kB! 256kB! 3 15!

16 Swapping (2) Allocating space for growing data segment Allocating space for growing stack & data segment 31 Memory use within a process PCB! Memory needs of known size Program code Global variables Memory needs of unknown size Dynamically allocated memory Stack Several in multithreaded programs Program! Process! program! Initialized global! variables (data)! Uninitialized global vars! Uninitialized global! variables! data! stack! Possibly stacks for more threads! 32 16!

17 Memory Addressing program! Addressing in memory Addressing needs are determined during programming Must work independently of position in memory Actual physical address are not known Initialized global! variables! Uninitialized global vars! 33 Memory Addressing PCB! program! Addressing in memory Addressing needs are determined during programming Must work independently of position in memory Actual physical address are not known data! stack! 34 17!

18 Memory Management Addressing Covered address translation and virtual memory PCB! program! data! program! Important now Translation is necessary Therefore possible to have several parts Pages Segments data! data! stack! 35 Paging Paging Equal lengths Determined by processor One page moved into one memory frames Process Process 2! 3! 4! 5! 1! Process is loaded into several frames Not necessarily consecutive No external fragmentation Little internal fragmentation Depends on frame size 36 18!

19 Paging Virtual address page table size VPage # offset > error Page table PPage# PPage#... PPage # offset Physical address Use a page table to translate Various bits in each entry Context switch: similar to the segmentation scheme What should be the page size? Pros: simple allocation, easy to share Cons: big page table and cannot deal with holes easily Segmentation Different lengths Determined by programmer Memory frames Segmentation Programmer (or compiler toolchain) organizes program in parts Move control Needs awareness of possible segment size limits Pros and Cons Principle as in dynamic partitioning No internal fragmentation Less external fragmentation because on average smaller segments 38 19!

20 Virtual address segment offset seg size. + Segmentation Have a table of (seg, size) Protection: each entry has > error (nil, read, write) On a context switch: save/ restore the table or a pointer to the table in kernel memory Pros: Efficient, easy to share Cons: Complex management and fragmentation within a segment physical address Paging and Segmentation Typical for paging and swapping Address translation At execution time With processor support Simple paging and segmentation Without virtual memory and protection Can be implemented by address rewriting at load time by jump tables setup at load time Lookup! table! ( part 2,! offset in part 2)! +! Simplified! Address translation! Code part 1! Code part 2! 4 2!

21 Segmentation with Paging Vseg # Virtual address VPage # offset seg. size Page table PPage# PPage#... > PPage # offset error Physical address Other needs (protection) Protection of process from itself (stack grows into heap) Protection of processes from each other (write to other process) PCB! program! data! program! data! stack! program! Solutions to protection! with! Address Translation! stack! data! stack! 42 21!

22 Summary: Memory Management Algorithms Paging and segmentation Extended in address translation and virtual memory lectures Placement algorithms for partitioning strategies Mostly obsolete for system memory management since hardware address translation is available But still necessary for managing kernel memory memory within a process memory of specialized systems (esp. database systems) Address translation solves Solves addressing in a loaded program Hardware address translation Supports protection from data access Supports new physical memory position after swapping in Virtual memory provides Provide larger logical (virtual) than physical memory Selects process, page or segment for removal from physical memory 43 Why Virtual Memory? Use secondary storage Extend expensive DRAM with reasonable performance Protection Programs do not step over each other and communicate with each other require explicit IPC operations Convenience Flat address space and programs have the same view of the world 44 22!

23 Virtual Memory Paging (1) The position and function of the MMU 45 Translation Overview CPU Translation (MMU) Physical memory virtual address physical address I/O device Actual translation is in hardware (MMU) Controlled in software CPU view what program sees, virtual memory Memory view physical memory 23!

24 Goals of Translation Implicit translation for each memory reference A hit should be very fast Trigger an exception on a miss paging Protected from user s faults Registers Cache(s) DRAM Disk 1x 1x 1Mx 47 Paging (2) The relation between virtual addresses and physical memory addresses given by page table 48 24!

25 Page Tables (1) Internal operation of MMU with 16 4 KB pages 49 Page table! bit! 15!!! 14!!! 13!!! 12!!! 11! 111! 1! 1!!! 9! 11! 1! 8!!! 7!!! 6!!! 5! 11! 1! 4! 1! 1! 3!! 1! 2! 11! 1! 1! 1! 1!! 1! 1! Incoming virtual address! (x24, 8196)! Memory Lookup present! 1! 1!! 4-bit index! into page table! virtual page = x1 = 2! Outgoing physical address! (x64, 2458)! 12-bit offset!!! 1!!!!!!!!!!! 1!!! 5 25!

26 Page table! Memory Lookup present! bit! 15!!! 14!!! 13!!! 12!!! 11! 111! 1! 1!!! 9! 11! 1! 8!!! 7!!! 6!!! 5! 11! 1! 4! 1! 1! 3!! 1! 2! 11!! 1! 1! 1!! 1! 1! Incoming virtual address! (x24, 8196)! 4-bit index! into page table! virtual page = x1 = 2! Outgoing physical address! PAGE FAULT 12-bit offset!!! 1!!!!!!!!!!! 1!!! 51 Page Fault Handling 1. Hardware traps to the kernel saving program counter and process state information 2. Save general registers and other volatile information 3. OS discover the page fault and tries to determine which virtual page is requested 4. OS checks if the virtual page is valid and if protection is consistent with access 5. Select a page to be replaced 6. Check if selected page frame is dirty, i.e., updated 7. When selected page frame is ready, the OS finds the disk address where the needed data is located and schedules a disk operation to bring in into memory 8. A disk interrupt is executed indicating that the disk I/O operation is finished, the page tables are updated, and the page frame is marked normal state 9. Faulting instruction is backed up and the program counter is reset 1. Faulting process is scheduled, and OS returns to routine that made the trap to the kernel 11. The registers and other volatile information is restored and control is returned to user space to continue execution as no page fault had occured 52 26!

27 Instruction Backup An instruction causing a page fault 53 Page Tables (2) Second-level page tables! Top-level! page table! 32 bit address with 2 page table fields Two-level page tables 54 27!

28 Page Tables (3) Typical page table entry 55 Multiple-Level Page Tables Virtual address dir table offset pte. Directory... 28!

29 TLBs Translation Lookaside Buffers A TLB to speed up paging 57 Translation Look-aside Buffer (TLB) Virtual address VPage # offset VPage# VPage# VPage# PPage#... PPage#.... PPage#... TLB Hit PPage # offset Miss Real page table Physical address 29!

30 Bits in A TLB Entry Common (necessary) bits Virtual page number: match with the virtual address Physical page number: translated address Valid Access bits: kernel and user (nil, read, write) Optional (useful) bits Process tag Reference Modify Cacheable Hardware-Controlled TLB On a TLB miss Hardware loads the PTE into the TLB Need to write back if there is no free entry Generate a fault if the page containing the PTE is invalid VM software performs fault handling Restart the CPU On a TLB hit, hardware checks the valid bit If valid, pointer to page frame in memory If invalid, the hardware generates a page fault Perform page fault handling Restart the faulting instruction 3!

31 Software-Controlled TLB On a miss in TLB Write back if there is no free entry Check if the page containing the PTE is in memory If no, perform page fault handling Load the PTE into the TLB Restart the faulting instruction On a hit in TLB, the hardware checks valid bit If valid, pointer to page frame in memory If invalid, the hardware generates a page fault Perform page fault handling Restart the faulting instruction Hardware vs. Software Controlled Hardware approach Efficient Inflexible Need more space for page table Software approach Flexible Software can do mappings by hashing PP# (Pid, VP#) (Pid, VP#) PP# Can deal with large virtual address space 62 31!

32 How Many PTEs Do We Need? Worst case for 32-bit address machine # of processes 2 2 (if page size is 496 bytes) What about 64-bit address machine? # of processes Inverted Page Tables Virtual address pid vpage offset pid vpage k n-1 Inverted page table Physical address k offset Main idea One PTE for each physical page frame Hash (Vpage, pid) to Ppage# Pros Small page table for large address space Cons Lookup is difficult Overhead of managing hash chains, etc 32!

33 Inverted Page Tables Comparison of a traditional page table with an inverted page table 65 Page Replacement Algorithms Page fault OS has to select a page for replacement Modified page write back to disk Not modified page just overwrite with new data How do we decide which page to replace? determined by the page replacement algorithm several algorithms exist: Random Other algorithms take into acount usage, age, etc. (e.g., FIFO, not recently used, least recently used, second chance, clock, ) which is best??? 66 33!

34 Optimal Best possible page replacement algorithm: When a page fault occurs, all pages in memory are labeled with the number of instructions that will be executed before this page will be used again The page with most instructions before reuse is replaced Easy to describe, but impossible to implement (OS cannot look into the future) Estimate by logging page usage on previous runs of process Useful to evaluate other page replacement algorithm 67 Not Recently Used (NRU) Two status bits associated with each page: R page referenced (read or written) M page modified (written) Pages belong to one of four set of pages according to the status bits: Class : not referenced, not modified (R=, M=) Class 1: not referenced, modified Class 2: referenced, not modified Class 3: referenced, modified (R=, M=1) (R=1, M=) (R=1, M=1) NRU removes a page at random from the lowest numbered, non-empty class Low overhead 68 34!

35 First In First Out (FIFO) All pages in memory are maintained in a list sorted by age FIFO replaces the oldest page, i.e., the first in the list Reference string: A B C D A E F G H I A J! Now the buffer is full, No change next page in the fault FIFO results chain a replacement AC BE F GI AJ DH B DE F HI A CG AC DE GH I BF BC DF GH AE AB CE F GD AB DE F C AC DE B BC DA Page most recently loaded Page first loaded, i.e., FIRST REPLACED Low overhead FIFO is rearly used in its pure form 69 Second Chance Modification of FIFO R bit: when a page is referenced again, the R bit is set, and the page will be treated as a newly loaded page Reference string: A B C D A E F G H I! Page I will be inserted, find a page to page out by looking at the first page loaded: Page -if A s B s R-bit R-bit = = 1 replace move page out, last in shift chain chain and left, clear and R-bit, insert look I last at new in the first chain page (B) Now the buffer is The full, R-bit next for page page fault A is results set in a -if R-bit = replacement 1 clear R-bit, move page last, and finally look at the new first page E G DH A I F R-bit Page most recently loaded DF C GH A E C E B F GH D B D A E F GC 1 A C DE F B 1 B C DE A 1 A B C D 1 A B C 1 Page first loaded Second chance is a reasonable algorithm, but inefficient because it is moving pages around the list 7 35!

36 Clock More efficient way to implement Second Chance Circular list in form of a clock Pointer to the oldest page: R-bit = replace and advance pointer R-bit = 1 set R-bit to, advance pointer until R-bit =, replace and advance pointer Reference string: A B C D A E F G H I! H A 1 B I G C F E D 71 Least Recently Used (LRU) Replace the page that has the longest time since last reference Based on the observation that pages that are heavily used in the last few instructions will probably be used again in the next few instructions Several ways to implement this algoithm 72 36!

37 Least Recently Used (LRU) LRU as a linked list: Reference string: A B C D A E F G H A C I! Now the buffer is Page full, Move fault, next A C last A page replace last in in fault the in the LRU results chain (B) (most in with a replacement I (most recently used) E F GD HI AC E F DG CH A D E BF AG H D AC E HF G BC DA GE F BC F DE B E CD D B Page most recently used Page least recently used Expensive - maintaining an ordered list of all pages in memory: most recently used at front, least at rear update this list every memory reference!! 73 Least Recently Used (LRU) LRU by using aging: reference counter for each page after a clock tick: shift bits in the reference counter to the right (rightmost bit is deleted) add a page s referece bit in front of the reference counter (left) page with lowest counter is replaced Clock tick Clock tick Clock tick Clock tick Clock tick !

38 Least Recently Used (LRU) LRU as a matrix: N pages N x N matrix Page N is referenced row N is set (1) column N is cleared () Replace page with lowest row value Page frame string: ! Counting Algorithms LRU by using a reference counter clear the counter when the page is referenced (counter = ) increase all counters each clock tick replace the page with the highest counter Not/Least Frequently Used (N/LFU) counter initially increase the page s counter only if it has been referenced during this clock tick replace the page with lowest counter Most Frequently Used (MFU) counter as LFU replace the page with the highest counter (assuming low counters mean new, fresh pages) 76 38!

39 LRU-K & 2Q LRU-K: bases page replacement in the last K references on a page [O Neil et al. 93] 2Q: uses 3 queues to hold much referenced and popular pages in memory [Johnson et al. 94] 2 FIFO queues for seldom referenced pages 1 LRU queue for much referenced pages Retrieved from disk Reused, move to LRU queue NOT Reused, move to FIFO queue NOT reused, page out FIFO LRU FIFO NOT reused, page out Reused, re-arrange LRU queue Reused, move back to LRU queue 77 Working Set Model Working set: set of pages which a process is currently using Working set model: paging system tries to keep track of each process working set and makes sure that these pages is in memory before letting the process run reduces page fault rate (prepaging) Defining the working set: set of pages used in the last k memory references (must count backwards) approximation is to use all references used in the last XX instructions 78 39!

40 The Working Set Page Replacement Algorithm (1) k The working set is the set of pages used by the k most recent memory references w(k,t) is the size of the working set at time, t 79 Working Set Page Replacement Algorithm τ - time period to calculate the WS over age - virtual time - last reference time if all pages have R == 1! select one page randomly! Expensive - must search the whole page table 8 4!

41 WSClock Page Replacement Algorithm Organize each page table entry as a clock As with clock - the page pointed to is examined first R = 1: clear bit, set virtual time, continue (b) R = : (c) age < τ : continue to next age > τ : if page clean, replace (d) othervice, write to disk and continue to next 224! If all pointer comes back to start writes are scheduled to clean pages (find first) no scheduled writes (all in WS), several option remove first clean remove oldest ! 224! 224! 81 Review of Page Replacement Algorithms 82 41!

42 Demand Paging Versus Prepaging Demand paging: pages are loaded on demand, i.e., after a process needs it Should be used if we have no knowledge about future references Each page is loaded separatly from disk, i.e., results in many disk accesses Prepaging: prefetching data in advance, i.e., before use Should be used if we have knowledge about future references # page faults is reduced, i.e., page in memory when needed by a process # disk accesses can be reduced by loading several pages in one I/O-operation 83 Allocation Policies How should memory be allocated among the competing runnable processes? Equal allocation: all processes get the same amount of pages Proportional allocation: amount of pages is depending on process size 84 42!

43 Allocation Policies Local page replacement: consider only pages of own process when replacing a page corresponds to equal allocation can cause thrashing multiple, identical pages in memory Global page replacemet: consider all pages in memory when replacing a page corresponds to proportional allocation better performance in general monitoring of working set size and aging bits data sharing 85 Allocation Policies Example: local versus global replacement insert page A5 using age replacement Age Age Age A1 1 A1 1 A1 1 A2 7 A3 4 A4 11 Local replacement: Replace the oldest of A s pages A2 7 A5 13 A4 11 A2 7 A3 4 A4 11 B1 6 B1 6 B1 6 B2 12 B3 1 B4 3 Global replacement: Replace the oldest page in memory B2 12 B3 1 B4 3 B2 12 A5 13 B4 3 C1 8 C1 8 C1 8 C2 2 C2 2 C2 2 C3 9 C3 9 C3 9 C4 5 C4 5 C4 5 Original configuration Local replacement Global replacement 86 43!

44 Allocation Policies Page fault frequency (PFF): Usually, more page frames fewer page faults PFF: page faults/sec # page frames assigned PFF is unacceptable high process needs more memory PFF might be too low process may have too much memory!!!?????? Solution??: Reduce number of processes competing for memory reassign a page frame 1 d swap one or more to disk, divide up pages they held reconsider degree of multiprogramming n 1 d n 87 Page Size Determining the optimum page size requires balancing several competing factors: Data segment size n x page size internal fragmentation (small size) Keep in memory only data that is (currently) used (small size) Disk operations (large size) Page table size: access/load time and space requirements (large size) Page replacement algorithm: operations per page (large size) Usual page sizes is 4 KB 8 KB, but up to 64 KB is suggested for systems supporting new applications managing high data rate data streams like video and audio 88 44!

45 Locking & Sharing Locking pages in memory: I/O and context switches Much used pages Shared pages users running the same program at the same time, e.g., editor or compiler Problem 1: not all pages are shareable Problem 2: process swapping or termination 89 Separate Instruction and Data Spaces One address space Separate I and D spaces 9 45!

46 Cleaning Policy Need for a background process, paging daemon periodically inspects state of memory When too few frames are free selects pages to evict using a replacement algorithm It can use same circular list (clock) as regular page replacement algorithmbut with diff ptr 91 Implementation Issues Operating System Involvement with Paging Four times when OS involved with paging 1. Process creation - determine program size - create page table 2. Process execution - MMU reset for new process - TLB flushed 3. Page fault time - determine virtual address causing fault - swap target page out, needed page in 4. Process termination time - release page table, pages 92 46!

47 Page Fault Handling (1) 1. Hardware traps to kernel 2. General registers saved 3. OS determines which virtual page needed 4. OS checks validity of address, seeks page frame 5. If selected frame is dirty, write it to disk 93 Page Fault Handling (2) 6. OS brings schedules new page in from disk 7. Page tables updated l Faulting instruction backed up to when it began 6. Faulting process scheduled 7. Registers restored l Program continues 94 47!

48 Instruction Backup An instruction causing a page fault 95 Locking Pages in Memory Virtual memory and I/O occasionally interact Proc issues call for read from device into buffer while waiting for I/O, another processes starts up has a page fault buffer for the first proc may be chosen to be paged out Need to specify some pages locked exempted from being target pages 96 48!

49 Backing Store (a) Paging to static swap area (b) Backing up pages dynamically 97 Segmentation (1) One-dimensional address space with growing tables One table may bump into another 98 49!

50 Segmentation (2) Allows each table to grow or shrink, independently 99 Segmentation (3) Comparison of paging and segmentation 1 5!

51 Implementation of Pure Segmentation (a)-(d) Development of checkerboarding (e) Removal of the checkerboarding by compaction 11 Segmentation with Paging: MULTICS (1) Descriptor segment points to page tables Segment descriptor numbers are field lengths 12 51!

52 Segmentation with Paging: MULTICS (2) A 34-bit MULTICS virtual address 13 Segmentation with Paging: MULTICS (3) Conversion of a 2-part MULTICS address into a main memory address 14 52!

53 Segmentation with Paging: MULTICS (4) Simplified version of the MULTICS TLB Existence of 2 page sizes makes actual TLB more complicated 15 Segmentation with Paging: Pentium (1) A Pentium selector 16 53!

54 Segmentation with Paging: Pentium (2) Pentium code segment descriptor Data segments differ slightly 17 Segmentation with Paging: Pentium (3) Conversion of a (selector, offset) pair to a linear address 18 54!

55 Segmentation with Paging: Pentium (4) Mapping of a linear address onto a physical address 19 Segmentation with Paging: Pentium (5) Level! Protection on the Pentium 11 55!

56 Paging on Pentium In protected mode, the currently executing process have a 4 GB address space (2 32 ) viewed as 1 M 4 KB pages The 4 GB address space is divided into 1 K page groups (1 level page directory) Each page group has 1 K 4 KB pages (2 level page table) Mass storage space is also divided into 4 KB blocks of information Uses control registers for paging information 111 Control Registers used for Paging on Pentium Control register (CR): P G C N D W Not-Write-Through and Cache Disable: used to control internal cache Paging Enable: OS enables paging by setting CR[PG] = 1 W P Write-Protect: If CR[WP] = 1, only OS may write to read-only pages P E Protected Mode Enable: If CR[PE] = 1, the processor is in protected mode Control register 1 (CR1) does not exist, returns only zero Control register 2 (CR2) only used if CR[PG]=1 & CR[PE]=1 31 Page Fault Linear Address !

57 Control Registers used for Paging on Pentium Control register 3 (CR3) page directory base address: only used if CR[PG]=1 & CR[PE]= Page Directory Base Address A 4KB-aligned physical base address of the page directory PC PW D T Page Cache Disable: If CR3[PCD] = 1, caching is turned off Page Write-Through: If CR3[PWT] = 1, use write-through updated Control register 4 (CR4): 31 4 PS E Page Size Extension: If CR4[PSE] = 1, the OS designer may designate some pages as 4 MB 113 Incoming virtual address! (x14238, )! Pentium Memory Lookup Page directory: PT base address physical base address of the page table... PS A U W P page size accessed present allowed to write user access allowed !

58 Incoming virtual address! (x14238, )! Pentium Memory Lookup Index to page directory! (x6, 6)! CR3:...1 Page Directory Base Address Page table PF: 1. Save pointer to instruction 2. Move linear address to CR2 3. Generate a PF exception jump to handler 4. Programmer reads CR2 address 5. Upper 1 CR2 bits identify needed PT 6. Page directory entry is really a mass storage address 7. Allocate a new page write back if dirty 8. Read page from storage device 9. Insert new PT base address into page directory entry 1. Return and restore faulting instruction 11. Resume operation reading the same page directory entry again now P = Incoming virtual address! (x14238, )! Pentium Memory Lookup Page frame PF: Save 11 pointer to instruction 2. Move linear address to CR Generate a PF exception jump to handler Index to page directory! Index to page table! 4. Programmer reads CR2 address (x6, 6)! (x2, 2)! 5. Upper 1 CR2 bits identify needed PT Use middle 1 CR2 bit to determine entry in PT holds a mass storage address Allocate a new page write back if dirty 8. Read page from storage device Insert new page frame base address into 11 page table entry 1. Return and restore faulting instruction Resume operation reading the same 1 page directory entry and page table entry again both now P = Page table: CR3: Page Directory Base Address !

59 Incoming virtual address! (x14238, )! Pentium Memory Lookup Index to page directory! (x6, 6)! CR3: Page Directory Base Address Index to page table! (x2, 2)! Page offset! (x38, 56)! requested data 1 1 Page: 117 Page Fault Causes Page directory entry s P-bit = : page group s directory (page table) not in memory Page table entry s P-bit = : requested page not in memory Attempt to write to a read-only page Insufficient page-level privilege to access page table or frame One of the reserved bits are set in the page directory or table entry !

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