Building Bigger Systems: Interfacing

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1 ! Building Bigger Systems: Interfacing Lecture L Advanced Digital Design ECE Department Many elements Don Thomas, 2014, used with permission with credit to G. Larson

2 Basic Principles Reading: Chapter of SV book What s an interface do? Signal level conversions voltages, currents, charge, analog-todigital, digital-to-analog, Handles data availability, protocol and packetization Is the data in the input register new and unseen? One side deals with packets or sectors, the other side deals with words Handles error detection and possibly correction Sometimes through the protocol (hey you! -- resend that data!) Sometimes the data can be corrected in the interface Connects multiple threads within a clock domain clock domains within a computer system For now, single clock domains 2

3 Two concurrent hardware threads Hardware Threads (FSM-Ds), each with: its own state transition diagram and data path control and data lines for coordination via some protocol Questions: What does threadleft (below) know about the state of threadright? Could you model these as a single hardware thread? outputs inputs 3

4 Synchronizing FSMs (wait states) How are multiple FSMs synchronized? Wait states (among others) Wait state a state with a self loop conditioned by an external signal ( ready here) external? This example waits for ready and then asserts ld_data as it exits the wait state Assumption One FSM is guaranteed to be in the wait state before the other machine asserts ready And that ready is asserted long enough for the other FSM to see it, but not long enough to see it twice! This is a one-sided wait ready wait ready ready / ld_data Wait in this state for the ready signal to be asserted which in this case is a control signal to load data AND to enter a new state. while (~ready) /* do nothin */ ; Generally, the protocol specifies these relationships 4

5 An illustration Consider an FSM in a wait state waiting for a counter to count down to zero Can be viewed as two machines its state register is count, plus maybe a bit in the FSM Is the assumption from previous slide guaranteed to hold? /start startval -1 start wait ~done done FSM sel == 0 mux done/ ld_cnt_l ck count 5

6 Guaranteed to work? A protocol is defined between the two machines The left machine is completely in control -- it s the master It s guaranteed that the right machine will be in state waitstart when the wait state is entered. Therefore the left machine can t miss the done signal to exit Part of the reasoning is based on knowing that there is a masterslave relationship between the two machines /start startval -1 wait ~done start done FSM sel == 0 mux done/ ld_cnt_l ck count master slave 6

7 Another Situation Here Machine A doesn t wait Machine B is waiting for A BW is wait state When A transits from AA, B transits from BW Such a meeting is often called a Rendezvous Rendezvous: An situation where two + FSMs meet in designated states Their transitions are synchronized with each other Then each machine knows the state of the other by design The point is, the state of the other machines is known (by design), so data can be passed. Split register transfers reg reg Machine A A A A B Machine A output / readya readya readya Machine B B W B i + reg readya readya / ldreg Machine B input A split register transfer ldreg 7

8 Where this might not work Assumption One FSM is guaranteed to be in the wait state before the other machine asserts ready ready Requirements You need a means of guaranteeing an order Approaches One machine solely controls the other (e.g., the counter example) A reset signal to both FSMs guarantees the order Other handshake (synchronizing lines) keep the order once established (covered later) Killers ready ready / ld_data Data dependent execution that can get the two machines out of order wait 8

9 Synchronizing FSMs Another approach to synchronizing two machines double-sided wait state Similar to the previous version but now arrival is order independent either machine can come first How? A waits for B if first Machine A Machine B B waits for A if first Both proceed when machines are in their wait states wait readyb / readya A W readyb / readya A i readya readyb B W readya / readyb wait readya / readyb B j Called a system rendezvous Name comes from some software languages that have a similar notion. 9

10 Tracing signals into rendezvous MachineA.state A W A i Lots of synchronized things can happen on this edge to next state ReadyA asserted MachineB.state ReadyB B W asserted B j System rendezvous state Machine A Machine B wait A W readyb / readya readya readyb B W readya / readyb wait readyb / readya readya / readyb A i B j 10

11 Synchronizing FSMs (Lockstep) Lockstep Synchronization Keeping two FSMs in state-synchronization Assume same clock and edge Given two+ FSMs that are in rendezvous, they will stay in rendezvous in any sequence of states for which the number of states from the start in each machine is determinable and equal Sometimes certain state transitions (arcs) are still in rendezvous but others aren t Lockstep Considerations: There are no unbounded wait states, data-driven while statements, There aren t any if-then-else statements with differing numbers of states in each branch 11

12 Lockstep illustration Lockstep machines are locked in 1-1 transitions Edge pairs can assume availability of data Set up by design of the system Machine A Machine B A W readyb / readya readya readyb B W readya / readyb B Rendezvous starts readyb / readya readya / readyb A 3 Once they rendezvous FSMs can stay in rendezvous using lockstep synchronization allowing synchronized actions to occur B 7 A 4 Put data on bus Read data from bus B 8 Lockstep A 5 B 9 No signaling lines used! 12

13 Alas, Lockstep doesn t last forever All good things come to an end What is the extent of the rendezvous/lockstep now? It s the edges that matter Machine A Machine B readyb / readya readya readya / readyb B A W readyb B W readyb / readya readya / readyb A 3 A 4 Oops, this unbounded, datadriven wait breaks the lockstep. States and transitions aren t 1-1 at this point. B 7 B 8 readyc readyc A 5 B 9 13

14 An example can get uglier This is way over done, but you ll get the idea Assumptions Machine A R Machine B Grey arrows are inter-fsm signals self loops there are waiting for the signal Same clock and reset a b R A H D is a data dependent loop Questions c B C D On which edge pairs are they in rendezvous so they can transmit data in either direction? Some are one directional only which are and why? e g d f E F G 14

15 The SimpleBus Protocol We ll discuss a simple bus protocol the example will come back to haunt us in several lectures The idea is to have: some bus wires that connect two modules on the bus a processor and a memory a protocol for how the bus is going to read and write an example that fits onto slides for presentation 15

16 The SimpleBus Protocol The basic operation This is a processor memory bus. The data sent is 8 bits. The 16-bit address is sent in two bytes, separately (upper first and then lower). Other signals serve to synchronize the two machines wrt each other. Both participants use the same clock / reset Some definitions Master an interface that is in charge of a communications channel (here a bus). It is capable controlling all the other interfaces, specifically how/when they use the channel Slave an interface that is on a communications channel and whose communication is controlled by another device (the master) In some systems, there can be more than one master, although typically not executing as a master at the same time. In these cases, mastership is passed around by some protocol 16

17 Watching the bus lines wiggle A B C D E F address upper lower start read data datavalid S1 S2 S3 S4 S5 S6 Functionality: From reset, a bus master puts the upper address bits on the bus and asserts start. The slave sees this, latches the address and waits for the lower address in the next state. Also in the next state, if read is asserted, then this is a bus read. In that case, the slave will put the read-data on the bus data lines and signal datavalid. If it s a write, the master will drive the data lines and signal datavalid. When datavalid becomes unasserted, the bus cycle is over. 17

18 Overview of interface Functionality: From reset, a bus master puts the upper address bits on the bus and asserts start. The slave sees this, latches the address and waits for the lower address in the next state. Also in the next state, if read is asserted, then this is a bus read. In that case, the slave will put the read-data on the bus data lines and signal datavalid. If it s a write, the master will drive the data lines and signal datavalid. When datavalid becomes unasserted, the bus cycle is over. address[7:0] data[7:0] start read datavalid Processor Interface Memory Interface Interface Master and Slave have different view of the interface lines (input vs output) Clock could be in the interface or could be different master and slave clocks 18

19 The processor (master) We ll conceive of the processor as having two hardware threads an interface thread that will handle the protocol when the processor asks a processor thread that will request reads and writes this is essentially the testbench Processor Thread access doread Avalue wdatardy Dvalue Processor Interface Thread address data start read datavalid Memory Interface Thread AddrReg data memdata-avail Memory Thread The bus lines 19

20 The DataPath part of the Master en_addrup BusDrivers[7:0] AddrReg[15:0] from Processor [15:8] [7:0] BusDrivers[7:0] en_addrlo address[7:0] The testbench (processor) provides a 16-bit address to read/write Interface control signals enable either the upper or lower byte of the address to drive the bus module BusDrivers #(parameter W = 1) (input logic [W-1:0] dataout, input logic enable, output logic [W-1:0] busline); assign busline = (enable)? dataout : bz; endmodule Tri-state driver inferred 20

21 More DataPath The testbench (processor) uses DataReg to provide 8- bit data to write. It reads data from DataReg Data to Processor DataReg ld_data en_data Bus Transceiver BusDrivers[7:0] BusRcvrs[7:0] Interface control signals enable DataReg to drive the bus, and data from the bus to be loaded in to register DataReg data[7:0] module BusTransceiver #(parameter W = 1) (input logic [W-1:0] dataout, input logic enable, inout logic [W-1:0] busline output logic [W-1:0] datain); assign busline = (enable)? in : bz; assign datain = busline; endmodule 21

22 The Master s FSM & internal signals R MA MB MC ~access access/start, en_addrup doread/read=1, en_addrlo ~datavalid datavalid/ ld_data ~doread/read=0, en_addrlo MD wdatardy/ dv, en_data ~wdatardy/ access signal from processor to start the access doread signal from processor to do a read wdatardy signal from processor that the data to write is in the data register en_data enable the bus data register to drive the bus lines en_addrup en_data BusDrivers[7:0] BusDrivers[7:0] AddrReg[15:0] from Processor [15:8] [7:0] BusDrivers[7:0] DataReg BusRcvrs[7:0] en_addrlo address[7:0] Data to Processor ld_data Bus Transceiver data[7:0] A B C D E F ld_data enable the bus data register to load from the bus lines address start upper lower read data datavalid S1 S2 S3 S4 S5 S6 22

23 The memory (slave) We ll conceive of the memory as having two hardware threads an interface thread that will handle the protocol when a memory access is being requested a memory thread that will model the memory Processor Thread access doread Avalue wdatardy Dvalue Processor Interface Thread address data start read datavalid Memory Interface Thread AddrReg data memdata-avail Memory Thread The bus lines 23

24 The Slave s Datapath Very similar to the master s datapath, but now data is to/from a memory ld_data Memory Address[15:0] to Memory en_data MemData Bus Transceiver ld_addrup [15:8] [7:0] ld_addrlo BusDrivers[7:0] BusRcvrs[7:0] AddrReg[15:8] AddrReg[7:0] data[7:0] address[7:0] Since the address is sent in two pieces, they have to be loaded into registers to produce the whole 16-bit address 24

25 The Slave s FSM & its internal signals address A B C D E F upper lower R SA ~start start/ld_addrup ld_addrup(lo) load the address register parts from the bus start read data datavalid en_data S1 S2 S3 S4 S5 S6 ld_data Memory MemData Bus Transceiver SB SC memdataavail data in the slave is ready to drive the bus data lines read/ld_addrlo ~memdataavail memdataavail/ dv, en_data ld_addrup ~read/ld_addrlo [15:8] SD datavalid/ ld_data ~datavalid/ en_data enable the Memory to drive the bus Address[15:0] to Memory [7:0] ld_data load the memory from the bus ld_addrlo BusDrivers[7:0] BusRcvrs[7:0] AddrReg[15:8] AddrReg[7:0] data[7:0] address[7:0] 25

26 How do they work together? R ~access R ~start MA SA Master access/start, en_addrup MB doread/read=1, en_addrlo ~doread/read=0, en_addrlo start/ld_addrup Slave SB read/ld_addrlo ~read/ld_addrlo MC ~datavalid MD ~wdatardy/ SC ~memdataavail SD ~datavalid/ datavalid/ ld_data wdatardy/ dv, en_data memdataavail/ dv, en_data datavalid/ ld_data A B C D E F address upper lower start read data datavalid S1 S2 S3 S4 S5 S6 26

27 Master Overview module BusMaster (input logic resetn, clock, output logic start, read, inout datavalid, output logic [7:0] address, inout [7:0] data); logic en_addrup, en_addrlo, ld_data, en_data, access = 0; logic doread, wdatardy, dv; logic [7:0] DataReg; logic [15:0] AddrReg; enum {MA, MB, MC, MD} State, NextState; clock, negedge resetn) if (!resetn) State <= MA; else State <= NextState; R ~access MA access/start, en_addrup MB doread/read=1, en_addrlo ~doread/read=0, en_addrlo MC ~datavalid MD ~wdatardy/ datavalid/ ld_data wdatardy/ dv, en_data 27

28 The DataPath part of the Master en_addrup BusDrivers[7:0] AddrReg[15:0] from Processor [15:8] [7:0] BusDrivers[7:0] en_addrlo address[7:0] R ~access MA access/start, en_addrup MB doread/read=1, en_addrlo ~doread/read=0, en_addrlo MC ~datavalid MD ~wdatardy/ always_comb begin if (en_addrlo) address = AddrReg[7:0]; else if (en_addrup) address = AddrReg[15:8]; else address = 'bz; end datavalid/ ld_data wdatardy/ dv, en_data 28

29 More DataPath assign data = (en_data)? DataReg : 'bz; clock) begin // DataReg if (ld_data) begin DataReg <= data; $display ("At time %d, %h read from slave address %h", $stime, data, AddrReg); end end R ~access MA access/start, en_addrup Data to Processor MB doread/read=1, en_addrlo DataReg ld_data ~doread/read=0, en_addrlo en_data Bus Transceiver MC ~datavalid MD ~wdatardy/ BusDrivers[7:0] BusRcvrs[7:0] datavalid/ ld_data wdatardy/ dv, en_data data[7:0] 29

30 Next state and output logic R MA MB MC ~access access/start, en_addrup doread/read=1, en_addrlo ~datavalid datavalid/ ld_data ~doread/read=0, en_addrlo MD wdatardy/ dv, en_data ~wdatardy/ Remember: access, read, and write are signals from the processor doing the memory access always_comb begin start = 0; en_addrup = 0; en_addrlo = 0; read = 0; ld_data = 0; en_data = 0; dv = 0; case (State) MA: begin NextState = (access)? MB : MA; start = (access)? 1 : 0; en_addrup = (access)? 1 : 0; end MB: begin NextState = (doread)? MC : MD; en_addrlo = 1; read = (doread)? 1 : 0; end MC: begin NextState = (datavalid)? MA : MC; ld_data = (datavalid)? 1 : 0; end MD: begin NextState = (wdatardy)? MA : MD; en_data = (wdatardy)? 1 : 0; dv = (wdatardy)? 1 : 0; end endcase end Note the descriptive style 30

31 Slave Overview module BusSlave (input logic resetn, clock, input logic start, read, inout datavalid, input logic [7:0] address, inout [7:0] data); logic [7:0] Mem [16'hFFFF: 0], MemData; logic ld_addrup, ld_addrlo, memdataavail = 0; logic en_data, ld_data, dv; logic [7:0] DataReg; logic [15:0] AddrReg; R ~start SA enum {SA, SB, SC, SD} State, NextState; start/ld_addrup clock, negedge resetn) if (~resetn) State <= SA; else State <= NextState; SB SC read/ld_addrlo ~memdataavail memdataavail/ dv, en_data ~read/ld_addrlo SD datavalid/ ld_data ~datavalid/ 31

32 The Slave s Datapath clock) if (ld_addrup) AddrReg[15:8] <= address; clock) if (ld_addrlo) AddrReg[7:0] <= address; R SA SB SC ~start start/ld_addrup read/ld_addrlo ~memdataavail memdataavail/ dv, en_data ~read/ld_addrlo SD datavalid/ ld_data ~datavalid/ ld_data Memory Address[15:0] to Memory en_data MemData Bus Transceiver ld_addrup [15:8] [7:0] ld_addrlo BusDrivers[7:0] BusRcvrs[7:0] AddrReg[15:8] AddrReg[7:0] data[7:0] address[7:0] 32

33 The Slave s Datapath Hmm, didn t use an always_ff? R SA ~start assign data = (en_data)? MemData : 'bz; assign datavalid = (State == SC)? dv : 1'bz; ld_data) // models mem even when AddrReg doesn't change MemData = Mem[AddrReg]; clock)// DataReg if (ld_data) begin DataReg <= data; Mem [AddrReg] <= data; $display ("Time %d, %h written to slave address %h", $stime, data, AddrReg); end SB SC start/ld_addrup read/ld_addrlo ~memdataavail memdataavail/ dv, en_data ~read/ld_addrlo SD datavalid/ ld_data ~datavalid/ ld_data Memory Address[15:0] to Memory en_data MemData Bus Transceiver ld_addrup [15:8] [7:0] ld_addrlo BusDrivers[7:0] BusRcvrs[7:0] AddrReg[15:8] AddrReg[7:0] data[7:0] address[7:0] 33

34 Slave Next state and output logic always_comb begin ld_addrup = 0; ld_addrlo = 0; dv = 0; en_data = 0; ld_data = 0; R SA SB SC ~start start/ld_addrup read/ld_addrlo ~memdataavail memdataavail/ dv, en_data ~read/ld_addrlo SD datavalid/ ld_data ~datavalid/ Remember: dataavail is a signal from the memory that it read a value case (State) SA: begin NextState = (start)? SB : SA; ld_addrup = (start)? 1 : 0; end SB: begin NextState = (read)? SC : SD; ld_addrlo = 1; end SC: begin NextState = (memdataavail)? SA : SC; dv = (memdataavail)? 1 : 0; en_data = (memdataavail)? 1 : 0; end SD: begin NextState = (datavalid)? SA : SD; ld_data = (datavalid)? 1 : 0; end endcase end 34

35 module top; Top module of the interface logic tri tri clock=1, resetn=0; datavalid, start, read; [7:0] data, address; initial $monitor ($stime,,"ms=%s, SS=%s, Addr=%h, data=%h, start=%b, read=%b, datavalid=%b, M.DReg=%h, S.DReg=%h", M.State.name, S.State.name, address, data, start, read, datavalid, M.DataReg, S.DataReg); always #5 clock = ~clock; initial #2 resetn=1; BusMaster M(.* ); BusSlave S(.* ); endmodule address[7:0] data[7:0] start read datavalid Processor Interface Interface Memory Interface 35

36 SystemVerilog Tasks Tasks are akin to programming language procedures They are a separate statement that calls a procedure to execute they re not called from with an expression (like a function) When they return, the next statement executes They may have procedural timing control wait) and <= Values are copied in at the beginning. Task outputs are copied back when it returns. Same with inouts Tasks can be declared automatic then they re re-entrant, having their own copies of their variables Re-entrant is like when 36

37 Tasks how to s These signal the Master to do a write DataReg Being written two different ways???? Where and what to write task WriteMem //task for testbench (input [15:0] Avalue, input [7:0] Dvalue); begin $display("time=%d, setting up a write", $stime); access <= 1; doread <= 0; wdatardy <= 1; AddrReg <= Avalue; DataReg <= clock) access <= clock); wait (State == MA); repeat clock); end endtask Wait until the write cycle is done, then wait a few more clocks before starting again 37

38 Tasks how to s task ReadMem //task for testbench (input [15:0] Avalue); These signal the Master to do a read Where to read from begin $display("time=%d, setting up a read", $stime); access <= 1; doread <= 1; wdatardy <= 0; AddrReg <= clock) access <= clock); wait (State == MA); repeat clock); end endtask Wait until the read cycle is done, then wait a few more clocks before starting again 38

39 The testbench initial begin int i; for (i = 0; i <= 16'hFFFF; i++) Mem[i] = i[7:0]; end initial begin // testbench repeat clock); WriteMem (16'h0406, 8'hDC); ReadMem (16'h0406); WriteMem (16'h0407, 8'hAB); ReadMem (16'h0406); ReadMem (16'h0407); $finish; initialize memory wait for a little time and then start writing and reading things end 39

40 Waiting for random amounts of time // testbench memory takes random cycles to access begin: randomwait bit [2:0] delay; memdataavail <= 0; if (State == SC) begin delay = $random; $display ("random delay = %d, time = %d", delay, $stime); repeat clock); // delay at least two $display ("finished delay at time = %d", $stime); memdataavail <= 1; end end R ~start SA delay = $urandom_range(9,2); This creates a random number in the range of 9 through 2 that s the number of clock periods to wait. models memory access delay SB SC start/ld_addrup read/ld_addrlo ~memdataavail memdataavail/ dv, en_data ~read/ld_addrlo SD datavalid/ ld_data ~datavalid/ 40

41 Points to take away Reason for synchronizing? To know the state of the other machine you re synchronizing with Synchronized FSMs Linked through reset, clock, signals, and number of states Knowing what state another FSM is in Different views of a protocol Synchronous? Synchronous in terms of all signals Asynchronous in terms of bus cycle length Clock-cycle accurate modeling SystemVerilog Tasks 41

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