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1 New! New! New! New! New! Models 72664, Model Model General Information Models 72664, are members of the Cobalt family of high-performance CompactPCI s based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 764 XMC modules mounted on a cpci carrier. Model is a 6U cpci while the Model is a 3U cpci ; both are equipped with one Model 764 XMC. Model is a 6U cpci with two XMC modules rather than one. The output of these models supports fully the VITA-49.1 Radio Transport Standard. These models include four or eight s, four or eight multiband s and four or eight banks of memory. The Cobalt Architecture The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the s data and control paths are accessible by the FPGA, enabling facry-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with facry-installed applications ideally matched the s analog interfaces. The facry-installed functions of these models include four or eight acquisition IP modules. Each of the acquisition IP modules contains a powerful, programmable IP core. IP modules for either or memories, controllers for all data clocking and synchronization functions, a test signal generar, a programmable beamforming IP core, an Aurora gigabit serial interface, and a interface complete the facry- installed functions and enable these models operate as complete turnkey solutions without the need develop any FPGA IP. Extendable IP Design For applications that require specialized function, users can install their own cusm IP for data processing. Pentek GateFlow FPGA Design Kits include all of the facry installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Xilinx Virtex-6 FPGA The Virtex-6 FPGA site can be populated with two different FPGAs match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Features Complete radar and software radio interface solutions Support VITA-49.1 Radio Transport Standard Support Xilinx Virtex-6 LXT and SXT FPGAs Four or eight -bit s Four or eight multiband s (digital downconverters) One or two multi programmable beamformers Up 2 or 4 GB of ; or: 32 MB or 64MB of Sample clock synchronization an external system reference LVPECL clock/sync bus for multi synchronization Block Diagram, Model Model doubles all resources except the PCI--PCI Bridge Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus MODEL INTEACES ONLY LVDS Aurora I/O Sum previous J2 VIRTEX-6 FPGA Sum next TIMING BUS Clock / Sync / Gate / PPS PCI VCXO PCI/PCI-X BUS 32-bit, 33/66 MHz Clock/Sync Bus option 150 option 155 -BIT -BIT option 0 option 5 orybanks1&2 ory Banks 3&4 Config FLASH 64 MB -BIT VIRTEX-6 FPGA LX240T or SX315T Sum previous J3 -BIT Aurora Gigabit Serial I/O Sum next x4 PCI From/To Other XMC Module of MODEL PCI PCI PCI/PCI-X BUS 32/64-bit, 33/66 MHz

2 Acquisition IP Modules These models feature four or eight Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data any of the four s or a test signal generar Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s job of identifying and executing on the data. providing a wide range satisfy most applications. The decimating filter for each accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each delivers a complex output stream consisting of 24-bit I + 24-bit Q or-bit I + -bit Q samples at a rate of ƒ s /N. Beamformer IP Cores In addition the s, these models feature one or two complete beamforming subsystems. Each core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up 8K samples. The power meters present average power measurements for each core output in easy--read registers. In addition, each core includes a threshold detecr aumatically send an interrupt the processor if the average power level of any core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the four core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and Ch 1 Ch 2 threshold detect block is provided for the summed output. The output is then directed back in the Acquisition IP Module 1 FIFO for reading over the. For larger systems, multiple 761 s can be chained gether via a built-in Xilinx Aurora gigabit serial interface through the P XMC connecr. This allows summation across channels on multiple s. VITA-49 The VITA-49 specification addresses the problem of interoperability between different elements of Software Defined Radio (SDR) systems. Specifically each SDR receiver manufacturer typically develops cusm and proprietary digitized data and metadata formats, making interoperability of data different receivers impossible. VITA-49 solves this problem by providing a framework for SDR receivers used for analysis of spectrum and localization of emmisions. It is based upon a transport procol layer convey timestamped digital data between components in the system. With a common procol, SDR receivers can be interchanged, thereby enabling hardware upgrades and mitigating hardware lifecycle limitations. This eliminates the need create new software support each new receiver. These models support fully the VITA specification. Ch 3 Ch 4 IP Cores Within each Acquisition IP Module is a powerful IP core. Because of the flexible input routing of the Acquistion IP Modules, many different configurations can be achieved including one driving all four s or each of the four s driving its own. Each has an independent 32-bit tuning frequency setting that ranges DC ƒ s, where ƒ s is the sampling frequency. Each can have its own unique decimation setting, supporting as many as four different output bandwidths for the. Decimations can be programmed 2 65,536 TEST SIGNAL next Bank 1 AURORA GIGABIT SERIAL INTEACE FLOW IP MODULE 1 sum out SUMMER sum in BEAMFORMER CORE previous FLOW MUX MUX MUX MUX Bank 2 Bank 3 Bank 4 IP MODULE 2 INPUT MULTIPLEXER FLOW IP MODULE 3 VIRTEX-6 FPGA DATAFLOW DETAIL MUX CORE CORE CORE CORE FLOW IP MODULE 4 INTEACE

3 Converter Stage The front end accepts four or eight analog HF or IF inputs on front panel SSMC connecrs with transformer coupling in four or eight Texas Instruments ADS5485, -bit converters. The digital outputs are delivered in the Virtex-6 FPGA for signal processing, data capture and for routing other module resources. Clocking and Synchronization An internal timing bus provides all timing and synchronization required by the converters. It includes a clock, two sync and two gate or trigger signals. An on- clock generar receives an external sample clock the front panel SSMC connecr. This clock can be used directly by the or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced an on- programmable voltage controlled crystal oscillar. In this mode, the front panel SSMC connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel 26-pin LVPECL Clock/Sync connecr allows multiple s be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple s. Multiple s can be driven the LVPECL bus master, supporting synchronous sampling and sync functions across all connected s. ory Resources The Cobalt architecture supports up four or eight independent memory banks which can be configured with all,, or as combination of two banks of each type of memory. Each bank can be up 8 MB deep and is an integral part of the module s DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, banks can each be up deep. Built-in memory functions include multichannel data capture, tagging and streaming. In addition the facry-installed functions, cusm user-installed IP within the FPGA can take advantage of the memories for many other purposes. PCI-X Interface These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers and the. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73664: 32 bits only.

4 Ordering Information Model Description Channel with s, VITA-49, one Virtex-6 FPGA - 6U cpci Channel with s, VITA-49 one Virtex-6 FPGA - 3U cpci Channel with s, VITA-49, two Virtex-6 FPGAs - 6U cpci Options: -062 XC6VLX240T -064 XC6VSX315T -150 Two 8 MB ory Banks (Banks 1 and 2) -0 Two 8 MB ory Banks (Banks 3 and 4) -155 Two ory Banks (Banks 1 and 2) -5 Two ory Banks (Banks 3 and 4) Specifications Model or Model 73664: 4 s Model 74664: 8 s Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz Resolution: bits Digital Downconverters (4 or 8) Quantity: Four channels Decimation Range: 2x 65,536x in two stages of 2x 256x LO Tuning Freq. Resolution: 32 bits, 0 ƒ s LO SFDR: >120 db Phase Offset Resolution: 32 bits, degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Beamformers (1 or 2) Summation: Four channels on-; multiple s can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connecr using Aurora procol Phase Shift Coefficients: I & Q with -bit resolution Gain Coefficients: -bit resolution Channel Summation: 24-bit Multi Summation Expansion: 32-bit Sample Clock Sources (1 or 2) On- clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable on- programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the clock External Clocks (1 or 2) Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin connecr LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/pps inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T ory Banks (1 or 2) Option 150 or 0: Two 8 MB memory banks, 400 MHz DDR Option 155 or 5: Two memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73664: 32 bits only Environmental Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, non-cond. Size: Standard 6U or 3U cpci

5 Performance Spurious Free Dynamic Range Spurious Pick-up f in =, Internal Clock f s =, Internal Clock Two-Tone SFDR Two-Tone SFDR f 1 = 30 MHz, f 2 = f 1 = 69 MHz, f 2 = 71 MHz, f s = Adjacent Channel Crosstalk Crosstalk Input Frequency Response f in Ch2 =, Ch 1 shown f s =, Internal Clock

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