A B A+B

Transcription

1 ECE 25 Lab 2 One-bit adder Design Introduction The goal of this lab is to design a one-bit adder using programmable logic on the BASYS board. Due to the limitations of the chips we have in stock, we need to design it using only the 2 input NAND gates introduced in Lab 1. Prelab Before we design such a circuit, we need to first understand what a one-bit adder is. Similarly to how humans represent numbers using a decimal base, computers represent numbers with a binary base. The goal is to design a circuit with the following truth table: A B A+B Notice that we need two outputs to represent the result of a binary addition. By convention, we will call the least significant digit the result bit and the most significant digit the carry bit. We will start designing the result bit which shares the same truth table as a XOR gate. To express an XOR gate with NAND gates we can start with A XOR B = AB + A B and draw a simple schematic with AND, NOT, and OR gates. "Push the bubbles until you have only 5 NAND gates. Pushing the bubble is the visual explanation of De Morgan s Law, where the bubble, a NOT gate, is pushed through a gate. Pushing a bubble through will change the logic gate and invert the inputs as shown below. Hint: Put two bubbles at each OR gate input and push one of them through. You must show any work that you performed to get the results (Boolean algebra, pushing bubbles, cascading design, etc.). Draw a 2 bit XOR gate using 5 2-input NAND gates by using the methods described above. Do not justify your design with techniques not covered in this class. You were just given sufficient directions to come up with the proper design. -Turn in the hand drawn design in the prelab.

2 Alternatively, we can take a mathematical approach and reduce the gate count to 4 by starting with A XOR B = (A + B )(A + B). (Hint: distribute the content in the second parentheses and then do De Morgan s Law three times.) Convince yourself that they are equivalent by the distributive property. Draw a 2 bit XOR gate using only 4 2-input NAND gates using the above method. -Turn in your derivation in the prelab. In the 4 gate design, we can reuse the result of the first NAND gate and add one NOT gate to represent the carry bit output (AB = carry). Remember to implement this NOT gate using 2- input NAND gates. Use the Vivado Design Suite to implement the adder we designed above. This requires learning the software. Before you start the prelab, make sure to go through the "Vivado Guide" tutorial on the Lab Website. There you will learn the steps needed to finish this prelab. You may also need to refer to the Lab Reference section for additional information. After completing the tutorial (no need to turn it in), you will have to start a new project to do this prelab. Print out both the gate level Verilog code of the adder and its corresponding timing diagram from Simulation showing all 4 possible output states. Remember that the inputs and outputs of your circuit need to be labeled using the format listed in the tutorial. Failure to follow the labeling procedure will result in a zero grade for the Pre-lab. Also, the tutorial code is not the same code which you are being asked to write here. In the prelab include the gate-level Verilog code and simulation for the 5 NAND gate adder design. Lab Upon further investigation, it is obvious that our design in the prelab has a flaw: if we want to add multiple-bit binary numbers together, the adder cannot handle the carry bit of the previous digit! That is why we call the above design a half adder. Now, we need to refine our design to handle the carry bit and thus make a full adder. The truth table is shown below. A B Carry A+B Result1+(Carry in) A+B+(Carry in) in Carry1 Result1 Carry2 Result2 Carry-out Result

3 For a full adder, we want to get the truth table as shown in the last column. From the other two columns, it is apparent that we can make a full adder by connecting two half adder in series and then to OR both carries. Convince yourself about this design. Build the Full Adder To build the full adder, we will use a top module in Verilog, which is a common technique to separate logic and implementation. (Moreinfo about top module in the Lab Reference) Create a new source. Follow all the setup steps as usual, but now instantiate the module you defined in the prelab as shown in the simulation part. For example, use: yourhalfadder halfadder1(input, output); <- order might change for your design Finish all the connections as shown in the diagram above before you proceed to the next part. Downloading and verifying full adder Design Download your Xilinx design from the prelab onto your BASYS3 board following the procedure in the Vivado tutorial. Use SW15(A), SW14(B), and SW13(Carry-in) to control the 3 inputs of your full adder and have your full adder output to two LEDs (LD15(Result), LD14(Carry-out)). Note that even if you have downloaded the design onto your board outside class before lab, you may have to do this again during lab starting from the schematic. The pin out for the programmable chip and expansion connector can found on the Lab Reference pg.4 on the Lab Web site. Review the Vivado tutorial section: Downloading verified design into programmable chip if necessary. Demonstrate the functionality to a TA once completed.

4 Manual implementation of a full adder Next you will build your full adder from 2-bit NAND gates on your breadboard (you should use the 4 NAND gate design you came up with during pre-lab). We will be using the 74LS00N two-input NAND gates from Lab 1. The pin out is shown above. Remember to power the chip with VCC going to pin 14 and ground going to pin 7 of the IC. These chips should be powered from the bench top power supply using 5V. Because your design should implement a half adder cascaded with another to make it a full adder, check the half adder after you have finished building that part of it to make sure that it works. Notice that you can push the bubbles for the OR gate in carry-out to the last not gate in the half adder. This will reduce the overall number of NAND gates needed. In order to test the design, program the connections in the same way as in lab 1. Namely, you should connect SW15 to JA1, SW14 to JA2, SW13 to JA3, LD15 to JA7, and LD14 to JA8. Now, load this to your BASY3 board. Review the Vivado tutorial section: Downloading verified design onto programmable chip, if necessary. Get the first half adder working before you move on to the the rest of the circuit. Test your circuit by trying all possible inputs. Does the output behavior match the output of your Xilinx design? Have the TA sign your sheet and move on to the next step.

5 Use of the logic analyzer We will now test the full adder circuit using the counter chip (CD4516) from Lab 1 and a logic analyzer instead of the switches from the BASY3 board. You can disconnect all wires from your BASYS3 board as you will not be using it for this section. Power the counter chip using the bench top power supply by setting Pin 16 and Pin 10 to 5 volts. Be sure you ground pins 1, 5, 8, and 9. Wire the 3 least significant bits of the counter chip into the inputs of the full adder circuit. These should be Q1, Q2, and Q3. Pin 15 will connect to your function generator and will serve as the clock. Set the clock signal at 1 khz with a 0 to 3.3V pk-pk signal (i.e. offset the voltage to have only positive voltage). Next, attach the logic analyzer to your circuit and to your computer. The analyzer connects to the computer through a USB port. Hook the grey lead of the logic analyzer to ground, the black lead to the Q1, the brown lead to the Q2, the red lead into the Q3, the orange lead to the carry bit, and the yellow lead to the result bit. If a lead is missing or broken, it is OK to substitute another, however Q1-Q3 and the LED need to be in the same order listed so that they display correctly. There is a program for the logic analyzer called Logic. Find it through the start menu (All Programs ---> SALEAE LLC ---> Logic), or click on the desktop shortcut and open it. The window should look similar to the figure below but will not have the same waveform.

6 Click the "Start" button. Use your mouse to zoom in and out (right click to zoom out and left click to zoom in), until you can see at least 1 complete cycle. Compare the output with the results from your Xilinx simulation you made during prelab. The results should be the same. If it does not work, begin checking the first half of your circuit, because the 2 input for the first half adder should be wired correctly. Have the TA sign your sheet once your logic analyzer output matches your simulation from prelab. Discuss in your lab report The relationship between pushing bubbles and De Morgan s Law The design and implementation of the full adder with Vivado The design and implementation of the full adder with physical NAND gates What was the purpose of the logic analyzer in this lab? Why not just use an O-scope? Now you should be able to understand the code given in the previous project. Briefly explain how [a:b] works in Verilog and how to use assign. (you will be using [a:b] a lot later in the labs because it can save a lot of time in connecting modules) *Make sure you get this lab working because you will need this lab again in lab 5.