A Fast Powertrain Microcontroller. Erik Norden, Patrick Leteinturier, Jens Barrenscheen, Klaus Scheibert, Frank Hellwig. Steering.

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1 A Fast Powertrain Microcontroller Infineon Hot Chips 16 Erik Norden, Patrick Leteinturier, Jens Barrenscheen, Klaus Scheibert, Frank Hellwig N e v e r s t o p t h i n k i n g. Trend: Global Chassis Control: Functions within Dynamic & Powertrain Grow Together Mech. Steering STEERING EHPS TRACTION TCM EMS EPS Rear Steering Hybrid 4x4 Fault-Tolerant Steering Steering Traction E-Car Braking Suspension ABS Mech. Braking EHB ESP EBA... ASR BRAKING EMB Active Suspension Semiactive Damping Dynamic Leveling Load Leveling SUSPENSION Mech. Damping Seite 1

2 Trends: Distributed Systems in s Software Powertrain Management Distributed systems in vehicles Distributed smart sensors, actuators, computation New opportunities for scalability, flexibility, reusability, composability Infineon is member of the FlexRay consortium Software will play an increasing role s Drive & Feel will become increasingly defined by algorithms and software Energy Management Engine Control Thermal Management Start/ Stop 42V Starter- Generator i.e. SW will become a significant element in brand differentiation Minimal Hybrid Transmission Control Telematics Brake-bywire Surround Sensing Adaptive Cruise Control Steer-bywire Chassis Management Software complexity increases and will be a compilation of different vendor s contributions A change in SW development methodology will occur New SW interfaces will become standard, encapsulation will be needed Infineon is member of the AutoSAR development partnership Guidance Powertrain Trends Semiconductor Content Indirect Injection Direct Injection Cam-less Engine Electronic Turbo Charger Full-Hybrid Hybrid Mini-Hybrid Fuel Cell Electric Low Emission & Low Consumption Seite 2

3 Less Fuel Consumption and Cleaner Engines - Driving Forces for Higher Performance 50 Performance 12 Performance relative to 1980 (=1) Average Fuel consumption 1978: : 80C : : C167 EURO1 AUDO-NG 2002: AUDO Emission EURO Liter / 100km CO-Emission g/km source: VDA, own estimations year Year of introduction : Infineon Microcontroller Type EUROx=European Emission Standards Optimized Partitioning for Powertrain Today - Example Conventional Engine Management Tomorrow Optimized Chip Set by Infineon + Vbatt CAN bus + Vbatt Sensors Hall Sensor Knock Rotary speed Sensors Hall Vol.Reg Sensor Supply Sensor Knock? CAN- Transceiver Safety µc Flash SRAM Main 32 bit µc EEPROM Supervision Module High Pincount 50 ma 3A - 4A 2A - 3A 0,5A Driver Main Relais CAN bus Vol.Reg Sensor Sensor Supply Supply Supervision CAN/LIN-Transceiver Module Transceiver I- Chip Sensors AUDO NG AUDO NG 32 bit µc TC Ignition 2A - 3A 2A-3A 3A - 4A 3A - 4A 0.5A IC 1 50mA Driver Main Driver Relais 6A Bridge Sensors Ignition 6A Bridge => Saves System Costs Seite 3

4 AUDO-Next Generation (NG): TC At a Glance 32-bit superscalar TriCore V1.3 CPU 32-bit Control Processor (PCP2) Multi-channel DMA controller Powerful & flexible peripheral set 2.5 x GPTA (flexible timer array) MultiCAN (4 nodes) 2x ASC and 2x SSC Interfaces 2x µs-bus Interfaces (MSC) Multi-Processor Interface (MLI) Multi-channel ADCs, FAST ADC On-chip Memory: 2.1 MByte Flash Memory (partially supports EEPROM emulation) 192 kbyte SRAM, 16 kbyte Program Cache 48 kbyte SRAM for PCP2 Digital Port Supply Voltage 2.3V - 3.3V Full automotive temperature range Package: P-BGA 416 AUDO-NG: TC The Three Layer Implementation Application Layer Transfer Layer Layer To allow the right function partitioning with clear interfaces, Infineon has design the three layer approach. Seite 4

5 AUDO-NG: TC Block Diagram Instruction Level Parallelism TriCore can execute up to 3 instructions in parallel per cycle In parallel, the PCP executes its own instructions Seite 5

6 Data Level Parallelism TriCore s packed arithmetic allows to process up to 4 data per instruction In parallel, the PCP processes e.g. data from the GPTA The DMA unit transfers data e.g. from the FADC Intelligent peripherals handle data in parallel Non-Intrusive Data Transfer Capability No Penalty for TriCore and PCP DPRAM Remote Bus Cost for the TriCore/PCP - Usage = 0 - Wait = 0 >30 Mbit/s DMA MLI SSC SSC ADC ADC FADC 16 bit 10 Mbit/s 16 bit 10 Mbit/s > 500 k.samples/s > 500 k.samples/s 3.5 M.Samples/s Seite 6

7 TriCore Architecture Designed for Embedded Real Time Applications MMU * FPU COP I/F Program Cache and Scratch Memory Program Memory Interface Data Memory Interface Data Memory * not implemented in TC Interrupt 64 Dual LMB Bus - split in PLMB and DLMB High performance 32-bit core The first unified RISC/DSP architecture 150 MHz / 4 stage superscalar pipeline Fast context switch mechanism Fast, deterministic interrupt mechanism Floating point unit (optional) Flexible coprocessor interface For up to 3 coprocessors Optional memory management unit * Configurable cache and memory sizes Fast local memory bus system TriCore Architecture Powerful Interrupt Service System Features Up to 4 x 255 request nodes (SRN), concurrently supported Parallel arbiter HW to select highest interrupt & clear when accepted Automatic context save during branch to interrupt routine Benefits Meets real-time requirements Zero software overhead Ease of programming, High flexibility Large number of SRNs Flexible grouping of request into priority groups SRN SRN SRC SRC SRN SRC SRN SRC SRN SRC SRN SRC Arbitration Bus FPI Bus Int. Ack. Int. Req. Interrupt Control Unit (ICU) Seite 7

8 PCP2 Coprocessor PCP2 is a full 32 bit user programmable processor dedicated to communication and driver activities Off-loads TriCore from handling interrupt tasks (hardware arbitration & register context switch, 255 priority levels) Includes DMA engine PCP2 can run autonomously Flywheel, Injection, Ignition driver software Modules: GPTA General Purpose Timer Array Unified High Functionality and Flexibility FPC 00 FPC 01 FPC 02 FPC 03 FPC 04 FPC 05 Function blocks for Input signal conditioning and analysis Digital PLL Capture/Compare Cell Arrays Flexible timer array PDL 00 PDL 01 DCM 00 DCM 01 DCM 02 DCM 03 DIGITAL PLL Highly functional structure: Largely autonomous operation requiring low or no SW overhead Main CPU not loaded with highly repetitive tasks Permits optimized use of timer cells Scalable functionality avoids functional overhead Maximizes system functionality GT 0 GT 1 GTC 00 GTC 01 GTC 02 GTC 03 GTC 04 Cell Array Global Timer Clock Bus LTC 00 LTC 01 LTC 02 LTC 03 LTC 04 Cell Array Local Timer Architecture driven by needs for: 8-cylinder combustion engines 3-phase AC-motor GTC 30 GTC 31 LTC 62 LTC 63 Seite 8

9 Modules: MultiCAN Feature Set and Module CAN functionality conform to CAN specification V2.0 B active (compliant to ISO 11898) 4 independent CAN nodes available 128 independent message objects (message objects are shared by the CAN nodes) Data transfer rate up to 1MBaud, individual programmable for each node Flexible and powerful message transfer control and error handling capabilities to offload CPU Automatic gateway mode support 16 individually programmable interrupt outputs CAN Analyzer Mode for bus monitoring Time-Triggered CAN (TTCAN) support Time Triggered CAN (TTCAN) Enhancements Modules: Fast ADC Application Example: Knock Detection Remove expensive external filters Reduce system cost Allow better utilization of the input signal range Allow better signal diagnosis Self test, explore signal consistency High sampling frequency Up to 3.5 M sample/s with 10 bit resolution Configurable HW differential amplifier Reduce cost on external HW Improved common mode noise rejection Configurable digital data compression Reduce software load Result of DSP calculation: decision for Knock Detection R fast 10 bit ADC converter (approx. 3Msamples/s) C analog low pass input filter SRAM FLASH EBU TC ksamples/s 200ksamples/s FFT PMU FPU TriCore TC 1.3 LMB System FIR (11th order) DSP - Calculations av=4, ov=2 CPU Bus DMU LFI SPSRAM DPSRAM Bridge DMA av=2, ov=3 Filter 0 Filter 1 data reduction filter with moving averaging FADC with concatenated comb filters Remote Bus Seite 9

10 Modules: MLI / MSC Multicore/Device Link via High Speed MLI and MSC Micro Link Interface (MLI) to connect smart companion devices Micro Second Channel (MSC) to primarily connect power devices Benefit: Highly configurable and scalable the wiring on the board amount of pins per package the bandwidth but EMI Low swing and smooth edge Open license policy on MLI, MSC IFX will provide Open Market Specification MLI: Micro Link Interface >30 Mbit/s full duplex Analog Front-End Analog Front-End Transceivers 8 8 Micro- Controller 1 8 Micro- Controller 2 Power Supply MSC: µsecond channel Interface >30 Mbit/s (LVDS) Smart-Power Next Generation Smart-Power Next Generation Remote Protocol Engine ECU Transceivers Tuning Protection and Authentication IP IP Snatcher Snatcher Microcontroller Theft Theft Flash EEPROM CPU Debug RAM EEPROM TTCAN anti theft system Tuner Tuner Seite 10

11 Traditional approach - expensive solutiondue to additional necessary HW PC TC1796ED Emulation Device Thick, Short Nexus Cable thin cable Serial link, e.g. Ethernet, USB Emulator HW Calibration HW TC1796ED covers complete emulator functionality, fast prototyping and calibration Emulation logic is next to production chip On the same silicon High frequency capability High amount of traceable signals (on mask level) Production & emulation have the same behavior Infineon s approach - high Easy link to standard PC e.g. USB functionality and cost effective Interface TC1796 and 1796ED using the same footprint with TC1796ED No need to develop different PCB PC Extra balls for the ED Tool connector on top TC1796 and TC1796ED Mass Production Device: Bonding SoC (TC17x6) Emulation Device: Bonding with EEC EEC SoC (TC17x6) Seite 11

12 Summary TC1796 serves upcoming trends in powertrain applications Fullfills highest performance requirements including soft- and hard real-time Intelligent peripherals Optimized bus system Unified CPU/DSP and peripheral coprocessor Reduces system cost Powerful emulation support Thank you for your attention Questions? Never stop thinking Seite 12