PSoC 4 BLE TRM. PSoC 4 BLE Architecture Technical Reference Manual (TRM) PSoC 41XX_BLE/42XX_BLE Family. Document No Rev.

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1 PSoC 4 BLE TRM PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture Technical Reference Manual (TRM) Document No Rev. *D May 31, 2017 Cypress Semiconductor 198 Champion Court San Jose, CA Phone (USA): Phone (Intnl):

2 Copyrights Copyrights Cypress Semiconductor Corporation, This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PUR- POSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. 2 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

3 Contents Overview Section A: Overview Introduction Getting Started Document Construction Section B: CPU System Cortex-M0 CPU DMA Controller Modes Interrupts Section C: System Resources Subsystem (SRSS) I/O System Clocking System Power Supply and Monitoring Chip Operational Modes Power Modes Watchdog Timer Reset System Device Security Section D: Digital System Serial Communications Block (SCB) Universal Digital Blocks (UDB) Timer, Counter, and PWM Bluetooth Low Energy Subsystem (BLESS) Section E: Analog System Precision Reference SAR ADC Low-Power Comparator Continuous Time Block mini (CTBm) LCD Direct Drive CapSense Temperature Sensor Section F: Program and Debug 325 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 3

4 Contents 26. Program and Debug Interface Nonvolatile Memory Programming Glossary 349 Index PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

5 Contents Section A: Overview 17 Document Revision History Introduction Top Level Architecture Features CPU System Processor Interrupt Controller Direct Memory Access Memory Flash SRAM System-Wide Resources Clocking System Power System GPIO Bluetooth Low-Energy Subsystem RF Transceiver Digital PHY Modem Link Layer Controller Programmable Digital Fixed-Function Digital Timer/Counter/PWM Block Serial Communication Blocks Analog System SAR ADC Continuous Time Block mini Low-Power Comparators Special Function Peripherals LCD Segment Drive CapSense IDACs and Comparator Program and Debug Device Feature Summary Getting Started Support Product Upgrades Development Kits Application Notes...29 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 5

6 Contents 3. Document Construction Major Sections Documentation Conventions Register Conventions Numeric Naming Units of Measure Acronyms...32 Section B: CPU System 35 Top Level Architecture Cortex-M0 CPU Features Block Diagram How It Works Address Map Registers Operating Modes Instruction Set Address Alignment Memory Endianness Systick Timer Debug DMA Controller Modes Block Diagram Description Trigger Sources and Multiplexing Trigger Multiplexer Creating Software Triggers Pending Triggers Output Triggers Channel Prioritization Data Transfer Engine Descriptors Address Configuration Transfer Size Descriptor Chaining Transfer Mode Single Data Element Per Trigger (OPCODE 0) Entire Descriptor Per Trigger (OPCODE 1) Entire Descriptor Chain Per Trigger (OPCODE 2) Operation and Timing Arbitration Register List Interrupts Features How It Works Interrupts and Exceptions - Operation Interrupt/Exception Handling Level and Pulse Interrupts Exception Vector Table Exception Sources PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

7 Contents Reset Exception Non-Maskable Interrupt (NMI) Exception HardFault Exception Supervisor Call (SVCall) Exception PendSV Exception SysTick Exception Interrupt Sources Exception Priority Enabling and Disabling Interrupts Exception States Pending Exceptions Stack Usage for Exceptions Interrupts and Low-Power Modes Exceptions Initialization and Configuration Registers Associated Documents...65 Section C: System Resources Subsystem (SRSS) 67 Top Level Architecture I/O System Features GPIO Interface Overview I/O Cell Architecture Digital Input Buffer Digital Output Driver Drive Modes Slew Rate Control GPIO-OVT Pin High-Speed I/O Matrix I/O State on Power Up Behavior in Low-Power Modes Input and Output Synchronization Interrupt Peripheral Connections Firmware Controlled GPIO Analog I/O AMUXBUS Connection and DSI LCD Drive CapSense Bluetooth Low Energy Sub-System (BLESS) Serial Communication Block (SCB) Port Restrictions Registers Clocking System Block Diagram Clock Sources Internal Main Oscillator Startup Behavior IMO Frequency Spread Programming Clock (36-MHz) Internal Low-speed Oscillator...86 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 7

8 Contents External Clock (EXTCLK) External Crystal Oscillator (ECO) ECO Load Capacitor Tuning Watch Crystal Oscillator (WCO) Clock Distribution HFCLK Input Selection LFCLK Input Selection ECO Divider Configuration SYSCLK Prescaler Configuration Peripheral Clock Divider Configuration Peripheral Clock Configuration Clock Generation Low-Power Mode Operation Register List Power Supply and Monitoring Block Diagram How It Works Regulator Summary Core Regulators RF Transceiver Regulators Voltage Monitoring Power-On-Reset (POR) Brownout-Detect (BOD) Low-Voltage-Detect (LVD) Register List Chip Operational Modes Boot User Privileged Debug Power Modes Active Mode Sleep Mode Deep-Sleep Mode Hibernate Mode Stop Mode Power Mode Summary Low-Power Mode Entry and Exit Register List Watchdog Timer Features Block Diagram How It Works Enabling and Disabling WDT WDT Operating Modes WDT Interrupts and Low-Power Modes WDT Reset Mode Register List PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

9 Contents 13. Reset System Reset Sources Power-on Reset Brownout Reset Watchdog Reset Software Initiated Reset External Reset Protection Fault Reset Hibernate Wakeup Reset Stop Wakeup Reset Identifying Reset Sources Register List Device Security Features How It Works Device Security Flash Security Section D: Digital System 117 Top Level Architecture Serial Communications Block (SCB) Features Serial Peripheral Interface (SPI) Features General Description SPI Modes of Operation Motorola SPI Texas Instruments SPI National Semiconductors SPI Using SPI Master to Clock Slave Easy SPI Protocol EZ Address Write Memory Array Write Memory Array Read Configuring SCB for EZSPI Mode SPI Registers SPI Interrupts Enabling and Initializing SPI Internally and Externally Clocked SPI Operations Non-EZ Mode of Operation EZ Mode of Operation UART Features General Description UART Modes of Operation Standard Protocol SmartCard (ISO7816) IrDA UART Registers UART Interrupts Enabling and Initializing UART PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 9

10 Contents 15.4 Inter Integrated Circuit (I2C) Features General Description Terms and Definitions Clock Stretching Bus Arbitration I2C Modes of Operation Write Transfer Read Transfer Easy I2C (EZI2C) Protocol Memory Array Write Memory Array Read I2C Registers I2C Interrupts Enabling and Initializing the I2C Configuring for I2C Standard (Non-EZ) Mode Configuring for EZI2C Mode Internal and External Clock Operation in I2C I2C Non-EZ Mode of Operation I2C EZ Operation Mode Wake up from Sleep Master Mode Transfer Examples Master Transmit Master Receive Slave Mode Transfer Examples Slave Transmit Slave Receive EZ Slave Mode Transfer Example EZ Slave Transmit EZ Slave Receive Multi-Master Mode Transfer Example Multi-Master - Slave Not Enabled Multi-Master - Slave Enabled Universal Digital Blocks (UDB) Features How It Works PLDs PLD Macrocells PLD Carry Chain PLD Configuration Datapath Overview Datapath FIFOs FIFO Status Datapath ALU Datapath Inputs and Multiplexing CRC/PRS Support Datapath Outputs and Multiplexing Datapath Parallel Inputs and Outputs Datapath Chaining Dynamic Configuration RAM Status and Control Module PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

11 Contents Status and Control Mode Control Register Operation Parallel Input/Output Mode Counter Mode Sync Mode Status and Control Clocking Auxiliary Control Register Status and Control Register Summary Reset and Clock Control Module Clock Control Reset Control UDB POR Initialization UDB Addressing System Bus Access Coherency Simultaneous System Bus Access Coherent Accumulator Access (Atomic Reads and Writes) Port Adapter Block PA Data Input Logic PA Port Pin Clock Multiplexer Logic PA Data Output Logic PA Output Enable Logic PA Clock Multiplexer PA Reset Multiplexer Timer, Counter, and PWM Features Block Diagram Enabling and Disabling Counter in TCPWM Block Clocking Events Based on Trigger Inputs Output Signals Signals upon Trigger Conditions Interrupts Outputs Power Modes Modes of Operation Timer Mode Block Diagram How It Works Configuring Counter for Timer Mode Capture Mode Block Diagram How it Works Configuring Counter for Capture Mode Quadrature Decoder Mode Block Diagram How It Works Configuring Counter for Quadrature Mode Pulse Width Modulation Mode Block Diagram How It Works Other Configurations Kill Feature PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 11

12 Contents Configuring Counter for PWM Mode Pulse Width Modulation with Dead Time Mode Block Diagram How It Works Configuring Counter for PWM with Dead Time Mode Pulse Width Modulation Pseudo-Random Mode Block Diagram How It Works Configuring Counter for Pseudo-Random PWM Mode TCPWM Registers Bluetooth Low Energy Subsystem (BLESS) Features Block Diagram How it Works LFCLK Initialization Radio-PHY Block Power Supply RF Initialization Link Layer Controller Clocking Firmware Reset BLE Functional Modes and Configuration Power Modes Deep Sleep Mode Sleep Mode Idle Mode Transmit Mode Receive Mode Mode Transitions LL Sleep Mode Entry with Auto Wakeup LL Sleep Mode Entry with No Auto Wakeup Manual Exit from Sleep Mode LL Deep Sleep Mode Entry with Auto Wakeup LL Extended Deep Sleep Mode Entry LL Deep Sleep Mode Manual and Auto Exit LL Extended Deep Sleep Mode Manual Exit Bluetooth LE 4.2 Feature Data Length Extension Bluetooth LE 4.2 Feature Privacy Resolving List Resolving List Functions Handling Peer Devices that Do Not Use RPA Handling Unresolved Self RPA Register Details Section E: Analog System 245 Top Level Architecture Precision Reference Features Block Diagram PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

13 Contents 18.3 How it Works Precision Bandgap Trim Buffer Low-Power Buffers Current Mirrors Temperature-Controlled Voltage Generator Temperature-Controlled Current Generator Configuration SAR ADC Features Block Diagram How it Works SAR ADC Core Single-ended and Differential Mode Input Range Result Data Format Negative Input Selection Resolution Acquisition Time SAR ADC Clock SAR ADC Timing SARMUX Analog Routing Analog Interconnection SARREF Reference Options Bypass Capacitors Input Range versus Reference SARSEQ Averaging Range Detection Double Buffer Injection Channel Interrupt End-of-Scan Interrupt (EOS_INTR) Overflow Interrupt Collision Interrupt Injection End-of-Conversion Interrupt (INJ_EOC_INTR) Range Detection Interrupts Saturate Detection Interrupts Interrupt Cause Overview Trigger DSI Trigger Configuration SAR ADC Status Low-Power Mode System Operation Register Mode SARMUX Analog Routing Global SARSEQ Configuration Channel Configurations Channel Enables Interrupt Masks PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 13

14 Contents Trigger Retrieve Data after Each Interrupt Injection Conversions DSI Mode Firmware Analog Routing DSI Analog Routing Global SARSEQ Configuration DSI Channel Configuration Interrupt Trigger Retrieve Data DSI Output Enable Analog Routing Configuration Example Temperature Sensor Configuration Registers Low-Power Comparator Features Block Diagram How It Works Input Configuration Output and Interrupt Configuration Power Mode and Speed Configuration Hysteresis Wakeup from Low-Power Modes Comparator Clock Offset Trim Register Summary Continuous Time Block mini (CTBm) Features Block Diagram How It Works Power Mode Configuration Output Strength Configuration Compensation Switch Control Input Configuration Output Configuration Comparator Mode Comparator Configuration Comparator Interrupt Deep-Sleep Mode Operation Register Summary LCD Direct Drive Features LCD Segment Drive Overview Drive Modes PWM Drive Digital Correlation Recommended Usage of Drive Modes Digital Contrast Control PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

15 Contents 22.3 Block Diagram How it Works High-Speed and Low-Speed Master Generators Multiplexer and LCD Pin Logic Display Data Registers Register List CapSense Features Block Diagram How It Works CapSense CSD Sensing GPIO Cell Capacitance to Current Converter CapSense Clock Generator Sigma Delta Converter CapSense CSD Shielding CMOD Precharge General-Purpose Resources: IDACs and Comparator Register List Temperature Sensor Features How it Works Temperature Sensor Configuration Algorithm Registers Section F: Program and Debug 325 Top Level Architecture Program and Debug Interface Features Functional Description Serial Wire Debug (SWD) Interface SWD Timing Details ACK Details Turnaround (Trn) Period Details Cortex-M0 Debug and Access Port (DAP) Debug Port (DP) Registers Access Port (AP) Registers Programming the PSoC 4 Device SWD Port Acquisition Primary and Secondary SWD Pin Pairs SWD Port Acquire Sequence SWD Programming Mode Entry SWD Programming Routines Executions PSoC 4 SWD Debug Interface Debug Control and Configuration Registers Breakpoint Unit (BPU) Data Watchpoint (DWT) Debugging the PSoC 4 Device Registers PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 15

16 Contents 27. Nonvolatile Memory Programming Features Functional Description System Call Implementation Blocking and Non-Blocking System Calls Performing a System Call System Calls Silicon ID Configure Clock Load Flash Bytes Write Row Program Row Erase All Checksum Write Protection Non-Blocking Write Row Non-Blocking Program Row Resume Non-Blocking System Call Status Non-Blocking System Call Pseudo Code Glossary 349 Index PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

17 Section A: Overview This section encompasses the following chapters: Introduction chapter on page 19 Getting Started chapter on page 29 Document Construction chapter on page 31 Document Revision History Revision Issue Date Origin of Change ** June 27, 2014 PMAD New PSoC 4 BLE TRM *A December 19, 2014 UDYG *B June 29, 2015 UDYG Description of Change In the SCB chapter, updated the SCB_RX_CTRL register description and added MEDIAN bit in the SCB_RX_CTRL register. Removed the ENABLE bit of the SCB_TX_CTRL and SCB_RX_CTRL registers. Updated the procedure to configure SCB as UART IrDA interface. In the Introduction chapter, updated Figure 1-1 and Figure 1-2. Updated the CTBm section of the chapter to say that PSoC 42x7-BL has two CTBm blocks while PSoC 41x7-BL has one CTBm block. Corrected general grammatical errors. In the TCPWM chapter, added STOP power mode description to the Power Modes section. Corrected the GENERIC bit field in TCPWM_CNT_CTRL register to [15:8] in various places. In the LPCOMP chapter, updated the pin numbers for input pins of Comparator 1 to P0[4] and P0[5]. Added support for the PSoC 4 BLE 256KB flash family. Updated the device family name in the title. *C February 12, 2016 UDYG Added information on DMA support in the Introduction chapter and added the DMA chapter. Updated the BLESS chapter with information on support for Bluetooth 4.2-capable devices. *D May 30, 2017 SHEA Updated logo and copyright information PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 17

18 18 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

19 1. Introduction PSoC 4 is a programmable embedded system controller with an ARM Cortex -M0 CPU. It combines programmable analog, programmable interconnect, user-programmable digital logic, and commonly used fixed-function peripherals with a highperformance ARM Cortex-M0 subsystem. The PSoC 4xxx-BL family is based on the PSoC 4 architecture which supports Bluetooth. This is upward-compatible with larger members of PSoC 4. PSoC 4 devices have these characteristics: High-performance, 32-bit single-cycle Cortex-M0 CPU core BLE radio and subsystem On-chip BLE transceiver Link layer controller compliant with Bluetooth 4.2 Fixed-function and configurable digital blocks Programmable digital logic High-performance analog system Flexible and programmable interconnect Capacitive touch sensing (CapSense ) Low-power operating modes Sleep, Deep-Sleep, Hibernate, and Stop modes Direct memory access (DMA) This document describes each functional block of the PSoC device in detail. This information will help designers to create system-level designs. 1.1 Top Level Architecture Figure 1-1 shows the major components of the PSoC 41x7-BL4xx architecture and Figure 1-2 shows the major components of the PSoC 42x7-BL4xx architecture. Figure 1-3 shows the major components of the PSoC 41x8-BL4xx architecture and Figure 1-4 shows the major components of the PSoC 42x8-BL4xx architecture. Figure 1-5 shows the major components of the PSoC 41x8-BL5xx architecture and Figure 1-6 shows the same for PSoC 42x8-BL5xx architecture. PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 19

20 Introduction Figure 1-1. PSoC 41x7-BL4xx Family Block Diagram PSoC 41x7-BL 32-bit AHB-Lite System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches CPU & Memory Peripherals PCLK SWD/TC Cortex M0 24 MHz FAST MUL NVIC, IRQMX SPCIF FLASH 128 kb Read Accelerator SRAM 16 kb SRAM Controller System Interconnect (Single Layer AHB) ROM 8 kb ROM Controller Peripheral Interconnect (MMIO) Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test DFT Logic DFT Analog IOSS GPIO (5x ports) Programmable Analog SMX x1 SAR ADC (12-bit) CTBm x1 2x OpAmp 4x TCPWM CapSense 2x SCB-I2C/SPI/UART LCD 2x LP Comparator Port Interface & Digital System Interconnect (DSI) Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 2.4 GHz GFSK Radio 24MHz XO 32kHz XO LDO IO: Antenna/Power/Crystal Active/Sleep Deep Sleep Hibernate High Speed I/O Matrix 36x GPIOs IO Subsystem 20 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

21 Introduction Figure 1-2. PSoC 42x7-BL4xx Family Block Diagram PSoC 42x7-BL 32-bit AHB-Lite System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches CPU & Memory Peripherals PCLK SWD/TC Cortex M0 48 MHz FAST MUL NVIC, IRQMX SPCIF FLASH 128 kb Read Accelerator SRAM 16 kb SRAM Controller System Interconnect (Single Layer AHB) ROM 8 kb ROM Controller Peripheral Interconnect (MMIO) Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test DFT Logic DFT Analog IOSS GPIO (5x ports) Programmable Analog SMX x1 SAR ADC (12-bit) CTBm x2 2x OpAmp Programmable Digital UDB... x4 UDB 4x TCPWM CapSense 2x SCB-I2C/SPI/UART LCD Port Interface & Digital System Interconnect (DSI) 2x LP Comparator Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 2.4 GHz GFSK Radio 24MHz XO 32kHz XO LDO IO: Antenna/Power/Crystal Active/Sleep Deep Sleep Hibernate High Speed I/O Matrix 36x GPIOs IO Subsystem PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 21

22 Introduction Figure 1-3. PSoC 41x8-BL4xx Family Block Diagram PSoC 41x8-BL 32-bit AHB-Lite System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches CPU & Memory Peripherals PCLK SWD/TC Cortex M0 24 MHz FAST MUL NVIC, IRQMX SPCIF FLASH 256 kb Read Accelerator SRAM 32 kb SRAM Controller System Interconnect (Single Layer AHB) ROM 8 kb ROM Controller Peripheral Interconnect (MMIO) Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test DFT Logic DFT Analog IOSS GPIO (5x ports) Programmable Analog SMX x1 SAR ADC (12-bit) CTBm x1 2x OpAmp 4x TCPWM CapSense 2x SCB-I2C/SPI/UART LCD 2x LP Comparator Port Interface & Digital System Interconnect (DSI) Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 2.4 GHz GFSK Radio 24MHz XO 32kHz XO LDO IO: Antenna/Power/Crystal Active/Sleep Deep Sleep Hibernate High Speed I/O Matrix 36x GPIOs IO Subsystem 22 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

23 Introduction Figure 1-4. PSoC 42x8-BL4xx Family Block Diagram PSoC 42x8-BL 32-bit AHB-Lite System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches CPU & Memory Peripherals PCLK SWD/TC Cortex M0 48 MHz FAST MUL NVIC, IRQMX SPCIF FLASH 256 kb Read Accelerator SRAM 32 kb SRAM Controller System Interconnect (Single Layer AHB) ROM 8 kb ROM Controller Peripheral Interconnect (MMIO) Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test DFT Logic DFT Analog IOSS GPIO (5x ports) Programmable Analog SMX x1 SAR ADC (12-bit) CTBm x2 2x OpAmp Programmable Digital UDB... x4 UDB 4x TCPWM CapSense 2x SCB-I2C/SPI/UART LCD Port Interface & Digital System Interconnect (DSI) 2x LP Comparator Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 2.4 GHz GFSK Radio 24MHz XO 32kHz XO LDO IO: Antenna/Power/Crystal Active/Sleep Deep Sleep Hibernate High Speed I/O Matrix 36x GPIOs IO Subsystem PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 23

24 Introduction Figure 1-5. PSoC 41x8-BL5xx Family Block Diagram CPU Subsystem PSoC 41x8-BL5xx 32-bit AHB-Lite SWD/TC FAST MUL NVIC, IRQMUX SPCIF Read Accelerator SRAM Controller ROM Controller Initiator/MMIO System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches PCLK System Interconnect (Multi Layer AHB) Peripheral Interconnect (MMIO) Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test Digital DFT Analog DFT Programmable Analog SAR ADC (12-bit) SARMUX x1 CTBm x1 2x OpAmp Port Interface & Digital System Interconnect (DSI) Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 2.4 GHz GFSK Radio 24MHz XO 32kHz XO LDO I/O: Antenna/Power/Crystal Power Modes Active/Sleep DeepSleep Hibernate IO Subsystem 24 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

25 Introduction Figure 1-6. PSoC 42x8-BL5xx Family Block Diagram CPU Subsystem PSoC 42x8-BL5xx 32-bit AHB-Lite SWD/TC FAST MUL NVIC, IRQMUX SPCIF Read Accelerator SRAM Controller ROM Controller Initiator/MMIO System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches System Interconnect (Multi Layer AHB) PCLK Peripheral Interconnect (MMIO) Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test Digital DFT Analog DFT Programmable Analog SAR ADC (12-bit) SARMUX x1 CTBm x2 2x OpAmp Programmable Digital UDB... x4 UDB Port Interface & Digital System Interconnect (DSI) Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 2.4 GHz GFSK Radio 24MHz XO 32kHz XO LDO I/O: Antenna/Power/Crystal Power Modes Active/Sleep DeepSleep Hibernate IO Subsystem 1.2 Features The PSoC 4xxx-BL family has these major components: BLE radio and subsystem 32-bit Cortex-M0 CPU with single-cycle multiply, delivering up to 43 DMIPS at 48 MHz Up to 256 KB flash and 32 KB SRAM Direct memory access (DMA) Four independent center-aligned pulse-width modulators (PWMs) with complementary, dead-band programmable outputs Twelve-bit SAR ADC (with a sampling rate of 1 Msps in PSoC 42xx-BL and 806 ksps in PSoC 41xx-BL) with hardware sequencing for multiple channels Up to four opamps that can be used for analog signal conditioning and as a comparator Two low-power comparators Two serial communication blocks (SCB) that can work as SPI, UART, I 2 C, and local interconnect network (LIN) slave serial communication channels Up to four programmable logic blocks, known as universal digital blocks (UDBs) CapSense Segment LCD direct drive Low-power operating modes: Sleep, Deep-Sleep, Hibernate, and Stop Programming and debugging system through serial wire debug (SWD) Fully supported by PSoC Creator IDE tool 1.3 CPU System Processor The heart of the PSoC 4 is a 32-bit Cortex-M0 CPU core running up to 48 MHz for PSoC 42xx-BL and 24 MHz for PSoC 41xx-BL. It is optimized for low-power operation with extensive clock gating. It uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This instruction set enables fully compatible binary upward migration of the code to higher performance processors such as Cortex M3 and M4. The CPU has a hardware multiplier that provides a 32-bit result in one cycle. PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 25

26 Introduction Interrupt Controller The CPU subsystem includes a nested vectored interrupt controller (NVIC) with 32 interrupt inputs and a wakeup interrupt controller (WIC), which can wake the processor from Deep-Sleep mode. The Cortex-M0 CPU of PSoC 4 implements a non-maskable interrupt (NMI) input, which can be tied to digital routing for general-purpose use Direct Memory Access The DMA engine is capable of independent data transfers anywhere within the memory map (peripheral-to-peripheral and peripheral-to/from-memory) with a programmable descriptor chain. Note: DMA is available only in PSoC 41x8-BL5xx and PSoC 42x8-BL5xx families. 1.4 Memory The PSoC 4 memory subsystem consists of flash and SRAM. A supervisory ROM, containing boot and configuration routines, is also present Flash The PSoC 4 has a flash module, with a flash accelerator tightly coupled to the CPU, to improve average access times from the flash block. The flash accelerator delivers 85 percent of single-cycle SRAM access performance on an average SRAM The PSoC 4 provides SRAM, which is retained during Hibernate mode. 1.5 System-Wide Resources Clocking System The clocking system for the PSoC 4 device consists of the internal main oscillator (IMO) and internal low-speed oscillator (ILO) as internal clocks and has provision for an external clock, external crystal oscillator (ECO), and watch crystal oscillator (WCO). The IMO with an accuracy of ±2 percent is the primary source of internal clocking in the device. Multiple clock derivatives are generated from the main clock frequency to meet various application needs. The ILO is a low-power, less accurate oscillator and is used as a source for LFCLK, to generate clocks for peripheral operation in Deep-Sleep mode. Its clock frequency is 32 khz with ±60 percent accuracy. An external clock source ranging from 0 MHz to 48 MHz can be used to generate the clock derivatives for the functional blocks instead of the IMO. The ECO is used to generate a highly accurate 24-MHz clock without any external components. It is primarily used to clock the BLE subsystem, which contains the Link Layer engine, the digital PHY modem, and the RF transceiver. The high-accuracy ECO clock can also be used as a clock source for the PSoC 4 device. The WCO is used as a source for LFCLK. WCO is used to accurately maintain the time interval of advertising events and connection events during Deep Sleep mode. Similar to the ILO, WCO is also available in all modes, except Hibernate and Stop modes Power System The PSoC 4 operates with a single external supply in the range 1.71 V to 5.5 V. PSoC 4 has four low-power modes Sleep, Deep-Sleep, Hibernate, and Stop in addition to the default Active mode. In Active mode, the CPU runs with all the logic powered. In Sleep mode, the CPU is powered off with all other peripherals functional. In Deep-Sleep mode, the CPU, SRAM, and high-speed logic are in retention; the main system clock is OFF while the low-frequency clock is ON and the low-frequency peripherals are in operation. In Hibernate mode, even the low-frequency clock is OFF and low-frequency peripherals stop operating. Multiple internal regulators are available in the system to support power supply schemes in different power modes GPIO Every GPIO in PSoC 4 has the following characteristics: Eight drive strength modes Individual control of input and output disables Hold mode for latching previous state Selectable slew rates Interrupt generation edge triggered CapSense and LCD drive support PSoC 4 also has two over-voltage tolerant ports, which enable I2C Fast Mode power down specification compliance and have the ability to connect to higher voltage buses while operating at lower V DD. The pins are organized in a port that is 8-bit wide. A highspeed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Pin locations for fixedfunction peripherals are also fixed. 26 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

27 Introduction 1.6 Bluetooth Low-Energy Subsystem PSoC 4xxx Bluetooth Low-Energy (BLE) subsystem integrates the RF transceiver, digital PHY modem, and link layer controller RF Transceiver The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50-ohm antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the antenna to a 1-MHz intermediate frequency and digitizes the analog signal to 10- bit digital signal. In the transmit direction, this block takes 1 Mbps GFSK modulated from digital PHY, up-converts it to radio frequency, and transmit it to air through antenna Digital PHY Modem In the transmit direction, this sub-block takes the 1-Mbps serial data from the link layer controller, generates GFSK direct modulated data, and sends it to the BLE analog section. On the receive side, it takes the 1-MHz IF ADC data from the BLE analog section and uses digital demodulator to generate the 1-Mbps serial data Link Layer Controller The link layer controller implements all timing critical functions specified in the Bluetooth Low-Energy Link Layer specifications (packet framing/de-framing, CRC generation/ checking, encryption/decryption, state machines, and packet transmission); it also provides interface to the digital PHY. The communication between link layer hardware and firmware is done through interrupt, FIFO, and registers. 1.7 Programmable Digital The PSoC 42xx-BL has up to four UDBs. Each UDB contains structured data-path logic and uncommitted PLD logic with flexible interconnect. The UDB array provides a switched routing fabric called the digital signal interconnect (DSI). The DSI allows routing of signals from peripherals and ports to and within the UDBs. The UDB arrays in PSoC 42xx-BL enable custom logic or additional timers/pwms and communication interfaces such as I 2 C, SPI, I2S, and UART. Note PSoC 41xx-BL does not have UDBs. 1.8 Fixed-Function Digital Timer/Counter/PWM Block The Timer/Counter/PWM block consists of four 16-bit counters with user-programmable period length. The functionality of these counters can be synchronized. Each block has a capture register, period register, and compare register. The block supports complementary, dead-band programmable outputs. It also has a kill input to force outputs to a predetermined state. Other features of the block include centeraligned PWM, clock prescaling, pseudo random PWM, and quadrature decoding Serial Communication Blocks The device has two SCBs. Each SCB can implement a serial communication interface as I 2 C, UART, local interconnect network (LIN) slave, or SPI. The features of each SCB include: Standard I 2 C multi-master and slave function Standard SPI master and slave function with Motorola, Texas Instruments, and National (MicroWire) mode Standard UART transmitter and receiver function with SmartCard reader (ISO7816), IrDA protocol, and LIN Standard LIN slave with LIN v1.3 and LIN v2.1/2.2 specification compliance EZ function mode support for SPI and I 2 C with 32-byte buffer 1.9 Analog System SAR ADC PSoC 42xx-BL has a configurable 12-bit 1-Msps SAR ADC and PSoC 41xx-BL has a similar 12-bit SAR ADC with 806 ksps. The ADC provides three internal voltage references (V DDA, V DDA /2, and V REF ) and an external reference through a GPIO pin. The SAR hardware sequencer is available, which scans multiple channels without CPU intervention Continuous Time Block mini The Continuous Time Block mini (CTBm) provides continuous time functionality at the entry and exit points of the analog subsystem. The CTBm has two highly configurable and high-performance opamps with a switch routing matrix. The opamps can also work in comparator mode. PSoC 42xx-BL has two such CTBm blocks, while PSoC 41xx-BL has one CTBm block. The block allows open-loop opamp, linear buffer, and comparator functions to be performed without external components. PGAs, voltage buffers, filters, and trans-impedance amplifiers can be realized with external components.ctbm block can work in Active, Sleep, and Deep-Sleep modes Low-Power Comparators The PSoC 4xxx-BL has a pair of low-power comparators, which can operate in all device power modes. This functionality allows the CPU and other system blocks to be disabled PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 27

28 Introduction while retaining the ability to monitor external voltage levels during low-power modes. Two input voltages can both come from pins, or one from an internal signal through the AMUX- BUS Special Function Peripherals LCD Segment Drive The PSoC 4 has an LCD controller, which can drive up to four commons and every GPIO can be configured to drive common or segment. It uses full digital methods (digital correlation and PWM) to drive the LCD segments, and does not require generation of internal LCD voltages CapSense PSoC 4 devices have the CapSense feature, which allows you to use the capacitive properties of your fingers to toggle buttons and sliders. CapSense functionality is supported on all GPIO pins in PSoC 4 through a CapSense Sigma-Delta (CSD) block. The CSD also provides waterproofing capability IDACs and Comparator The CapSense block has two IDACs and a comparator with a 12-V reference, which can be used for general purposes, if CapSense is not used Program and Debug PSoC 4 devices support programming and debugging features of the device via the on-chip SWD interface. The PSoC Creator IDE provides fully integrated programming and debugging support. The SWD interface is also fully compatible with industry standard third-party tools Device Feature Summary Table 1-1 shows the PSoC 41xx-BL/42xx-BL device summary. Table 1-1. PSoC 41xx-BL/42xx-BL Device Summary Feature PSoC 41xx-BL PSoC 42xx-BL Maximum CPU Frequency 24 MHz 48 MHz Flash PSoC 41x7-BL: 128 KB PSoC 42x7-BL: 128 KB PSoC 41x8-BL: 256 KB PSoC 42x8-BL: 256 KB SRAM PSoC 41x7-BL: 16 KB PSoC 42x7-BL: 16 KB PSoC 41x8-BL: 32 KB PSoC 42x8-BL: 32 KB GPIOs (maximum) CapSense Available Available LCD Driver Available Available Timer, Counter, PWM (TCPWM) 4 4 Serial Communication Block (SCB) 2 2 Universal Digital Block (UDB) Not Available 4 IDAC (part of CapSense) 2 2 Opamp 2 4 Comparator 2 2 ADC 12-bit SAR, 806 ksps 12-bit SAR, 1 Msps Bluetooth Available Available 28 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

29 2. Getting Started 2.1 Support Free support for PSoC 4 products is available online at Resources include training seminars, discussion forums, application notes, PSoC consultants, CRM technical support , knowledge base, and application support engineers. For application assistance, visit or call Product Upgrades Cypress provides scheduled upgrades and version enhancements for PSoC Creator free of charge. Upgrades are available from your distributor on DVD-ROM; you can also download them directly from Critical updates to system documentation are also provided in the Documentation section. 2.3 Development Kits The Cypress Online Store contains development kits, C compilers, and the accessories you need to successfully develop PSoC 4 BLE projects. Visit the Cypress Online Store website at Under Products, click Programmable System-on-Chip to view a list of available items. Development kits are also available from Digi-Key, Avnet, Arrow, and Future. 2.4 Application Notes Refer to application note AN Getting Started with PSoC 4 BLE for additional information on PSoC 4 BLE device capabilities and to quickly create a simple BLE application using PSoC Creator and BLE development kit. PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 29

30 Getting Started 30 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D

31 3. Document Construction This document includes the following sections: Section B: CPU System on page 35 Section C: System Resources Subsystem (SRSS) on page 67 Section D: Digital System on page 117 Section E: Analog System on page 245 Section F: Program and Debug on page Major Sections For ease of use, information is organized into sections and chapters that are divided according to device functionality. Section Presents the top-level architecture, how to get started, and conventions and overview information of the product. Chapter Presents the chapters specific to an individual aspect of the section topic. These are the detailed implementation and use information for some aspect of the integrated circuit. Glossary Defines the specialized terminology used in this technical reference manual (TRM). Glossary terms are presented in bold, italic font throughout. Registers Technical Reference Manual Supplies all device register details summarized in the technical reference manual. This is an additional document. 3.2 Documentation Conventions This document uses only four distinguishing font types, besides those found in the headings. The first is the use of italics when referencing a document title or file name. The second is the use of bold italics when referencing a term described in the Glossary of this document. The third is the use of Times New Roman font, distinguishing equation examples. The fourth is the use of Courier New font, distinguishing code examples Register Conventions Register conventions are detailed in the PSoC 4100-BL/4200-BL Family: PSoC 4 BLE Registers TRM Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase h (for example, 14h or 3Ah ) and hexadecimal numbers may also be represented by a 0x prefix, the C coding convention. Binary numbers have an appended lowercase b (for example, b or b ). Numbers not indicated by an h or b are decimal. PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D 31

32 Document Construction Units of Measure This table lists the units of measure used in this document. Table 3-1. Units of Measure Abbreviation Unit of Measure bps bits per second C degrees Celsius db decibels dbm decibels-milliwatts ff femtofarads G Giga Hz Hertz k kilo, 1000 K kilo, 2^10 KB 1024 bytes, or approximately one thousand bytes Kbit 1024 bits khz kilohertz (32.000) k kilohms MHz megahertz M megaohms µa microamperes µf microfarads µs microseconds µv microvolts µvrms microvolts root-mean-square ma milliamperes ms milliseconds mv millivolts na nanoamperes ns nanoseconds nv nanovolts ohms pf picofarads pp peak-to-peak ppm parts per million SPS samples per second sigma: one standard deviation V volts Acronyms This table lists the acronyms used in this document Table 3-2. Acronyms Acronym Definition ABUS analog output bus AC alternating current ADC analog-to-digital converter ADV advertising Table 3-2. Acronyms (continued) Acronym AES AHB API APOR BC BLE BLESS BOD BOM BR BRA BRQ CAN CI CMP CO CPU CRC CSD CT CTB CTBm DAC DAP DC DI DMA DNL DO DSI DSM DW ECO EEPROM EMIF FB FIFO FSR GAP GATT GFSK GPIO HCI HFCLK HSIOM Definition Advanced Encryption Standard AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus application programming interface analog power-on reset broadcast clock Bluetooth Low Energy (Bluetooth Smart) BLE subsystem brownout detect bill of materials bit rate bus request acknowledge bus request controller area network carry in compare carry out central processing unit cyclic redundancy check CapSense sigma delta continuous time continuous time block continuous time block mini digital-to-analog converter debug access port direct current digital or data input direct memory access differential nonlinearity digital or data output digital signal interface deep-sleep mode data wire external crystal oscillator electrically erasable programmable read only memory external memory interface feedback first in first out full scale range generic access profile generic attribute profile Gaussian frequency-shift keying general purpose I/O host-controller interface (BLE stack) high-frequency clock high-speed I/O matrix 32 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No Rev. *D